Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.


Introduction
The intense development of channel engineering and manufacturing technology to obtain better efficiency has successfully driven continued device scaling. As the dimensions of the semiconductor devices are continually shrinking, control gate loses its sway over the channel, leading to diverse Short Channel Effects (SCEs). In order to further enhance the device efficiency in terms of reduced SCEs [1], engineers in the field of nanotechnology have been researching and looking for new device architectures. In this concern, Junctionless FETs (JLFETs) [2][3][4][5] have been the most influential device in rendering decreased SCEs, high ON -OFF current ratio and almost ideal subthreshold slope (SS ∼ 60 mV/dec). The aforementioned benefits of JLFETs are possible due to the absence of gradient doping concentration. The uniform doping helps the JLFETs to eliminate the formation of source/channel and channel/drain junctions.
In addition to JLFETs, the subthreshold swing of the Tunnel FET (TFET) is less than 60 mV/dec, which is the substantial limit of the MOSFET [6]. On top of it, Junctionless Tunnel FETs [7,8] and the concept of gate material [9][10][11][12] engineering is another tangible solution to reduce the SCEs. In this process of improving the reliability of device, Germanium (Ge) based TFETs [13][14][15] with enhanced oxide interface can serve as a supreme solution for minimizing the control gate leakage current.
Silicon (Si) based Tunnel FETs with silicon dioxide, turned out to perform with poor electrostatics and deserved a huge gate to source voltage for tunneling FET's to operate. Above this, because of the outpouring of electrons through the poor insulation layer, the leakage current will reach a high value, exceeding 1 A/cm 2 at 1 V [16]. The analytical model for junctionless DMDG FET [10] is proposed, but the aggregate advantages of Ge, High-K gate dielectric [17][18][19][20][21][22][23] (Titanium Oxide -TiO 2 ), and triple material gate work function engineering has not been explored in short channel (12 nm) junctionless surrounding gate tunnel FETs [24][25][26]. Also, from the application perspective the design of SRAM memory cell has been explored in the literature using various conventional FETs. Here, to extend the proposed Ge-TMSG-JLTFET for low power applications, design of 6 T SRAM has been explored [27][28][29].Therefore, the foremost objective of developing a 2-D mathematical model for Triple Material Surrounding Gate (TMSG) Junctionless TFET (JLTFET) with Germanium (Ge) and High-K gate dielectric materials is of great interest.
In view of all the above-mentioned details, an analytical model for junctionless surrounding gate TFETs with Ge, high-K gate dielectric and gate metal engineering has been demonstrated. In order to observe the short channel effects, the surface potential and electric field are critical components and can be estimated by solving the 2-D Poisson's equation by parabolic approximation. The design of 6 T SRAM using Ge-TMSG-JLTFET has been explored to analyze the subthreshold leakage power / memory cell for utilizing in low power applications. The extracted results from the mathematical approach are checked with the results of JLTFETs based on traditional Silicon technology. Furthermore, the findings of the analytical model, with TCAD results, are also verified.

Mathematical Modeling
The schematic, 3D and mesh profile view of the proposed device (Ge-TM-SG-JL-TFET) is presented in Fig.1. The gate electrode is made of three M_ 1 , M_ 2 and M_ 3 materials with their gate lengths to be L_ 1 , L_ 2 and L_ 3 . The total gate length (L = 12 nm) is expressed as L = L_ 1 + L_ 2 + L_ 3 .
Tunneling gate metalsM_ 1 , M_ 2 and M_ 3 havework functions of φ M _ 1 = 4.8 eV (Au), φ M _ 2 = 4.6 eV (Mo), φ M _ 3 = 4.4 eV (Ti). The three different materials for the gate metal are chosen in such a way thatφ M _ 1 > φ M _ 2 > φ M _ 3 . There is a 12 nm germanium channel in the proposed model, which is strongly doped with ntype material of10 19 cm −3 . The regions of source and drain are uniformly doped on the germanium channel.
The potential distribution in the channel is expressed using 2-D Poisson's equation, where φ(r, z)-2-D profile of the potential, q -charge of an electron, N d -uniform channel -doping concentration and ε Gegermanium permittivity.
A straightforward parabolic function is utilized to align the potential in the vertical direction, which is shown as below [30][31], where Y 1 (z), Y 2 (z) and Y 3 (z) are approximate functions of z only.
The Poisson's equation is solved independently using the boundary conditions listed below; (a) The surface potential as a function of z is denoted as; (b) At the center of the germanium pillar, the electric field is zero.
(c) At the interface of the gate and gate dielectric layer, the electric field is continuous.
(d) The source and drain end potentials are; Where, V G-t-S -Gate to source bias, E GB -Energy band gap of germanium, χ ea -Electron affinity of germanium, φ M i -Gate metal work functions and V bip -built-in potential.
For the three gate metal regions, the flat-band voltages are: Where, φ M _ 1 , φ M _ 2 and φ M _ 3 are the work functions of individual gate materials and φ Ge is the germanium work function.

Surface Potential
In this structure, as the control gate metal has three regions, the potential underneath each region are as follows; where,Y 1 (z), Y 2 (z) and Y 3 (z) are found using the boundary conditions (3)(4)(5).
On substitution of these above functions in (2), we obtain; Substituting (13) where, C i and D i used in (16) are as follows;

Lateral & Vertical Electric Field
The electric -field at the drain end intruding into the channel is one of the most remarkable reasons for devices to degrade at shorter channel lengths of 12 nm. This is supposed to have an adverse effect on the performance of the device. Hence, estimation of electricfield components becomes essential and is found by a simple differentiation of surface potential. Components of the electric -field LE i (z) , lateral electric -field and VE r (z), vertical electric -field are represented as:

Threshold Voltage
As the electric field approaches zero, it indicates that there is a minimal electrostatic potential. Also, when this minimum potential beneath the gate metal region M_ 1 approaches zero, the value of threshold -voltage may beset equivalent to the value of control -gate bias. The mathematical equations are expressed below; where, Incorporating this potential minimum underneath control gate -metal region M_ 1 , as two times the bulk -potential and equating V G-t-S =V threshold , the final expression for threshold -voltage is represented as,

Results and Discussions
The complete mathematical model presented is verified against3-D TCAD device simulator. Shockley-Read-Hall (SRH) recombination model combined with Auger In addition to this, to analyze the transport mechanism of the carriers in device simulation, model of Drift Diffusion (DD) has also been included.
The total channel length of the device is considered to be 12 nm. The main device parameters such as thickness of the germanium channel (t ge ) and dielectric layer thickness (t ox ) are predefined to be 2 nm and 1 nm. Table 1 describes the specification of design parameters used for simulation purpose. Figure 2 indicates the surface potential contrast of both Ge-TMSG-JLTFET and Si-TMSG-JLTFET. The proposed Ge based TMSG-JLTFET has incorporated the effect of high-K material and renders superior value of surface potential compared to Si based device with silicon dioxide as their gate -oxide material.
The surface potential distribution noticed in Fig. 3 in the daintily doped drain tends to increase as the length of the channel increases. But it is obvious that the potential is considerably less for thinner t ox = 1 nm oxide thickness, relative to t ox = 2 nm. In addition to this, a significant shift in potential is ascertained at the interface of the three gate metals due to varying work functions in the device. This transition in step is critically important for increasing the speed of the carriers and also for enhancing the efficiency of carrier transport. Figure 4 depicts the surface potential trace of Ge-TMSG-JLTFET for distinct values of germanium thickness. It is clearly visible that, as the thickness of germanium decreases, the value of potential also decreases. This minimum potential shifts towards the source side, thus manifesting that applied gate bias has a high impact on the tunneling generation rate at the source end. The validity of the proposed analytical model is ascertained with TCAD results. Figure 5 illustrates that lateral electric -field near tunneling junction (i.e. drain side) is condensed. It is also perceived that as drain-to-source voltage decreases, the value of lateral electric field is also reduced. Figure 6 outlines the distinction of lateral electric field between Ge-TMSG-JLTEFT and Si-TMSG-JLTFET for distinct values of oxide thickness. Due to thinner oxide thickness (tox = 1 nm) and high-K dielectric material used (Titanium Oxide), the crest of the lateral electric -field is towards the source side. It is a clear notion that the Drain Induced Barrier Lowering (DIBL) is considerably reduced for Ge-TMSG-JLTFETs. But in case of Si-TMSG-JLTFET, a peak electric -field at the drain end may end up in constitution of extremely energetic and active "Hot Carriers". These carriers can get lodged in the insulation region and root causes the device to just be weakened. Therefore, by shortening the thickness of the gate oxide layer, we can surmount the SCEs and strengthen the reliability.
The vertical electric field variance of Ge-TMSG-JLTEFT is illustrated in Fig.7 with various values of V ds = 0.3 V and 0.5 V. The figure clearly demonstrates that a shift in the potential profile causes the electric -field lines at the intersection of three gate metals also to change. Independent gate metals are positioned so that the material has a lower work -function on the drain side than on the source side. The electrons near the source are then accelerated more strongly, leading to advancements in performance of the device. It is also inferred that the vertical electric field portion is minimal on the drain side with V ds = 0.3 V and along the channel it becomes highly consistent. The model described here appears to match the data obtained from the TCAD simulation.
The comparisons of the Ge-TMSG-JLTFET and Si-TMSG-JLTFET vertical electric field patterns are included in Fig. 8. The vertical field aspect of both models is minimal for thinner oxide thicknesses. However, for the proposed Ge-TMSG-JLTFET analytical model with titanium oxide as the dielectric gate, the strength of the electric field is better. With thin silicon dioxide layer, electrons can swiftly drift across the dielectric material and causes the gate threshold voltage to alter. Once threshold voltage is altered, this will lead to problems with instability in the structures of the device.
The threshold voltage variance of Ge-TMSG-JLTFET is shown in Figs. 9 and 10 for particular values of impurity doping concentration. It is visible that there is a decline in threshold voltage demonstrating a decrease in short channel effects for a given channel doping. Lower voltage circuits thereby look very attractive for mainstream memory applications which require low power and low leakage current.
Germanium-based TM-SG-JL-TFET ambipolar features are contrasted with Si-TM-SG-JL-TFET and Si-SM-SG-JL-TFET, and the system output restricting the ambipolarity is  Fig. 11.The present structure exhibits greater ON current and reduces the ambipolar behavior due to the Ge based uniformly doped regions and high -K gate material compared to the equivalent structure of silicon based single and triple gate material. Analytical model results match well with Silvaco ATLAS TCAD simulator data and the precision of our ambipolar drain current model is verified.

6 T Ge-TM-SG-JL-TFET SRAM Design
A novel 6 T germanium-based TM-SG-JL-TFET SRAM has been introduced, which retains a sufficient number of transistors to form CMOS based memory cell is shown in Fig. 12.

Also, proposed 6 T -SRAM maintains a proper read and write noise margins (RNM & WNM).Our design is composed of cross-connected inverters (INVERTER 1 and INVERTER 2)
with BL and BLB bit lines connected to the Q node via T5 and T6 transistors. It is a programming technique that gives INVERTER 1 a virtual ground by writing "1" / "0" to node -Q. Simulated grounding technique tends to increase the WNM by disconnecting the cross-connected inverter (or decreasing the regenerative action).
Metrics utilized to contrast the output of distinct SRAM designs are read -write delays. The read -delay is characterized as time -delay amidst the activation of 50% of the word line (WL) to 10% of the difference in pre-charged voltage among the bit lines. The reading delay of various SRAM designs could be seen in Fig. 13. We infer that due to its high drive current, germanium-based TM-SG junctionless tunnel FETs outperform than CMOS-based SRAM design in the entire voltage range.
Delay in writing is measured as time between the 50% activation of the word line (WL) to 90% of its lower voltages when internal -Q is flipped. As shown in Fig. 14, the write delay of the proposed Ge-TM-SG-JL-TFET SRAM is substantially less than that of 6 T CMOS and Si TM SG JL-TFET. Because of the cross-connected inverter configuration along with the Ge-TM-SG-JL-TFET, this allows for a faster writing speed than other designs. 6 T CMOS and Si TM SG JL-TFET write delays are considerably higher than the proposed 6 T germanium-based TM-SG-JL-TFET design at V DD = 0.3 V. This is because of the utilization of germanium in the proposed device. One unique feature of germanium based transistors is that this indirect band gap material has a smaller energy band gap than silicon (Si). Larger the band gap, more energy is required to excite an electron from the valance band to the conduction band, and hence readwrite delays will be substantially higher for silicon based SRAM designs. Figure 15 depicts standby -leakage power per cell of various SRAM designs. The standby leakage power of 6 T

Conclusion
An analytical model for 12 nm germanium based triple -material surrounding -gate junctionless tunnel FET is presented. To validate and verify our model, the proposed mathematical expressions have been related with silicon based TMSG-JLTFET and also with the results extracted from 3-D Silvaco ATLAS TCAD simulator. Strong correlation is observed amidst the proposed mathematical model and TCAD simulation data. With these findings, it is well established that Ge-TMSG-JL-TFET resembles to be the assuring device for lowpower design of 6 T SRAM. The combined dominance of germanium, titanium oxide (high-K dielectric), three distinct gate metals and the surrounding gate structure in the proposed model will hold a significant role in the future electronic framework. Most of the On-chip memory technologies embed these kind of powerful lowleakage Ge-TMSG-JL-TFET based 6 T SRAM designs to mitigate the bottleneck involved in advanced scalable memory systems.
Funding The authors of the manuscript did not receive any funding, grants, or in-kind support in support of the research or the preparation of the manuscript.

Declarations
Conflict of Interest All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version. This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue. The authors have no affiliation with any organization with a direct orindirect financial interest in the subject matter discussed in the manuscript.
Ethical Approval "All procedures performed in studies involving human participants were in accordance with the ethical standards of the institutional and/or national research committee and with the 1964 Helsinki declaration and its later amendments or comparable ethical standards.
Informed Consent "Informed consent was obtained from all individual participants included in the study."