Low-cost defect simulation framework for analog and mixed signal (AMS) circuits with enhanced time-efficiency

Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space, and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods with reduced defect simulation time. In this work, we present a simple and time-efficient defect simulation framework for pre-silicon testing of AMS circuits. In our method, a given defect model is realized using Verilog-A modules and tests multiple defects in a circuit in a single-run simulation. In contrast to the conventional defect simulation framework, our method saves simulation time by avoiding repetitive work of generating a netlist for each defect and by reducing the time overhead for the simulator to interface with data/file-handling system. To strongly validate our proposed framework, diverse AMS circuits are considered such as operational amplifier (op amp), fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) and Successive-approximation-register (SAR) analog-to-digital converters (ADC). For DC testing schemes for op amp and LDO, we used intentional offset injection based testing scheme. With this method, we show that the proposed framework reduces the simulation time to less than one-tenth (1/10th ) in comparison with conventional framework for DC oriented defect simulation testing. On the other hand, for the transient testing scheme, the proposed framework reduces the simulation time to less than 50% of the conventional framework. Furthermore, we also show that there is no negative impact on the defect coverage using the proposed framework.


Introduction
Integrated Circuits (ICs) are becoming more and more complex which can be attributable to shrinking technologies, innovative circuit designs and advanced manufacturing techniques.Due to all these reasons, the number of device elements in ICs is increasing immensely which in turn increases the number of probable defects in ICs.This would in turn result in increased defect simulation time (hence increasing the cost).The testing for defects is very important especially for safety-critical applications such as in automotive, space and medical industries.Furthermore, it is a known fact that the number of ICs in automotive vehicles is increasing regularly as automotive designers constantly endeavor to embed more and more safety and infotainment features in vehicles.Moreover, with the constant increase in the market for electric vehicles, the number of electronic components can be expected to increase even further in coming years.The concept of Functional Safety, also known as FuSa, is very important in automotive industry [1] because a minimal defect in a vehicle can result in enormous repair costs or even worse can result in deadly accidents.This is one of the reasons why the mission-critical automotive industry contractually demands the chip manufacturers to have zero defective parts per million (0 DPPM) [2].These demands in turn result in a need for a high defect coverage requirement.
In addition to these expectations from the industry, the requirements from standards such as ISO26262 Standard for functional safety [3] recommends an automotive integrated circuit (IC) to have a very high defect coverage (usually greater than 90%) put additional emphasis on timeefficient defect screening techniques [4,5].Furthermore, as discussed, the circuits are becoming progressively more complex and integrated, the number of defects to be tested are also increasing proportionately which in turn increases the defect-simulation time.The concept of defect simulation testing is in a very advanced stage for digital circuits and is also automated in many cases.On the other hand, the defect simulation testing methods for analog and mixed signal circuits are still challenging due to their design complexity.Also, the fact that, in an SoC, the major portion of field returns are due to fails in analog circuits [6] stresses the need for increased defect coverage testing for analog circuits.Hence, due to all the stated reasons, the area of defect-oriented testing for AMS circuits is one of the hot topics [2,4].
As the number of probable defects to be tested is increasing day by day due to massive increase in the level of integration, the defect simulation time is also increasing proportionately.Additionally, the simulation time is extremely high to run defect-simulations on large AMS designs such as phase-locked-loops (PLLs), analog-to-digital converters (ADCs), digital-to-analog converter (DACs), and voltagecontrolled oscillators (VCOs).On top of this, if we need to perform defect-simulations for several test conditions and in Monte Carlo process/ mismatch corners, the overall simulation time may become excessively long [4].Hence, there is a need to develop ways to reduce defect simulation time.To address this issue, in this paper, we present an extremely simple defect simulation framework which increases the time-efficiency of defect simulations.To achieve time efficiency, we use Verilog-A based defect injection along with global control variables to enable several defects in different circuit elements and test defects using a single simulation run.By doing so, we avoid repetitive work of generating netlist for each defect and thereby reduce the time overhead for the circuit-simulator to interface with data/file-handling system.We also need to note that the framework proposed in this work is not a replacement but is complementary to the prevailing defect-simulation time-reduction strategies (such as in [7][8][9]) i.e., we can still use exiting time-reduction techniques in conjunction our framework to achieve additional time savings.
This paper is organized as follows.In Sect.2, the proposed framework is introduced with a sample defect model.In Sect.3.1, the defects in an operational amplifier are simulated using a DC testing scheme called Intentional Offset Injection method [10,11] using the proposed framework.In Sect.3.2, we use oscillation test method (OTM) [8], a predominantly transient detection scheme, to further corroborate the time-efficiency of our framework.We repeat the same exercise for fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) in Sect. 4. In Sect.5, a SAR ADC is tested using the proposed framework with the defecting testing method introduced in [24].This is followed by concluding remarks.

Conventional defect simulation framework
In this subsection, the conventional way of defect simulation is explained briefly.Figure 1 presents the simplified flowchart depicting the conventional defect simulation flow.As shown, the primary inputs to the framework are the netlist of the circuit under test (CUT) and the defect model.The next step is to modify the netlist for a given defect and run the defect simulation and this procedure is repeated sequentially until all the defects are tested.Once all the defects are tested, the defect results are analyzed to calculate the defect-coverage figures.

Proposed defect simulation framework
In our proposed defect simulation framework which is extension of work from [12], a global control variable is used to Fig. 1 Process flow for conventional defect simulation framework with netlist generation loop enable several defects in the CUT.By sweeping the control variable, the framework activates and test various defects in the circuit with just a single DC/transient simulation depending on the used defect simulation testing method.Figures 1  and 2 presents the simplified flow chart of the conventional simulation framework and the proposed simulation framework respectively.In conventional framework, the circuit netlist is generated recursively for each and every defect in the defect universe.In comparison with the conventional framework, the proposed framework avoids the repetitive work of generating netlist for each defect.This would directly translate to reduced simulation time.In addition to this, the proposed framework also reduces the time overhead for the simulator to interface with data/file-handling system.This reduced time-overhead would further increase the time efficiency of the defect simulation.

Netlist generation for defect-simulation testing
In this subsection, the process to convert a given circuit's netlist to a 'modified' netlist is presented which later will be used to simulate the defects.To illustrate the framework, the most commonly used six defects model shown in Fig. 3 is considered which is in compliance with the model prescribed in P2427 Standard for Analog Defect Modeling and Coverage [13,14].As depicted in Fig. 4, it can be noted that all six defects from the defect model can be realized using seven 'defect' resistors ( R DD ,R SS , R GG ,R GD ,R GS ,R DS ,R GG′′ ).Depending on the defect that needs to be activated, each of these defect resistors take values as tabulated in Table 1.
Let us understand the definitions of the defect resistors below: 1. R nml_short : Short in normal, defect-free operation.Ideal value is 0Ω .(Can be modelled using 0 V voltage source using VerilogA Command : v(p,n)->0) 2. R nml_open : Open in normal, defect-free operation.Ideal value is ∞Ω .(Modelled using 0 A current source using VerilogA Command : i(p,n)->0) 3. R flt_short : Short resistance in defect case.Its value would depend on the chosen defect model (usually 1 Ω − 100Ω).The main idea of the proposed framework is that if we can modify the netlist such a way that all the transistors are converted to "modified" transistors (as shown in Fig. 4), then all the defects in the defect model can be activated by modifying the resistor values as per the lookup table in Table 1.

Modelling of defect resistors
In this subsection, the modelling of the defect resistors is explained.As discussed earlier, the framework uses Verilog-A to model these defect resistors.To understand better, consider the defect resistor R DD as an example.Figure 5 shows simplified code of R DD resistor modelled in Verilog-A.
The terminals of the R DD module are: 1. p : positive terminal of the resistor 2. n : negative terminal of the resistor 3. c : control terminal 4. g : reference voltage node for control terminal The primary input parameters of the module are: 1. vc step : Step size of the control voltage 2. max dfcts : Maximum number of defects per transistor 3. dev id : Identifier for the device to be tested Now, let us define two variables.
• V cint = V c ∕vc step : This variable converts the control voltage into the defect number.• V cg_norm = V cint %max_dfcts : This variable denotes the defect number that needs to be activated in the given defect model A defect in a given transistor ( dev id ) is enabled if and only if the identifier dev id satisfies the below Eq.
To understand all these equations, let us consider an example.The maximum number of defects for our defect model is 6 (as shown in Fig. 3) i.e., max dfcts = 6 .Consider the step size of the control voltage, vc step = 1mV .Now, say the input control voltage V c = 7mV .Then, Furthermore, if we solve Eq. ( 1) for V cint = 7 then the value of device id is calculated as 2 i.e., dev id = 2 .In other words, the value V cint = 7 satisfies Eq. (1) for the device with identifier dev id = 2 .Hence, the framework activates the defect corresponding to V cg_norm to the device 2 i.e., the framework introduces Drain-Open (DO) defect in the device with identifier dev id = 2 .Hence, we need to assign R DD = R flt_open in that transistor as per the lookup table in Table 1.This can be observed in simulation waveform in Fig. 6.At V c = 7mV , R DD = R flt_open = 100MΩ.

Note All the 'opens' in the plots signify that the current across the resistance is zero (i.e., resistance = infinity) as realised using VerilogA command I(p,n) + > 0.
Similar to the Verilog-A model for R DD , all the other six 'defect' resistors ( R SS , R GG , R GD , R GS , R DS , R GG�� ) are mod- eled in accordance with the defect look up table in Table 1.After modeling all these 'defect' resistors, we convert each transistor in the netlist to a 'modified' transistor using these resistors'-based model as shown in Fig. 4.However, the readers need to note that, our new modified transistor have two more terminals ( c, g ) for control voltage to acti- vate defects.In addition to normal parameters of the transistor, the modified transistor would have these additional parameters:{max dfcts , dev id , vc step , R nml short , R nml_open , R flt_short , R flt_open } .Once all the transistors in the CUT are transformed (1) to the 'modified' transistors and each transistor is given a unique dev id , the framework can simulate all the defects just by controlling the global control voltage V c .We can also note that modelling these "modified" transistors is a one-time effort for a given technology.Once modelled, they can be used for different circuits in that technology.In this work, we just considered defects in transistors.However, one can also 'modify' other circuit components to realize defects by making Verilog-A models satisfying their corresponding truth tables as shown in Fig. 7a and b.Note that in our framework, the values of variables r_nml_short and r_nml_open are 0, infinity respectively as they are realized using 0V voltage source and 0A current source.Hence, they would have no impact on normal performance of the circuit.

Defect simulation: operational amplifier
In this section, consider an operational amplifier as the first AMS circuit under test (CUT) to validate the time-efficiency of the proposed framework.For this exercise, the defects in operational amplifier are simulated using two methods.
First method is predominantly a DC testing method known as intentional offset injection (IOI) method proposed in [10].
On the other hand, the second testing method is well known transient testing method called Oscillation Test Method (OTM) [15,16].

Circuit under test: operational amplifier
The first CUT that is under consideration is a two-stage operational amplifier as shown in Fig. 8a.It has a folded cascode amplifier as the first stage followed by a simple common source stage.This operational amplifier is designed in UMC65nm technology using 2.5 V I/O transistors.The Widlar current reference and the biasing circuitry shown in Fig. 9a and b generates the bias voltages ( V pt , V bp , V bn ) necessary for the operational amplifier.The the frequency response of the CUT with DC gain, phase margin and unity gain frequency for a typical corner is shown in Fig. 8c for both original CUT as well CUT with 'modified' transistors.
It can be noted that the performance of the original CUT is not affected with our framework.

Intentional offset injection methodoperational amplifier
The first test method used to simulate defects in the op amp using our framework is called the intentional offset injection (IOI) method first introduced in [10].In IOI method, either a positive (or negative) offset is injected into the circuit as a control signal by closing the switches M pt (or M nt ).The output of the op amp is expected to go close to Vdd when positive offset is injected and is expected to go to Vss when negative offset is injected.This is tested using the detector's output V amp_check .Hence, if a defect in the op amp violated this, then that defect is considered detected (See ).To get a single 'High' output for the defect free case, Detector1 is placed to generate V ampcheck which follow below equations.

Negative offset injection
While the intentional offset injection tests the main circuit of the operational amplifier, the defects in the widlar reference and biasing circuit are tested using three digital window comparators [10] as shown in Fig. 9c.The outputs of all these window detectors would be high in a defectfree situation.However, if any defect in either Widlar current reference or biasing circuit triggers any of the window detector outputs to go low, then that defect is marked detected.Furthermore, the outputs of all the detectors ( V ampcheck , V pt_wc , V bp_wc ,V bn_wc ) are sent to an AND gate and the final reliability output, V rel is generated (See Fig. 9d).In a defect-free case, V rel should be High and in a defect-case, V rel is expected to go low if that defect is detectable (See Table 2).The table also contains the detector output values for an example defect (Source-Drain short in MPTL transistor in the op amp).

Defect detection of operational amplifier using IOI with proposed framework
In this subsection, let us simulate the defects in operational amplifier with the proposed framework to demonstrate the time efficiency of the proposed method in comparison with conventional framework.The first step is to convert all the transistors into "modified" transistors as explained in Sect. 2. For this exercise, the dev id parameter is assigned according to its name in the Fig. 8i.e., a transistor M x would have its dev id = x .Next step is to set the required input conditions ( V P = V N = V CM ) to check the defect coverage.Then, by set- ting V os_pos = HighandV os_neg = Low , the CUT enter positive injection test case.Next step is to sweep the control voltage V c ( V c is not shown in the schematic) to test defect coverage for positive injection case.The defects that would be detected in the positive IOI test would trigger the reliability output V rel to 0 (See third waveform in Fig. 10).Once positive injec- tion test is completed, the same procedure is repeated for the negative IOI test by setting V os_pos = Low;V os_neg = High .Similar to positive injection test, the defects that would be detected in the negative IOI test would trigger the reliability output V rel to 0 (See fourth waveform in Fig. 10).In the end, a defect is marked as detected if that defect makes V rel = 0 at least in one of positive or negative IOI tests.Hence, with our proposed framework, just two DC sweep simulations need be performed, one for positive IOI and one for negative IOI, to simulate all 150 (25 transistors×6 defect per transistor) defects in the circuit.The V rel outputs for these two simulations for positive and negative injection cases are labelled as V rel_pos_inj and V rel_neg_inj respectively (see Fig. 10).These two outputs are then ANDed to get the final reliability digital output V rel_IOI .For a defect-free case, V rel_IOI = 1 .As discussed, if an acti- vated defect results in making V rel_IOI to '0', then that defect is marked as detected.Therefore, it can be seen from Fig. 10 that some of the activated defects are detected, and some are not detected.Furthermore, we need to note that some of the 'undetected' defects are expected not to be detected.As an example, consider a Gate-Drain (GD) short defect for transistor M 14 .As the defect-free circuit itself has a diode connection between gate and drain for M 14 , that defect even when injected is not detected.Hence, the defects of this kind are marked as detected for our consideration.
Table 3 gives a performance comparison between conventional framework and the proposed framework for op amp testing using IOI method.The time -efficiency of our method can be understood clearly by comparing the simulation time.While the conventional framework takes around 172 s to simulate all the 150 defects, the proposed framework takes just about 16 s to simulate the same.In other words, our framework provides a time saving factor of ~ 10 times in comparison with the conventional framework.All the simulation times in the tables are an average for 10 simulation runs.

Defect detection of operational amplifier using OTM with proposed framework
In this subsection, using oscillation test method as testing method, let us understand the time-efficiency of the proposed method.Oscillation test method (OTM) is a prominent defect detection methodology in which a circuit under test is converted into an oscillator and once converted, the oscillation frequency is compared to the expected frequency of a defect-free circuit [15,16].The IOI discussed in the previous section is predominantly a DC-based testing method.In comparison, the OTM method is a transient testing scheme.For this defect simulation, the same operational amplifier tested in the previous section is used (Figs. 8 and  9), except that the new circuit would not have the IOI control circuitry (brown-dotted transistors at the input pair) as well as IOI detectors.To convert the operational amplifier into an oscillator a positive feedback circuit (R, C) is used as shown in Fig. 11.
The values of resistors and capacitors are chosen in such a way that sustained oscillations are achieved at 6 MHz.This can be seen in the inset graph in Fig. 13., showing oscillations at V out_osc zoomed in for the first 10µs of simulation which covers the defect-free case.To start simulating the defects, the control voltage V c is swept in steps of V c_inc =1mV (See V c in Fig. 13).The oscillator is tested for 10µs for each defect.Therefore, the total simulation time of 1510µs to test 150 defects including an initial 10µs for the defect-free case.For our defect-simulation testing, a detection tolerance range of ±10% is considered.In other words, if the frequency of oscillation for a given defect is outside [ 5.4MHz − 6.6MHz ] range, then that defect is considered detected.In Fig. 13, the transient waveforms for V c , V out_osc and corresponding frequency f osc are plotted.We also added horizontal markers for nominal frequency f osc_nom = 6MHz along with ±10% threshold lines at 5.4MHz and 6.6MHz .These thresholds are chosen based on the Monte Carlo variation of oscillation frequency as shown in Fig. 12.As discussed all the defects that generate the oscillation frequency outside these threshold lines are marked as detected.Moreover, the output is reset to ground before the beginning of testing every defect to clear the effects of preceding defect state.
gives a performance comparison between conventional framework and the proposed framework for op amp testing using OTM method.The total simulation time for conventional framework is around 185 s to 150 defects.In contrast, our proposed takes around 85 s which means our proposed method takes less than 50% simulation time compared to the conventional framework.This saving factor is estimated just for a single simulation corner.However, when considered across variations viz., process, voltage, and temperature corners along with mismatches, the time-saving factor would remain the same.To validate this point, assume we need to simulate operational amplifier for 150 defects in 200 Monte Carlo variations,2 voltage corners,3 temperature corners using 20 parallel computers.For the OTM method, the average simulation time per defect is 1.24 s for conventional framework (See Table 4).Therefore, the total simulation time for both the methods can be calculated as shown in Eqs. ( 2) and ( 3) confirming that the time-saving factor remains the same ( (3.1∕1.33)≅ 2.3). (

Defect simulation: FVF low drop-out regulator
In this section, let us consider the second AMS circuit, an FVF LDO to corroborate the time-efficiency of our proposed framework.Similar to the testing of operational amplifier, the defects in the FVF LDO are simulated using two similar methods.The first method is predominantly a DC testing method known as intentional offset injection (IOI) method for LDOs proposed in [17,18] and the second testing method is the Oscillation Test Method (OTM) [15,16].

Circuit under test: FVF LDO
Flipped Voltage Follower based LDOs (FVF LDOs) are capable of providing high bandwidth and by that, increased PSRR due to presence of fast local loop [19].They have been of special interest in recent years as they do not require external capacitors [19][20][21][22][23].The FVF LDO that is used in this work is shown in Fig. 14 and is similar to the architecture presented in [18,21].Our LDO has a bias block, an error amplifier (EA) and a power stage.The bias block generates necessary bias voltages for the error amplifier ( V EA_BP , V EA_BP_CAS , V EA_BN_CAS ) and for the power stage ( V PS_BP , V PS_BN ) .In Fig. 15, the transistor-level schematic (3) of the bias block is presented.Figure 16 shows the transistor-level schematic of the error amplifier (The brown-dotted circuit is the testing circuitry) and the Fig. 17 shows the schematic of the power-stage of our FVF LDO.

Intentional offset injection method -FVF LDO
The first scheme used to test our FVF LDO is the intentional offset injection method similar to the one discussed in the previous section.While [17] discussed IOI method for classic LDOs, [18] specifically discusses IOI method for FVF LDOs.As IOI method is already explained in detail in previous section, the method for LDOs is discussed briefly in this subsection.For more insight into the testing method, the readers of this paper are encouraged to refer to [18].In this testing method, either a positive or negative offset is injected into the error amplifier by using the testing transistors M PT ,M NT .Once these offsets are injected, the defects are simulated by checking the defect truth table presented in Table 5.There are four dual threshold detectors [18] placed at fault-sensitive nodes ( V OUT_LDO , V OUT_EA , V X , V G_MP ) and are named ( DET_EA_OUT , DET_LDO_OUT, DET_VX , DET_VG_MP ) as shown in Fig. 14.For a defect-free case, the outputs of all these detectors are '1' for a positive injection case and are '0' for a negative injection case.Furthermore, the outputs of all the detectors are sent into set of 4-AND and 4-NOR gates followed by switched to generate the final reliability output, V rel as shown in Fig. 18.In a defect-free case, V rel should be High for both positive and negative injection case.All this information is captured in Table 5.
Fig. 14 FVF LDO circuit along with feedback connect circuit and defect detectors

Defect detection of operational amplifier using IOI with proposed framework
In this subsection, using IOI method, the defects in FVF are simulated with the conventional and proposed framework to validate the time efficiency of the proposed method.Similar to the case for op amps, the first step is to convert all the transistors into "modified" transistors as explained in Sect. 2.Then, for the FVF LDO to enter the test mode, the feedback network is disconnected by opening the switch M NRML_SW and V FB_IN node is shorted to V REF by closing the switch M TEST_SW .Once the LDO enters the test mode, all the defects in the FVF LDO are tested in two steps.First, the positive offset is tested to the error amplifier and the control voltage V C is swept.The output of the reliability output for this case is saved (labelled V rel_pos_inj in Fig. 19).
This is repeated for negative offset case as well and the reliability output for negative offset is labelled as V rel_neg_inj in Fig. 19.As discussed for a defect-free case, both V rel_pos_inj and V rel_neg_inj would be high.However, if a defect cause any of these outputs to go zero, then that defect is considered to be detected.As shown in Fig. 19, some defects are detected, and some are not detected.Similar to op amp case, after removing the redundant defects such as diode-connections and cascode defects as explained in [18], the overall defect coverage is 94%.Table 6 gives a performance comparison for IOI based defect simulation of FVF LDO between conventional framework and the proposed framework.In contrast to the conventional framework that takes around 1071 s to simulate all the defects, our proposed framework takes just about 67 s to test the same.Hence similar to the case operational amplifier, our framework provides a significant time saving factor of ~ 16X time reduction in comparison with the conventional framework.All the simulation times in the tables are an average for 10 simulation runs.
Fig. 18 Generating the final reliability output V rel from the detector outputs Table 5 Truth table to detect defects in FVF LDO using IOI method Mode Defect-Free Fig. 19 Defect detection using IOI method for FVF LDO with proposed framework

Defect detection of FVF LDO using OTM with proposed framework
In this subsection, let us understand the time-efficiency of the proposed method for predominantly transient OTM method for LDOs.For this exercise, the same FVF tested in the previous section is used (Fig. 14), except that the new CUT would not have the detectors and other testing circuitry needed for the IOI.We convert the FVF LDO into an oscillator using a positive feedback connection ( R osc , C osc ) as shown in Fig. 20.The values of resistors and capacitors are chosen in such a way that sustained oscillations are achieved at 1.5 MHz as shown in Fig. 23.Next step is to sweep the control voltage in steps of V c_inc (1mV) to simulate defects one after the other.For each defect, the oscillator is simulated for 50 us.Hence, the total simulation time of 11450 µs is needed to simulate 228 defects (38transistors × 6defectspertransistor) including an initial 50 µs for the defect-free case.Similar to the OTM case of op amp, a tolerance range of ±10% is considered i.e., if the frequency of oscillation for a given defect is outside [ 1.35MHz − 1.65MHz ] range, then that defect is considered detected.The transient waveforms for V c , V out_osc and cor- responding frequency f osc are plotted in Fig. 22 along with horizontal markers for nominal frequency f osc_nom = 1.5MHz and ±10% threshold lines at 1.35MHz and 1.65MHz .These thresholds are chosen based on the Monte Carlo variation of oscillation frequency as shown in Fig. 21.If an activated defect generates an oscillation frequency outside the threshold lines, then that defect is marked as detected.With this, 90% of defects are detected after excluding the redundant defects.The total simulation time for the proposed method is 2274 s whereas the conventional framework takes around 7561 s.This implies that our method takes around onethird (< 33%) simulation time compared to the conventional framework.Table 7 gives a performance comparison between conventional framework and the proposed framework for FVF LDO testing using OTM method.

Defect simulation: successive approximation register (SAR) ADC
In this section, a data converter circuit is simulated using the proposed framework.For this exercise, a BIST presented in [24] is implemented that performs a structural test for an 18-bit SAR ADC's Capacitive DAC based on the natural operation of the ADC.

Circuit under test: SAR ADC
The blocks in the SAR ADC structure include a constant V GS Bootstrap switch for sampling analog voltage V in , a successive approximation register, an internal DAC and an analog voltage comparator which provides feedback to the SAR Logic by comparing the sampled V in with the DAC's output.The circuit under test is shown in Fig. 24.Different blocks of the CUT can be tested with different approaches: some of which have already been validated with our time efficient defect testing simulation.For instance, the comparator can be tested by taking the approach of intentional Fig. 20 Converting an LDO into an oscillator for oscillation test method to detect defects offset injection discussed in previous sections.As a result, the main block of focus tested and described in this section is the three segmented 18-bit Capacitive DAC Array.
The switches connecting the capacitors to VDDand GND lines are pmos and nmos switches respectively that are matched in size with the weight of the capacitors to maintain a constant RC factor and retain the same charging time for each capacitor unit independent of the size.Figure 25 shows our implementation of the CDAC switches.All the circuits in our ADC are same as presented in [24].

One hot encoding
The testing scheme implemented to test the three segmented 18-bit SAR ADC CDAC is the one hot encoding strategy [24].It is based on the analysis of the charge conservation in the capacitive DAC.One hot encoding is a two-phase testing scheme made up of the pre-charging and conversion phase.During pre-charge, all other bits except the bit under test (k th bit) are connected to ground as shown in Fig. 26.After pre-charge phase is conversion.In the conversion phase, the capacitor array of the kth bit is connected to the GND and a normal binary search is performed from the MSB.In a defect free case, a code of all zeros from MSB to kth bit and all ones from the (k-1) th bit to LSB is expected.However, in the case of the occurrence of each defect, we can observe that this conversion code will change.One hot can be performed for any bit.
Careful analysis in [24] showed that, by performing a one hot test for bit k, the defects in bit k to the MSB can be detected.However, the offset of the comparator, process variations, and mismatches limit this detection.For the CDAC architecture shown in Fig. 24, performing three onehot encoding tests for the LSB's in each segment is sufficient to detect all the defects in the CDAC array.

Defect Simulation with proposed framework using one hot encoding
In the SAR ADC, each capacitive DAC array is charged through a pmos and discharged through a nmos.Thus, for an 18-bit segmented array, there are 36 transistors.Simulating 6 defects for each transistor means testing 216 defects (36transistors × 6defectspertransistor) in total.We run three sets of one hot encoding for the LSB of each segment to simulate defects in that segment while sweeping control in steps of V c_inc (1mV).Thus, for the LSB segment (first 12 transistors) one hot encoding for BIT 1 is performed while sweeping control voltage from 0 (to include defect free) to 72mV.Similar steps are repeated for BIT 6 and BIT 13 while sweeping the appropriate control voltage ranges.
The SAR ADC completes a binary search and resets after every 22 µs and so errors that arise from the effects of preceding defects in transient testing are eliminated because of the reset.To cover 72 defect simulations, a transient simulation of 1584µs should be performed(1656 µs in the case where simulation for the golden circuit is included) as shown in Fig. 27. Figure 28 shows the zoomed in waveform for first 22µs which is the defect free case.Table 8 compares the number of defects simulated and the simulation time for conventional and proposed framework.The total defect simulation time for the conventional framework is 755 s to simulate all 3 segments (216 defects).In comparison, the proposed framework takes around 367 s that is ∼50% of the conventional framework).

Summary: time savings
This section summarizes the time savings achieved using the proposed defect simulation in comparison with the conventional framework.As tabulated in Table 9, the time savings are significant if the testing method is predominantly DC testing.For DC-oriented IOI testing, the time savings factor for op amp and FVF LDO are 10.75X and 16X respectively.On the other hand, for transient based testing, the time savings factor for op amp, FVF LDO and SAR ADC are 2.3, 3.3 and 2 respectfully.This information can be visually seen in (for operational amplifier), (for FVF LDO) and (for SAR ADC).

Conclusion
In this work, we propose a simple time-efficient framework to perform defect simulation for AMS circuits.This framework uses several Verilog-A modules which can be controlled by a global voltage to activate defects in a given circuit under test.Using this approach, we demonstrated the capability of our framework to simulate several defects with a single simulation run.In comparison with the conventional framework, our framework saves the overall simulation time not only by avoiding redundant work of generating netlist for each defect but also by reducing data/ file-handling overhead time.Additionally, the effectiveness of our framework using is validated using diverse AMS circuits such as operational amplifier, flipped voltage follower based LDO and SAR ADC as circuits under test.Furthermore, we also showed that more than 10X timesavings can be achieved for DC oriented test methods such as intentional offset injection testing method for op amp and FVF LDO.The Oscillation test method (OTM), which is primarily a transient testing method, is used as a second testing scheme to test op amp and FVF LDO.For OTM method, we showed that the simulation time is decreased to less than 50% for both op amp and FVF LDO.Lastly, for SAR ADC testing, one-hot encoding-based testing scheme is considered, for which, the proposed framework used less than 50% simulation time compared to the conventional framework.We also showed that for all the methods, our framework shows no negative impact on the defect coverage with respect to the conventional framework.Also, the framework proposed in this work is not a replacement but is complementary to the prevailing defect-simulation time-reduction strategies.

Fig. 2 Fig. 3 Fig. 4
Fig. 2 Process flow for proposed defect simulation framework with parametric control for defect injection

Fig. 5
Fig. 5 Verilog-A code for the defect resistorR DD

Fig
Fig.6 Defect Resistors' variation as with respect to the control voltage for dev id = 2 (Table1)

Fig. 8 a
Fig. 8 a Operational amplifier with intentional offset injection b Corresponding detector c The frequency response of original amplifier and 'modified' amplifier

Fig. 9 a
Fig. 9 a Widlar current reference b Biasing circuit c Digital window comparators d Final reliability output Vrel generation

Fig. 11
Fig. 11 Converting the operational amplifier into an oscillator for OTM testing

Fig. 21
Fig. 21 Defect-free oscillation frequency for FVF LDO with 500 Monte Carlo variations

Fig. 27
Fig. 27 Defect detection for SAR ADC using proposed framework for LSB segement

Table 1 )
66Defect Resistors' variation as with respect to the control voltage for dev id = 2 (

Table 2
Truth table to detect defects in op amp using IOI method

Table 3
Performance Summary for IOI Method for operational amplifier

Table 8
Performance summary for one-hot testing method for SAR ADC