Designing a one-bit coplanar QCA ALU using a novel robust area-efficient three-input majority gate design

Quantum-dot cellular automata (QCA) which is a suitable alternative to conventional CMOS technology is susceptible to some defects in chemical synthesis and deposition phases of circuit fabrication. Besides, the majority gate is one of the most important primary gates for designing digital circuits in this emerging technology. Designing a fault-tolerant majority gate is one of the hot topics in QCA technology. Most previous works tried to improve the majority gate reliability by increasing the number of QCA cells which resulted in occupying more area. In this paper we propose a novel area-efficient three-input majority gate which can tolerate the single-cell omission and extra-cell deposition defects by 86% and 75%, respectively. The proposed majority gate consists of 11 simple QCA cells with 0.006\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$0.006\,$$\end{document}µm2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\hbox {m}^{2}$$\end{document} and 1.62 e-002 MeV area and energy consumption, respectively. A complete fault tolerance analysis for our proposed majority gate against cell omission, extra-cell deposition, and cell displacement and misalignment defects is also provided. We design a fault-tolerant coplanar fulladder/fullsubtractor and a two-to-one multiplexer using the proposed majority gate and compare it with the same previous works. Simulation results from QCADesigner 2.0.3 and QCADesigner-E show that in all cases our proposed robust circuits can reduce the area consumption. Finally, we implement a fault-tolerant coplanar one-bit ALU using the proposed circuits that can perform four logical and mathematical operations.


Introduction
There has been a lot of research on finding a proper alternative to CMOS technology in the last decade.Although CMOS technology makes it possible to design more depth circuits by decreasing the size of transistor width, it has reached the physical restriction which results in some disorders like short-channel effects, design variation, and heat.Considering the high levels of performance, speed, and component density and the very low level of power consumption of quantum-dot cellular automata (QCA) technology, it has become a suitable alternative for CMOS technology [1][2][3][4].
QCA technology stores and transfers the information in cells containing quantum dots.Two free electrons sit in four quantum dots which are located in four corners of each cell.The free electrons are placed at diagonally opposite positions due to electrostatic Coulombic interactions between them.The two possible resulting polarizations define the logical state of the cell [5].The process of storing and transferring data in QCA cells is based on the relative formation of the cell charges instead of electric flow which results in a field coupled technology (FCN) [6].Metal island, semiconductor, magnetic, and molecular are the four different types of QCA cell implementations [7].
QCA technology has some serious problems which are not already fixed completely due to its novelty.There are some defects in the chemical synthesis and deposition phases of QCA circuit design which decrease the reliability of these circuits [8,9].Cell misalignment, cellular displacement, cell omission, and deposition of extra cells are the four most probable defects that would occur in the deposition phase resulting in a drastic reduction in circuit efficiency.As a result, fault-tolerant logical QCA circuit design has become so momentous that researchers have done a bunch of studies about this since the last decade.
Three-input majority gate and inverter are the two fundamental logic gates in designing logical and computational circuits in QCA technology [7,10].The efficiency of these two gates will result in the efficiency of the whole logical system.In this work, we design a novel robust area-efficient three-input majority gate with 11 simple QCA cells.Then we design a one-bit fulladder/fullsubtractor, a 2:1 multiplexer, and finally a one-bit ALU using the proposed three-input majority gate.
The remainder of this work is structured as follows.First, we review the QCA fundamentals as well as the different types of defects in QCA design in Sect. 2. In Sect. 3 we propose our fault-tolerant area-efficient three-input majority gate, verify its fault tolerance against common defects and compare it with already proposed designs.The computational circuits including a one-bit fulladder/fullsubtractor, a 2:1 multiplexer, and a one-bit ALU using our proposed structure are introduced and compared with the previous works in Sect. 4. Finally, we conclude the paper in Sect. 5.

Preliminaries
In this section, we first review the QCA fundamentals including QCA basic logic gates and clocking system.Then, we explain different types of QCA wire crossing.Finally, common QCA defects are discussed.

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Designing a one-bit coplanar QCA ALU using a novel robust…

QCA fundamentals
Square-shaped QCA cells are the basic element of QCA circuits which interact via local field with each other and realize logical behavior [7].Each QCA cell consists of four quantum dots which are located at the vertices of the square and able to confine electric charge [11].Furthermore, the QCA cells contain a free and mobile pair of electrons which can tunnel between the adjacent dots [12].Considering the Coulombic interaction between electrons in each cell, they only can place themselves at opposite corners of the cell which leads to two possible stable cell polarizations.Figure 1 shows P = −1 and P = +1 polarizations which define the logic '0' and logic '1,' respectively [12].
To construct a binary wire, a chain of QCA cells should be placed next to each other to propagate the input to the output by Coulombic energy transaction between the electrons of the cells [13]. Figure 2 illustrates two types of QCA wires which are based on 45-degree (rotated) and 90-degree (simple) cells [14].The rotated-based QCA wires (Fig. 2b) are usually employed to implement an inverter chain or for wire-crossing purposes [15].
The majority gate and inverter are the two basic gates of QCA technology that are employed to implement almost all the logical circuits [16].Figure 3a and b show a basic three-input majority gate and an inverter, respectively.As it is shown in Fig. 3a a three-input majority gate consists of three input cells, one voter cell, and an output cell.A three-input majority gate functionality is given by Eq. 1.The output value of the three-input majority gate becomes logic '1' only when two or more input values equal '1' [14].The QCA technology uses the clocking system in order to control the timing of the circuits and the information flow for creating pipelines and forcing logical circuits to stay in the quantum mechanics ground state [7].A QCA clocking zone is a group of QCA cells which are controlled by the same clock.Four clocking zones are available in QCA and each of them has four phases [17].Figure 4 illustrates the QCA clock phases named switch, hold, release and relax [18].In the switch phase, the potential barrier among quantum dots is gone up and cells begin to polarize according to their input.In the hold phase, the barrier is kept high.In the release and relax phases, the barrier is lowered and remains lowered, respectively, and cells become and remain unpolarized.The phase of a clock zone in a QCA design is 90 degrees different from the phase of the next and previous clock zones.For example, as it is shown in Fig. 5, when clock 1 is in the switch case, clocks 2, 3 and 4 are in the relax, release and hold phases, respectively.

Cross wire approaches
There are three different methods for crossing over QCA wires including multilayer, coplanar and logical coplanar [7]. Figure 6 shows these crossing methods.In the multilayer wire crossing (Fig. 6a), the crossing of two same type wires will be done Designing a one-bit coplanar QCA ALU using a novel robust… in different layers [19].The drawback of this type of wire crossing is that its implementation needs multiple active QCA layers on top of each other which have not been demonstrated before [7].In the single-layer or coplanar wire crossing (Fig. 6b) which employs rotated QCA cells, two orthogonal wires cross each other without any effect on their operations [20].The main drawback of this method is that because of employing two types of simple and rotated QCA cells, the implementation can easily be affected by fabrication and cross coupling defects [19].Finally, the logical coplanar wire crossing (Fig. 6c) employs two groups of QCA cell arrays Fig. 6 QCA crossing wires types: multilayer (a), coplanar (b), and logical coplanar (c) which have different clock phases.QCA cells in relax and release phases do not affect on their neighboring cells since they are unpolarized in these phases [21].Therefore, those cells which are in the hold and relax phases can cross over cells which are in switch and release phases with no polarization effect [22].This type of wire crossing, which is named logical coplanar wire crossing, is more reliable than simple coplanar wire crossing since it only employs simple QCA cells.It is also more area and energy efficient compared to multilayer wire crossing since it is implemented in one layer.

QCA defects
There are two types of defects in QCA design.One of them may occur during manufacturing QCA cells referred to as the synthesis step.Another may occur during placing the cells in the substrate which is referred to as the deposition step [23].
Since QCA cell sizes are very small and need high accuracy in arranging, defects in the deposition step are more likely to occur [24,25].Common defects in the QCA deposition step are categorized into four groups as follows: • Cell omission: This type of fault occurs when a cell is missing compared to the original fault-free design (Fig. 7a).• Cell displacement: This type of fault occurs when a cell is misplaced within its original direction and the distance between the cell and other cells is reduced or increased (Fig. 7b).• Cell misalignment: This type of fault occurs when a cell is not aligned correctly to its neighboring cells (Fig. 7c).• Extra cell: This type of fault occurs when an additional cell is placed in the substrate (Fig. 7d).

The proposed fault-tolerant three-input majority gate
Majority gates are one of the most important basic gates which are employed in QCA circuit designs.These gates always have an odd number of inputs and their only output is the majority vote of the inputs.Designing a fault-tolerant majority gate with optimized area consumption will result in area-efficient QCA circuits.In this section, we first propose a novel robust area-efficient three-input majority gate using simple QCA cells and verify its functionality with QCADesigner 2.0.3 simulator [26].Then the simulation results including cell count, area, and number of clock cycles are provided using QCADesigner 2.0.3 simulator and the energy consumption is also reported using QCADesigner-E simulator [27].After that, we study the fault tolerance of the proposed gate against different QCA defects such as cell omission, cell displacement, cell misalignment, and extra cell deposition.Finally, we compare the proposed design with those previous works which employ simple QCA cells in terms of area, cell count, energy consumption, number of clock cycles, and the amount of fault tolerance against single-cell omission defect.
1 3 Designing a one-bit coplanar QCA ALU using a novel robust… Figure 8 shows the layout of the proposed three-input majority gate.The output is calculated based on Eq. 1.As it is shown, the proposed gate consists of 11 simple QCA cells and the output is valid after one clock phase.The simulation results of the proposed structure which is performed by QCADesigner 2.0.3 is shown in Fig. 9.The area and the energy consumption of our proposed three-input majority gate are 0.006 μm 2 and 1.62 e-002 MeV, respectively.Two-input AND and OR gates can be implemented by fixing the polarization of one of the proposed three-input majority gate inputs to '0' and '1,' respectively.Figure 10a and b illustrate the proposed fault-tolerant two-inputs AND and OR gates, respectively.The output of these three gates is verified by QCADesigner 2.0.3 which is shown in 1 3 Designing a one-bit coplanar QCA ALU using a novel robust…

Fault tolerance analysis of the proposed majority gate against QCA defects
In this subsection, we study the fault tolerance of the proposed three-input majority gate against different QCA defects including single-cell omission, double-cell omission, cell displacement, and finally extra cell deposition.
To calculate the fault tolerance against cell omission defect which is one of the most important QCA defects, we consider all possible cases in which a single or double QCA cells of the proposed majority gate (excluding input/output cells) are omitted.Tables 1 and 2 show the output results in each case of single-and double-cell omission, respectively.As Tables 1 and 2 show, the majority gate output remains correct in many cases.In fact, the output in 86% and 43% of cases of singleand double-cell omission defects is correct, respectively.Extra cell deposition is another important QCA defect that we consider it in fault tolerance calculations.To measure the fault tolerance of the proposed three-input majority gate against this defect, we consider all possible cases where an extra simple QCA cell is located around the proposed gate.Figure 12 shows all these extra cells which are labeled as E1 to E8.The output result after depositing each extra cell is provided in Table 3.As it is shown the proposed gate output is correct in 75% of cases.
For calculating the fault tolerance of the proposed gate against misalignment and displacement defects, the permitted range of displacement of all QCA cells in which the output remains correct is measured for four main sides (e.i.north, east, south, and west).Table 4 shows the mentioned permitted range.As it is shown, the proposed majority gate is highly tolerant against misalignment and displacement defects.

Comparing the proposed three-input majority gate with previous works
The majority gate is one of the basic logic gates in QCA circuit design.Although there has been a lot of research in proposing an area/energy efficient majority gate with a high level of tolerance against QCA defects, it is still an open topic.We have  1 3 Designing a one-bit coplanar QCA ALU using a novel robust… proposed an area-efficient three-input majority gate using simple QCA cells.In this subsection, we compare our work to other area/energy efficient and robust threeinput majority gates which are based on simple/rotated QCA cells.
Table 5 shows the comparison between the proposed majority gate and previous works in terms of the number of QCA cells, area consumption ( m 2 ), latency (num- ber of clocks), energy consumption (MeV), and the gate tolerance against single-cell omission defect.As mentioned before, designs which employ both simple and rotated QCA cells can be affected by cross-coupling defects and are less fault-tolerant in comparison with those that are only based on simple QCA cells.Thus, our proposed robust majority gate is the most area-efficient design which only employs simple QCA cells comparing to all the previous works.The percentage of improvement in terms of the number of employed cells and the area consumption in the proposed majority gate compared to the previous works are also shown in Fig. 13.

Digital circuits based on the proposed three-input majority gate
In this section, we first design a fault-tolerant fulladder/fullsubtractor and a robust 2:1 multiplexer based on the proposed majority gate and compare them with same designs utilizing the best three area-efficient fault-tolerant majority gates which are  Designing a one-bit coplanar QCA ALU using a novel robust… based on simple QCA cells ([32]-1, [32]-2, [23]).Finally, we design a one-bit ALU based on our proposed basic circuits and compare it with previous ALU designs.

The proposed fulladder/fullsubtractor
Fulladder/fullsubtractor (FA/FS) is one of the most important building blocks in designing computational digital circuits like arithmetic multipliers, dividers and ALU [33,35,36].In this subsection, we design four different FA/FSs based on the three-input majority gates designed in [32]-1, [32]-2, [23], and our proposed one.Then we compare them in terms of the number of cells, area and energy consumptions.
The fulladder outputs named Sum and C out are calculated based on equations Eqs. 2 and 3, respectively.The equations for calculating fullsubtractor outputs named Sub and B out are also provided in Eqs. 4 and 5, respectively.In all these four equations A, B, and C in are considered as inputs.
For designing an area-efficient fault-tolerant fulladder/fullsubtractor employing the proposed fault-tolerant three-input majority gate, we use the FA/FS combined circuit design which is introduced in Ahmadpour et al. [35].The circuit outputs (i.e.Sum, Sub, C out and B out ) can be computed using the equations Eqs.6-8.
The fault-tolerant FA/FS circuit diagram employing our proposed three-input majority gate and its corresponding layout is illustrated in Fig. 14a and b, respectively, and the simulation output of the proposed circuit is also provided in Fig. 15.As it is shown in Fig. 14b, the proposed layout consists of 112 simple QCA cells, and the outputs are ready after 1.75 clock cycle.The area and total energy consumption of this proposed circuit are also 0.11µm 2 and 5.56 e-002 MeV, respectively.We calculate the reliability of the proposed FA/FS against single-cell omission defect.The results show that the Sum/Sub, C out and B out are 38%, 86% and 74% tolerant, respectively. (2) We compare our proposed fault-tolerant FA/FS with other three works which are designed using the three-input majority gates designed in [32]-1, [32]-2 and [23].All the FA/FSs are designed based on [35] work which provides one of the best architectures for coplanar FA/FS.The comparison is made in terms of cell count, area, and energy consumption which is available in Table 6.As it is shown, the fault-tolerant FA/FS employing our proposed majority gate occupies less area in comparison with other designs.

The proposed 2:1 multiplexer
Multiplexers are important digital circuits which are widely used in implementing different digital designs such as memory systems and FPGAs.In this subsection, we design and compare four different 2:1 multiplexers employing three-input majority gates designed in [32]-1, [32]-2, [23] and our proposed one.
A 2:1 multiplexer can connect one of its two inputs to the only output by a singlebit selection bit. Figure 16a shows a 2:1 multiplexer diagram where A and B are the inputs that can be transferred to the output (i.e.Out) based on the selection bit named S.The multiplexer output becomes A when the value of S is Zero (i.e. S = '0'), and it becomes B when the value of S is One (i.e. S = '1').The multiplexer output (i.e.Out) can be calculated using the equation Eq. 9. Based on this equation three three-input majority gate and a not gate are needed for implementing a 2:1 multiplexer.
Figure 16b illustrates the proposed fault-tolerant 2:1 multiplexer.The simulation output of the proposed circuit is also provided in Fig. 17.As it is shown in Fig. 16b, the proposed design consists of 51 simple QCA cells and the circuit output is ready after a 0.75 clock cycle.Based on the simulation results of the QCADesigner 2.0.3 1 3 Designing a one-bit coplanar QCA ALU using a novel robust… tool, our proposed multiplexer consumes 0.04µm 2 area.The total energy con- sumption of our design is also 3.87 e-002 meV according to QCADesigner-E tool  simulation results.The proposed design is also 43% tolerant against single-cell omission defects.We compare our 2:1 multiplexer to three other works which are based on the three best majority gates that were mentioned above.Table 7. shows the comparison of these designs in terms of cell count, area and energy consumptions.As the simulation results show, the 2:1 multiplexer based on our proposed three-input majority gate is area efficient in comparison with other three works.

The proposed one-bit ALU
The Arithmetic Logic Unit (ALU) which is one of the most important parts of the CPU, performs the basic arithmetic and logical operations.We design a new coplanar fault-tolerant scalable ALU based on our proposed three-input majority gate and compare it with the previous designs.Figure 18a and b shows the circuit diagram and truth table of the proposed ALU, respectively.As it is shown, the proposed ALU can perform four different functions.The QCA layout of the proposed fault-tolerant design is also provided in Fig. 19.
Based on the proposed circuit layout in Fig. 19, our coplanar ALU consists of 589 simple QCA cells employing logical wire crossing.The proposed design is also scalable (i.e., none of the input cells is surrounded by the structure [37]).The QCADesigner 2.0.3 simulation results show that the ALU consumes 1.08 m 2 and the output is provided after 3.75 clock cycles.
We compare our design with previous works in Table8.As there is no unique structure for these ALUs, we compare them in terms of the number of implemented building blocks, the number of cells, area consumption, the number of clock cycles that the output needs to be generated, the circuit layout structure, the  type of cells which are employed, and the scalability feature of the designs.As it is shown, compared to other designs, our proposed fault-tolerant coplanar scalable ALU is superior in terms of QCA cell count, and occupied area.Designing a one-bit coplanar QCA ALU using a novel robust…

Conclusion and future works
One of the most important issues in QCA technology is the circuit reliability against defects in chemical synthesis and deposition phases of circuit fabrication.We have proposed a novel area-efficient fault-tolerant three-input majority gate which has 11 simple QCA cells and occupies 0.006 m 2 area with 1.62 e-002 MeV energy con- sumption.The proposed majority gate is highly tolerance against QCA defects and the most area-efficient design comparing to the previous works.A coplanar areaefficient fault-tolerant fulladder/fullsubtractor and 2:1 multiplexer are also designed based on the proposed majority gate which in most cases could decrease the area consumption while improving the circuit fault tolerance in comparison with other similar designs.Using the proposed circuits, we designed a one-bit ALU which can perform AND, OR, NOT, and ADD/SUBTRACT operations.Simulation results show that our proposed ALU is also superior to other works.More area-efficient and robust complex circuits can be designed in future works by employing the proposed three-input majority gate.

Fig. 3 Fig. 4
Fig. 3 Basic majority gate (a) and inverter (b) designed based on QCA technology

Fig. 11 Fig. 7 FigFig.
Figure8shows the layout of the proposed three-input majority gate.The output is calculated based on Eq. 1.As it is shown, the proposed gate consists of 11 simple QCA cells and the output is valid after one clock phase.The simulation results of the proposed structure which is performed by QCADesigner 2.0.3 is shown in Fig.9.The area and the energy consumption of our proposed three-input majority gate are 0.006 μm 2 and 1.62 e-002 MeV, respectively.Two-input AND and OR gates can be implemented by fixing the polarization of one of the proposed three-input majority gate inputs to '0' and '1,' respectively.Figure10aand b illustrate the proposed fault-tolerant two-inputs AND and OR gates, respectively.The output of these three gates is verified by QCADesigner 2.0.3 which is shown in Fig.11.

Fig. 10 Fig. 11
Fig. 10 The proposed and, or gate circuit layout

Fig. 12
Fig. 12 Extra cells around the proposed majority gate

Fig. 13
Fig. 13 Improvements (%) in number of QCA cells (a) and area (b) of the proposed majority gate compared to the previous works

Fig. 18 Fig. 19
Fig.18 The proposed ALU circuit diagram (a) and truth table(b)

Table 5
Three-input majority gates comparison

Table 8
ALUs comparison