KLECTOR: Design of Low Power Static Random-Access Memory Architecture with reduced Leakage Current

- A novel approach called Keeper in LEakage Control Transistor (KLECTOR) is presented in this paper to reduce leakage currents in SRAM architecture. The SRAM is significantly affected by the leakage current during the "standby mode", which is caused by the fabric which has a lower threshold voltage. KLECTOR circuit employs less power consumption by restricting the flow of current through devices of less voltage drops and relies heavily on the self-controlled transistor at the output node. It has been found from the presented results that static (leakage) power in the write operation is reduced to 63% and 69 % for the read operation. This proposed approach is designed and simulated using the Virtuoso, Cadence EDA tool.


INTRODUCTION
In VLSI circuits, the basic key elements are memories, processor and logic devices which decide the effective power utilization based on current consumed in each stage. The advancements in VLSI technology demand low power devices to enhance larger operating time which are limited by leakage currents in various operation cycle [1,2]. The low power architecture of SRAM (Static Random-Access Memory) plays a dominant role in various applications due to its speed and long-term resistance [3]. Configurable Logic Block (CLB) is a major block in VLSI design involved devices like SPARTAN and VIRTEX architecture [4][5]15]. CLB consist of 20% to 30% SRAM cell [16] because it has the advantage of reprogrammable capability and speed. There are different types of SRAM basic cells available in CLB block in which some of the basic cell is activated based on word length while remaining cells are maintained in standby mode. The Leakage current plays a dominant role in SRAM power consumption during standby mode [7] [10][11][12][13]. This technique makes the leakage power consumption more than dynamic power which directly affects the speed of the SRAM operation [14]. This results in short channel effects that exponentially increase sub-threshold leakage current. Therefore, the CMOS system will leak power due to a sub-threshold leak current of this current value. When voltage is applied to the gate, the current will flow from the source to the drain, even though there is no voltage applied to the gate. The Transistor is in the area of low inversion, i.e., Reduction of the thickness of the door oxide increases the field oxide across the door that results in electron flows from door to door or substratum to door.  [6][7][8][9]. The first 7 techniques require extra monitoring input circuitry because according to SRAM work condition (active or standby mode) we need to change the input of extra adding transistor. In GALEOR technique power is reduced but voltage swing problem is occurred. In LSSR power is reduced with area penalty. So, among these techniques, LECTOR is the best technique for our application/architecture to reduce leakage current in SRAM. But the provision of sleep mode of operation for state retention is not possible. Hence, one of the devoted merits of Sleepy Keeper circuit is of state retention. The performance factors of LECTOR and Sleepy Keeper techniques were combined to focus on new emerging technique called KLECTOR to meet the trends and future projections in this area. Every technique has its limitations and can be used based on the application specific requirements [16]. To overcome the performance degradation of SRAM, KLECTOR technique is proposed and implemented in SRAM architecture to reduce the leakage current in it [17] [18]. This paper is organized as follows; LECTOR approach is discussed below. Section II discusses the proposed KLECTOR technique in SRAM. The experimental results are discussed in Section III. SRAM's performance is evaluated in Section IV sand Section V concludes the paper.

LECTOR APPROACH
LECTOR connects the pull-up and pull-down network transistors (pmos and nmos) in series mode. The LECTOR technology is also known as the self-control technology [9] subsequently the pmos transistor gateway is connected to the pull-down network and the nmos transistor to the network pull-up gate [3]. The transistors create a large sensitive path between VDD and GND, which reduces the SRAM leakage current during stand-by mode. Figure 1 shows the basic structure of LECTOR.

II. PROPOSED: KLECTOR TECHNIQUE
The prevailing dominant technologies in leakage current detection are Keeper and LECTOR Techniques. KLECTOR Technique overcomes the disadvantages of LECTOR technique. KLECTOR is a combination of LECTOR and keeper technique.
The Figure 3 shows the basic structure of KLECTOR technique. In this case, the transistor (pmos and nmos) of leakage control is inserted in between the network pull-up and pull-down. All pmos and nmos are linked in parallel for securing standby maintenance mode. The PMO gate is linked to the downstream and the nmos gate is linked to the upstream network so that no monitoring circuit is necessary to control the additional transistor.
The Figure 4 shows the basic 1bit SRAM cell with KLECTOR approach.

III. RESULTS & DISCUSSION
The implementation of LECTOR and KLECTOR technique in SRAM is done using Cadence v6.1.5 tool. The design is simulated using Spectre simulator of Cadence Design System (Spectre or HSPICE)     The above figure 8 shows SRAM cell schematic diagram with LECTOR technique. It consists of one control signal, two inputs and one output. Control signal R/W is always high. Input BL =0 & BL=0 "1" is read from the basic cell of SRAM.  The figure 10 displays the SRAM cell schematic diagram with KLECTOR technique for write 1. It consists of one control signal, two inputs and one output. Control signal R/W is always high. Input BL =1 & BL=0 "1" is written in a basic cell of SRAM.
Similarly, we have developed the SRAM cell with KLECTOR technique to read 0. It consists of one control signal, two inputs and one output. Control signal R/W is always high. Input BL =1 & BL=1 "0" is read from the basic cell of SRAM. Likewise, to read 1, Control signal R/W is always high. Input BL =0 & BL=0 "1" is read from the basic cell of SRAM. The above figure 11 shows the simulation waveform of SRAM cell for write operation. If BL =0 & BL=1, "0" value is display in output else if BL =1 & BL=0, "1" value is display in output.

Figure 12
Simulation waveform of read 0 & 1 in SRAM cell.
The above figure 12 shows the simulation waveform of SRAM cell for read operation. If BL =0 & BL=0, "1" value is display in output else if BL =1 & BL=1, "0" value is display in output. Figure 13 show the layout of proposed 10T KLector SRAM cells using gpdk 180nm technology in Cadence EDA tool.   In Table 1, It clearly states that the KLECTOR technique performs well in reducing the static power consumption. Table 2 shows that the leakage current in SRAM cell is reduced more than 70 times compared to previous technique.

V. CONCLUSION
In this paper, the KLECTOR technique has been designed and analyzed for low power consumptions in SRAM. The KLECTOR circuit will lead to a considerable reduction of the energy drop that occurred due to lose or leaked voltages. The SRAM power consumption is reduced as its leakage in SRAM is reduced. The static power in SRAM gets reduced by 63 percentage in write operation and 69 percentage in read operation by using KLECTOR modern technologies.

Declarations
Conflict of interest : We declare no conflict of interest.