Simulation of β - Ga2O3 based MOSFETs for Depletion and Enhancement Mode Operation

This paper reports on TCAD-simulation of beta-gallium oxide ( β − Ga 2 O 3 ) MOSFET with the channel recessed into a 1 µ m thick Si-doped (1 × 10 18 cm − 3 ) epitaxial layer. We optimized gate recess thickness to achieve both, depletion and enhancement mode operation. The simulated β − Ga 2 O 3 MOSFET structures show optimum depletion-mode and enhancement-mode characteristics for 150 nm and 15 nm active channel thickness, respectively. A comparative study is also done to analyze the thermal and electrical eﬀects by simulating hetero-epitaxial β − Ga 2 O 3 layer on sapphire substrate and homo-epitaxial β − Ga 2 O 3 layer on β − Ga 2 O 3 substrate. MOSFET devices based on β − Ga 2 O 3 layers on sapphire substrates show improved performance compared to devices based on β − Ga 2 O 3 layers on β − Ga 2 O 3 substrates in terms of drain current, trans-conductance and breakdown voltage. β − Ga 2 O 3 epitaxial layers on sapphire substrates exhibit a drain current density of 77.7 mA/mm with a peak trans-conductance of 2.28 mS/mm for D-mode operation and 27.3 mA/mm drain current density with a peak trans-conductance of 3.92 mS/mm for E-mode operation. In contrast, MOSFET devices based on β − Ga 2 O 3 epitaxial layers on β − Ga 2 O 3 substrates show a drain current density of 64.1 mA/mm for D-mode operation and 22.2 mA/mm drain current density with 3.2 mS/mm peak trans-conductance for E-mode operation. MOSFET devices based on β − Ga 2 O 3 epitaxial structures on sapphire and on β − Ga 2 O 3 substrates show reliable switching properties with sub-threshold swing of 95.98 mV/dec and 87.05 mV/dec respectively as well as a high I on /I off ratio of 10 11 . These simulation results show potential of laterally scaled β − Ga 2 O 3 MOSFETs for power switching applications.

1 Introduction β-gallium oxide (β −Ga 2 O 3 ) is emerging as new generation power semiconductor material because of its material properties such as an ultra-wide band gap of 4.8 eV and the resulting large critical breakdown field (E c ) of 8 MV/cm. These factors lead to high Figures of Merit such as Baliga's FOM (3214) and Johnson's FOM (2844), which are much larger than those of existing wide band-gap semiconductors like SiC and GaN. This enables β − Ga 2 O 3 to be a potential candidate for the realization of high voltage, low-loss power switching devices for power electronics [1] [2]. The proposed high electric field strength of β − Ga 2 O 3 thus outperforms GaN and SiC. In addition, the possibility of bulk growth of large and uniform β − Ga 2 O 3 crystals using conventional melt growth processes enables cheap production [2]. Availability of shallow donors for β − Ga 2 O 3 like Si, Ge and Sn allows n-type doping with a wide range of doping concentrations from 10 15 to 10 20 cm −3 [3]. As p-type conductivity is absent in β − Ga 2 O 3 due to the deep acceptor level of the dopants and the large hole mass all devices reported so far are unipolar devices [3] [2]. After the demonstration of first MESFET/MOSFET by the Higashiwaki group from NICT, Japan β − Ga 2 O 3 -based devices got a significant R&D interest. Various depletion mode (D-mode) devices were explored with doping concentrations up to 10 16 − 10 19 cm −3 (n-type doped) which gives drain current densities up to 200 mA/mm [4]. The voltage limitations also have been explored showing high breakdown voltages up to 1-2.3 kV [5][6] [7]. The devices usually have a negative threshold voltage. However, this introduces more circuit complexity if transistors are operating in a power switching system and is not generally preferable.
Enhancement mode (E-mode) devices are preferred over depletion mode devices in power electronics applications because of their fail-safe operation and the reduced system complexity. In this paper, simulations for enhancement mode β − Ga 2 O 3 based MOSFETs are demonstrated and compared to D-mode device simulations. Various techniques can be applied to achieve Emode in β − Ga 2 O 3 -based devices such as gate recess structure, thin channel layers so that the channel can be depleted easily by interface states and by incorporating unintentionally doped layer as channel layer in between channel layer and substrate [8] [9][10] [11] [12]. Lateral β − Ga 2 O 3 MOSFETs were also demonstrated for power electronics applications with advanced T-gate topology and nitrogen ion-implantation which shows a high-power figure of merit of 155 MW/cm 2 and breakdown voltage of 1.8 kV [?]. Recessed gate E-mode β − Ga 2 O 3 structures demonstrated to achieve good power FOMs for DC conduction switching applications. These devices can provide advantages in various applications such as high-speed switching device, high voltage device operations and many others. In this paper, we demonstrate a laterally scaled recessed gate structure with a 1➭m n-type doped (Si) epitaxial layer on 350 µm sapphire and β − Ga 2 O 3 substrates, respectively. We have optimized the gate recess thickness for this epilayer structures to achieve both depletion mode and enhancement mode β − Ga 2 O 3 based FETs. Device physics, struc-tural simulation parameters and results for these structures are discussed in next section.

Device Structure and Simulation
All the simulations are performed using the commercially available TCAD software SILVACO ATLAS. The schematic of the device is shown below in Figure ??. The structure is simulated with 20 µm source to drain distance (L sd ), gate length of 2 µm and a gate width of 100 µm. The ungated β − Ga 2 O 3 channel regions are kept at a thickness of 1 µm to get best results out of it. The simulation parameters used are taken from an existing model [13][14] [15] and some additional parameters are shown in Table 1. For high field saturation, field dependent mobility model FLDMOB is used for which electron saturation velocity is considered as 2.5 × 10 7 cm/s [2]. Self-heating effects are considered by incorporating lattice thermal models and solving heat flow equations. The built-in impact ionization model is also included to analyze impact ionization in the structure hence breakdown voltage is calculated. The ionization coefficient α based on Cheynoweth model is given by Where, a= 7.9 × 10 5 /cm and b= 2.92 × 10 7 V/cm [16]. These exact values are considered in the simulations without any modifications.

Results and Discussions
The above stated parameters are used for TCAD based 2-D simulations to analyze the performance of β − Ga 2 O 3 -based epi-layer structure. The structure is simulated to get output and transfer characteristics with high transconductance on this epitaxial structure (as shown in Figure 1(a)). The thick epilayer shows a large negative threshold voltage and very low trans-conductance.
As we know that a decrement of channel thickness will improve trans-conductance of the device we decided to use gate recess technique to improve performance. A β − Ga 2 O 3 recessed gate structure (Figure 1(b)) is simulated to check the transistor characteristics. The structure is gate recessed up to 850 nm thickness to get 150 nm active channel thickness which is used to deplete the channel. Transfer and output characteristics of β−Ga 2 O 3 epilayer on sapphire substrate are simulated and shown in Figure 2. β − Ga 2 O 3 MOSFET with 150 nm active channel thickness (after gate recess) is simulated at a drain voltage V ds of 25V to get depletion mode characteristic with a threshold voltage of -25.3 V and a drain current of 0.1 mA/mm. The depletion mode device shows a peak trans-conductance of 2.28 mS/mm and maximum drain current density of 77.7 mA/mm at VG=8 V. We decided to further reduce the channel thickness and we increased the recess thickness and reaches 15 nm of active channel thickness to get enhancement mode characteristics. This structure with 15 nm active channel layer shows an enhancement mode operation with a threshold voltage of +1.05 V at a drain current of 0.1 mA/mm. Simulation with E-mode operation shows a trans-conductance of 3.92 mS/mm and maximum drain current density of 27.3 mA/mm at Vg=8 V as shown in Figure 3. Further, we simulated the gallium oxide structure for a span of different recess thicknesses. Table 2 shows various calculated parameters for the span of different active channel thickness (Recess thickness from 850 nm to 985 nm). The active channel thickness for the structure is downscaled from 150 nm to 15 nm and the respective characteristics and parameters are shown in Figure 4, Figure 5 and table 2.  The depletion and enhancement mode parameters are achieved with practically feasible threshold and on-resistance values [5] [12]. The structure shows a decreasing drain current trend with reducing active channel layer. This reduced drain current trend at constant gate voltage can be co-related with the R SD drop voltage across the channel. As the relation is given by [17] ∆V D,Sat =˜∆(R SD I DS,Sat ) The R SD is inversely proportional to the thickness of the channel hence the drain current can be co-related as a function of the channel thickness as follows:  Where, t is the thickness of the channel. This relation interprets the output drain current variation with active channel thickness.

Comparison of gallium oxide epitaxy on different substrates
In previous section, we have optimized the gate recess thickness to achieve both depletion and enhancement mode operation. In this section we have per-  For simulation it is assumed that carrier transport is confined to channel and heat elements are places at contact pads and substrate which acts as heat sinks to define the thermal effects within the structure. In the simulator heat source is defined at gate edge near the drain and to detect thermal effects. The simulated structure comprises of 1 µm gallium oxide epilayer with an n-type Si doping of 1 × 10 18 doping concentration on sapphire and gallium oxide substrates. Device parameters dimensions of L sd =20 µm, L g =2 µm are taken by keeping in mind the limitation of the contact lithography. A coupled electro-thermal simulation models are used to get transfer and trans-conductance characteristics for both structures (shown in Figure 6). A threshold voltage of +1.02 V with a peak trans-conductance of 3.2 mS/mm is observed for β − Ga 2 O 3 epilayer on β − Ga 2 O 3 substrate structure. Whereas the β − Ga 2 O 3 epilayer on sapphire substrate shows a threshold voltage of +1.05 V with a peak trans-conductance 3.92 mS/mm. Output characteristics for both structures for depletion and enhancement mode are also The reduction in the drain current at high drain voltages can be interpreted by the following self-heating model [18]. The epilayer thickness at gate area is too thin to be neglected. Hence, the thermal impedance for the structure can be given by Where, k is the thermal conductivity of the substrate, tsub is the thicskness of the substrate and Lg is the gate length. As per the drift-diffusion and heat flow equation taking experimental temperature dependent thermal conductivity for both gallium oxide [19] and sapphire [20] is given by: Where, T is the position-dependent absolute temperature in β − Ga 2 O 3 and the approximate T −1 relationship is characteristic of phonon-dominated thermal transport. From the above equations thermal resistance and the thermal conductivity can be correlated. The thermal resistance is inversely proportional to the thermal conductivity of the material. As, β − Ga 2 O 3 has lower thermal conductivity compared to sapphire a higher thermal resistance has to be expected. which is responsible for the reduced output drain current. Output characteristics for these structure shows a Ron of 206 ω.mm and 215 ω.mm at lower drain voltage (Vd) for β − Ga 2 O 3 on sapphire substrate and β − Ga 2 O 3 on β−Ga 2 O 3 substrate structure respectively. β−Ga 2 O 3 on sapphire structure shows less Ron as compared to fabricated structure [12] which has a Ron of 215 ω.mm. The simulated structure shows a good sub-threshold swing of 95.95 mV/dec and 87.05 mV/dec for β − Ga 2 O 3 epilayer on sapphire substrate and β − Ga 2 O 3 epilayer on β − Ga 2 O 3 substrate respectively.We defined substrate properties (β − Ga 2 O 3 and sapphire) in the simulator to simulate two different structures. For both the structure all these scaled β − Ga 2 O 3 MOSFETs simulations shows a very high I on /I of f ratio of 10 11 leads to high performance, fast switching, low leakage and increased gate control over device.
In order to check the high voltage performance of these recessed-gate structures, we set gate voltage near pinch off (V g =0V in this case) value and keep on increasing the drain voltage. β −Ga 2 O 3 on β −Ga 2 O 3 structure and β −Ga 2 O 3 on sapphire structure shows a minor difference in the breakdown voltage. In case of β − Ga 2 O 3 on β − Ga 2 O 3 structure it is 462 V and for β − Ga 2 O 3 on sapphire structure it is 473 V. The minor change/increment in breakdown voltage may be due to the high thermal conductivity of the sapphire substrate.
The simulated device structure characteristics shows comparable results with compared to the fabricated data reported by Chabak et al. [12].

Conclusion
In this paper, TCAD simulation using Silvaco ATLAS 2D is performed for recessed gate β − Ga 2 O 3 MOSFET structure. In the simulated structure, recessed gate thickness has been varied to get for depletion and enhancement mode operation of the β − Ga 2 O 3 MOSFET. The depletion mode characteristics has been optimized with 150 nm active channel thickness (gate recess thickness of 850 nm). We further recessed it for 15 nm active channel thickness to get enhancement mode characteristics for the β − Ga 2 O 3 MOSFETs. For better understanding of gate recess thickness variations, simulations have been carried out for a span of recess thickness varying from 850 nm to 985 nm. For comparison the thermal and electrical effects caused by β − Ga 2 O 3 epilayers on β − Ga 2 O 3 substrate and sapphire substrate have been compared to each other. For the same parameters the β −Ga 2 O 3 on sapphire substrate structure shows an increment of 21.2% in drain current for the depletion type operation. β −Ga 2 O 3 epilayer on sapphire substrate shows a drain current density of 77.7 mA/mm with peak trans-conductance of 2.28 mS/mm for D-mode operation and 27.3 mA/mm drain current density with a peak trans-conductance of 3.92 mS/mm for E-mode operation. In contrast, β − Ga 2 O 3 epilayer on β − Ga 2 O 3 substrate shows a drain current density of 64.1 mA/mm for D-mode operation and 22.2 mA/mm drain current density with 3.2 mS/mm peak transconductance for E-mode operation with an I on /I of f ratio of 10 11 . Further improvement in breakdown voltage and performance can be achieved with incorporation of field plate structure and gate dielectric engineering. These simulations illustrate the advantages of scaled β − Ga 2 O 3 MOSFETs towards low loss high voltage switching power electronics applications.