Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata


 Quantum-dot cellular automata (QCA) are a novel dominant transistor-less computational nanotechnology. It is an appropriate candidate for the upcoming generation of quantum computational nano-electronics technology. The main objective of this research work is to present a QCA reversible logic circuits design such as the Toffoli gate (TG) and Peres gate (PG) and do the analysis of different parameters. In this paper, we propose a single layer coplanar method to solve this physical layout design and synchronization problem. The presented reversible logic gate (RLG) layout designs are implemented by Bijection functional algorithm for reduction of the number of QCA (quantum) cells, latency, and minimum design area. Also, the Optimized energy dissipation and effect of temperature on output polarization cell, of the proposed structure have been checked successfully using the tool QD-E (Energy) tool. The proposed QCA design has been verified by QCADesigner-E 2.2 tool using a bistable approximation and coherence vector engine. Finally, comparisons have been proposed RLG-TG and RLG-PG designs with the existing QCA design.


Introduction
The QCA is a novel emerging computational nanocommunication technology that is focused on the development of computer technologies. It is a promising alternative candidate to the conventional semiconductor based Very large scale integration (VLSI) and Complementary Metal-Oxide-Semiconductor (CMOS) technology. The QCA technology was first presented by Lent C.S. in 1994. The aim of QCA nanotechnology to developed quantum computing, information storage and nano-communication technology which is the principle, depends on quantum electronics theory for combined computational and transmission information [1]. The Reversible nano-computational techniques performed one-one mapping amongst the inputs and outputs vector. It is remarkable quantum dots nanotechnology for very fast processing speed, ultra-low power consumption with minimum energy dissipation, high switching frequency and very small size of circuits in nanometer.
In the reversible computational techniques not loss the digital information through the reversible computational circuits [2] and almost zero power dissipation are possible [3,4]. There are many areas for reversible logic and application another than QCA and quantum computational (QC) [5] such as optical computing, Low power CMOS technology [7], computer graphics [1], quantum cryptography [6], digital signal processing [7], and computer graphics [1]. The irreversible computations concept was proved in 1961 by Landauer, according to Shannon-Von-Neumann-Landauer (SNL) demonstrated in the Eq. (1), [3,8], for the energy (Ebit) required on a binary information transition. (1) The key points of the contribution to our work are as follows: 1. Design of coplanar single layer RLG-TG and RLG-PG by implementing Bijection functional algorithm for reduction of complexity of cell counts, layout design area (µm 2 ), quantum cost, and Latency by using QCADesign-E (Bistable-approximation-simulation engine) tool. 2. Optimized the energy dissipation of RLG-TG and RLG-PG by using novel simulation designer QD-E tool with considered (Coherence Vector (w/Energy) engine) and draw the QCA cell array coordinates map (ACM).

3.
To calculate the temperature effect on output polarization cell for presented ultra-efficient reversible (TG and PG) design with considering the size of QCA cell is 18nm×18nm.
The rest of the paper is organized as follows: in section 2 provides a fundamental of QCA technology including the cell polarization, basic gates, inverter, wire and QCA clocking. The proposed bijective algorithm and XOR gate design are explained in section 3 and section 4 respectively. The existing work of RLG-TG and RLG-PG is provided in section 5. The proposed work including the QCA layout and simulation result is addressed in section 6. The results analysis and discussion is explained in Section 7. The energy dissipation and AOP calculation part of the proposed structure are provided in section 8 and section 9 respectively. Finally, in section 10, we provide some concluding remarks.

Fundamental of QCA-design technology
The fundamental unit of QCA is "quantum cell or QCA Cell" with fabricate by four-quantum dots in a position at the corner of square, which are coupled by tunneling barriers by vertical capacitor [9] as demonstrate in Fig. 1. The quantum cell (QCA cell) has two different polarization states, define by P, i.e. logic 1 and logic 0 calls respectively polarization and [10][11][12][13][14][15] is demonstrated in Fig. 2. The digital logic gates for two quantum bits (qubits) are one of the most important parts of information processing in Quantum computing [12]. The neighbouring quantum cells by electrostatic force and information propagation based on coulomb (C) interactions. The cell polarizations (P) of the cell is defined Eq. (2) [10]. Where the electronic charge at corner side "i". The four Quantum dot cells are made by semiconductor material like Si/SiO2 and GaAs /AlGaAs [11].
(2)  The cell polarization in a the constructing all QCA logic gates by using QCA cell with their three basic key elements like QCA majority gate such as MAJ-3 and MAJ-5, wire, and inverter and [10,12]. The majority voter is shown in Fig. 3. The logic operation of MAJ-3 is representing in Eq. (3) [16][17][18][19][20]. If the logic OR and AND function of QCA can be realized from MG, by replacing any single input to fixed polarity value 1 and 0 respectively. The logic function is represent in Eq. (4), and Eq. (5) for majority OR gate and majority AND gate respectively [19].The three input QCA-AND-logic (QAL) layout design is shown in Fig.  4 and three input QCA-OR-logic (QOL) layout design is shown in Fig. 5.     The QCA inverter performs invert operation of the inputs is demonstrates in Fig. 6. The QCA inverter is a basic device that inverts ( an input signal (0 1, and 1 0) and the information is propagated from left cell to right cell. If the two ore more than QCA cells are contacted in series of the circuit act like wire. Layout structure of 90 0 QCA-wire is shown in Fig. 7 [13]. The signal flow in any QCA circuits controlled by Landauer clocks which has four different phases first-Switch, second-Hold, third-Release and fourth-Relax [21][22][23][24][25][26][27][28][29][30]. The phases of wires are calculated by Eq. (6), and the same phase shift of π/2, let considered the reference phase is [14]. ( π π π ). π (6)

Bijective algorithm mapping
The RLG performs unique operations one-to-one maps between inputs (I/P) and outputs (O/P) according to bijective algorithm. The bijective algorithm mapping function the number of O/P ports is equal to the number I/P ports shown in Fig. 8, and there is a one to one mapping between corresponding input vector bits [15] , Output vector bits [15] . The Toffoli in 1980 introduce the RLG represent unique number of inputs and outputs for any circuits [3,15]. A function f is a one-to-one correspondence or bijection if and only if function f is both one-to-one and onto (or both injective and surjective) in Eq. (7).
Example: Let and define function f as, is a bijection because each set value are correspondence one-toone maps.

Exclusive-OR design for RLG
The two input exclusive-OR logic gate has many application in reversible logic gate (RLG), arithmetic and logical unit (ALU), error detection and parity checking circuits and so on.
In the conventional EXOR logic circuits there is no need for one-to-one mapping, but in reversible XOR gate it is required to satisfy the bijective function with one to one mapping with the applied equal number of inputs and outputs. The minimum of complexity XOR gate design has been proposed in various research article works. The author A.N. Bahar et al. 2017 [16], 2018 [17] and A. Shiri et al. 2019 has been introduced the reversible XOR design. In this research work we have implemented a experimental QCA design of two input EXOR logic for designing of RLG on single layer design without any coplanar crossing or multilayer environment, it is shown in Fig. 9(a) [12,16,17], and output simulation waveform result is shown in Fig. 9(b). The mathematical functional equation of EXOR gate is represented in Eq. (8) [12,16,17]. The conventional EX-OR logic no need for one-to-one mapping but in reversible XOR gate required to satisfied the bijective function with one-toone mapping in same number of I/P and O/P functions.

Toffoli Logic gate (CC-NOT)
The three input-outputs RLG Toffoli (3×3), which used for reversible computational circuits design for quantum computers. The RLG-Toffoli gate is demonstrated in Fig. 10.
In this Toffoli logic inputs A and B directly maps to their respective outputs of X and Y. The mathematical equation is in represent in Eq. (10) for (A and Eq. (11) for (B ). The output Z of Toffoli reversible logic performs the operation (C ) in Eq. (12) [2,21]. The implemented QCA layout of Tomasso-toffoli gate is represented in Fig. 11. It has been designed by using one three input majority voter and two input XOR logic by using 90 0 QCA cells. In this design, used object of QCA cells are 21, design area is 26524.10 nm 2 = 0.03 µm 2 and latency count is 0.5. The output simulated results are verified by table is shown in Fig. 12 and Table 2.

Peres logic gate (PG)
The RLG-PG gate (3×3) is performs combinational operation of FG and TG. The quantum-cost of PG is four [6] calculated by Eq. (9). The three input-outputs vector mapping function denoted in Eq. (14), Eq. (15) and Eq. (16). The logical block design and QCA layout are represented in Fig. 13 and 14 respectively. The PG has utilized 44 quantum cells, latency obtained is 0.5 and entire design area is 43710.75 nm 2 = 0.043 µm 2 with used coplanar single layer scheme. The output simulated results of peres gate (PG) is given in Fig. 15.
The majority voter Equation of peres gate is representing in Eq. (17).   [23]. The proposed design comparison is represented in Table 3 and Table 4 for RLG-TG and RLG-PG respectively. The presented design improvement analysis is shown graphically in Fig. 16 for Toffoli gate and Fig.  18 for PG.
In the presented design have calculated energy dissipation by QCADesigner-E tool using coherence vector simulation engine setup (w/Energy). The proposed circuits design considered the main parameters of CVSE such as high saturation energy and low saturation energy of clock signal is 9.8e-22 j (Jules) and 3.8e-23 J respectively, the relaxation time for damping factor is 1e-15 s, relative permittivity is 12.90 for materials of GaAs and AlGaAs [32]. The period of input signals, total simulation time, and interval of each iteration step is 10e-12 s, 80e-15 s, and 1e-17 s respectively. In this calculation we have considered the stander cell size of QCA cell is18 nm × 18 nm, quantum dot-diameter is 5 nm and the distance between two quantum cells is 20 nm for single layer design. In the Table 5, and  1.6436e-003 -3.3904e-004 9.7812e-004 1.8532e-003 -9.8325e-005 1.4393e-003 -1.0658e-004

Array Coordinates Map For Cell Energy Dissipation
In this section, we have designed the array coordinates map (ACM) for reversible logic gates such as RLG-TG and RLG-PG. For this ACM, we have considered the radius of effect is 80 nm, relative permittivity of material as 12.90, and temperature T=1K by using novel QCADesigner-E (Energy) tool with coherence vector (w/Energy) engine setup. The array coordinates map for QCA cell energy dissipation (Sum_Ebath) according to clock synchronization (zone partitioning scheme) of reversible Toffoli logic gate and peres gate is shown in Fig.  18 and Fig. 20 respectively. The RLG-TG and RLG-PG ACM analysis, we have observed that maximum energy dissipated is 4.51e-003 eV = 4.51 meV and 3.72e-003 eV = 3.72 meV for array coordinates of QCA cell [Ax=4, Ay=2] at clock-0 and [Ax=6, Ay=7] at clock-1 respectively. It has been examined that the minimum energy dissipated is almost zero for all input variables and the fixed input cell is 0.00e-000eV = 0.0 meV. In Fig. 18 for RLG-TG array coordinates map observed the energy dissipated is 0.0 meV for inputs variable cells of array coordinates [Ax=4, Ay=1] for input cell-A, array coordinates [Ax=3, Ay=2] for input cell-B, array coordinates [Ax=7, Ay=6] input cell-C, and the fixed polarization P=-1.00 array coordinates [Ax=5, Ay=3] and [Ax=5, Ay=10]. The average energy dissipation (AED) per cycle for the RLG-TG array coordinate map is represented in Fig. 19. The maximum AED for RLG-TG is calculated for the cell in array coordinates

Average output polarization
The temperature effect is always observed in the output of QCA cells. The AOP calculate of implemented novel reversible logic gates of Toffoli gate and Peres gate at different temperature values 1K to 16K are shown in Table 7 and Table 8 respectively.  The effective temperature range of QCA circuits is 1K to 6K, in this temperature range average output polarization for the QCA output cell is very minimum changed [35,33] and the above this range polarization is drastically reduced. The AOP calculated by the following Eq. (20) [36]. The AOP in joule (J) versus temperature in Kelvin (K) plot for output cell polarization is illustrated in Fig. 22 for the reversible-Toffoli gate (TG) and Fig. 23 for reversible-peres gate (PG).
It is seen that proposed design provide a great value of output polarization is equal to ± 9.55e-001, ± 9.54e-001, and ± 9.94e-001 at QCA RLG-TG outputs such as X, Y and Z respectively and outputs polarization of QCA RLG-PG is equal to ± 9.94e-001, ± 9.94e-001, and ± 9.85e-001 for X, Y and Z respectively at considering the radius of effect is 80 nm at temperature T=1K.

Conclusion
The proposed nanotechnology-based reversible logic gates (RLG-TG and RLG-PG) implemented by a bijective functional algorithm on the coplanar single layer using the QCADesigner-E tool. It has been experimentally verified that the QCA based design has shown better results in terms of cell count, area, cell density, and latency. The presented novel RLG-TG and RLG-PG utilizes 38.23% and 21.14% lesser number of quantum cells as compared to existing optimal RLG designs. The proposed coplanar single layer in QCA technology for RLG-TG and RLG-PG utilizes 20.58%, and 34.84%, respectively less total design area as compared with existing designs with achieving minimum 0.5 clock-cycle delay, by Sasamal, T. N. et al., (2018) [23]. Finally, in this paper effect of temperature on output QCA cell or AOP, and energy dissipation analysis of QCA based effective design of RLG-TG and RLG-PG circuits has been carried out.