SPLAY TREE HYBRIDIZED MULTICRITERIA ANT COLONY AND BREGMAN DIVERGENCIVE FIREFLY OPTIMIZED VLSI FLOORPLANNING

Floorplanning is a basic designing step in VLSI circuit to estimate chip area before the optimized placement of digital blocks and their connections. The process of Floorplanning involves identifying the locations, shape, and size of components in a chip. The floorplanning is a hard problem since the consumption of energy and heat generation was high for the placement of modules. In order to improve the optimized floor planning, a novel Splay tree Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly Optimized Floor Planning (STHMAC-BDFOFP) technique is proposed. Main objective of STHMAC-BDFOFP technique is to efficient floor planning with minimum time. Initially, a number of modules are given with their connections obtained from benchmark dataset. In STHMAC-BDFOFP, a Splay tree-based non-slicing floor planning model constructing trees via modeling geometric relationship among modules. A splay tree is build after performing different operations namely splaying, join, split, insertion, and deletion on modules for floor planning. The constructed floorplan design is optimized by Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly algorithm. At first, the ant colony optimization is applied for finding the local optimum solution from the population of modules in the Splay tree with Multicriteria functions namely energy consumption, heat generation, space occupied, and wire length. Depends on fitness measure, the local optimum solution is determined. Then the global solution is attained by applying the Bregman Divergencive Firefly ranked algorithm. In this way, optimum modules in the splay tree are identified and obtain efficient floorplanning in VLSI design. Discussed results indicate that STHMAC-BDFOFP technique improves the performance of energy and heat aware floor planning as compared to conventional works.


Introduction
VLSI is the procedure for manufacturing numbers of transistors into single chip or Integrated Circuit. Physical VLSI design process discovers the physical position of active devices and interconnections among them within boundary of integrated circuit in which floorplanning is essential one. The floor planning is organizing a group of modules in rectangular chip region thus, the performance of wirelength, heat generation, space consumption are optimized. Resulting layout is called as a floorplan. The floorplanning problem has been proved by applying different evolutionary and optimization algorithms to lessen area and wirelength.
A 'Lion Optimization Algorithm (LOA) floorplanner was introduced in [1] for minimization of wirelength and area. However, the designed floorplanner failed to consider the heat and energy-aware floorplanning. In [2], a novel Interactive Self-Improvement based Adaptive Particle Swarm Optimization (ISI-APSO) was presented to offer better efficiency of floorplanning by considering wirelength and area. However, the temperature generation and space consumption were not reduced considerably.
A generic solution was presented in [3] to solve the problem of the rectangular floorplane. But it failed to cover other aspects such as the style, functionality, contextual constraints during the floorplanning process. A multi-objective design space exploration framework was developed in [4] for large-scale on-chip power grid VLSI designs. However, the designed framework was not efficient to provide the optimized VLSI design with lesser time consumption.
A Diffusion Oriented Time-improved Floorplanner was developed in [5] to optimize the temperature, chip area as well as wire length. However, the energy-aware floor planning remained unsolved. A hybrid genetic paired mutation algorithm was designed in [6] for Verylarge-scale integration (VLSI) placement optimization. The designed algorithm reduces the time complexity but it failed to solve the multiobjective constraints for efficient placement optimization.
Lion's pride inspired algorithm was designed in [7] to solve multi-objective VLSI floor planning to optimize the area minimization. However, the energy and hear aware optimization was not solved. Multi-Objective Bat Algorithm (MOBA) was designed in [8]. Designed algorithm reduces the wirelength and dead space but the other objectives such as heat generation, energy-based floorplanning were not considered.
In [9], A Self-Adaptive Particle Swarm Optimization (SA-PSO) was designed for VLSI design. But the VLSI design failed to extend other objectives namely chip area, size, critical path delay, and wirelength. A modified adaptive symbiosis based algorithm was presented in [10] to resolve multiobjective optimization issue of VLSI floorplanning. But it has more time complexity.
For efficient floorplans with lesser peak temperature, a genetic search algorithm and modified simulated annealing search algorithm were designed in [11]. A Genetic algorithmic program (GA) with harmony search algorithm was presented in [12] to lessen space and wire length. But time complexity of floorplanning was not minimized.
Different heuristic and meta-heuristic algorithms were developed in [13] for a multiobjective VLSI Floorplan. But the tree-based floor planning was not performed to reduce the complexity involved in the floor planning. A conjugate gradient scheme was developed in [14] to efficiently use the thermal resistance model for floorplanning. But the variety of objective functions is not optimized to improve the floorplan efficiency.
A temperature-aware floorplanning algorithm was designed in [15] depends on simulated annealing for efficiently minimize the chip peak temperature and reasonable area, wirelength, and time overhead. But the efficient heat generation minimization was not achieved. For fixedoutline 3D floorplanning, a fast thermal analysis technique was designed in [16]. However, the optimization technique was not applied for efficient floorplanning. A flow-based partitioning method was developed in [17] to reduce the wirelength penalty and area cost. However, the designed method failed to consider the heat, and energy-aware floor planning was not performed.
A communication-centric floorplanning algorithm was developed in [18] using Simulated Annealing for floor plan for minimizing the area of the entire floorplan. However, time consumption was not reduced. A flow-based partitioning algorithm was designed in [19] to reduce the wirelength. An improved multi-objective optimization technique using learning automata was developed in [20] based on the design of a variety of functional circuits.

Our contribution
Motivated by the above argument, in this paper a novel STHMAC-BDFOFP technique is introduced for fixed-outline floorplanning. Some key technical contributions of this STHMAC-BDFOFP are listed as follows,  To obtain efficient heat and energy-aware floorplanning in VLSI design, the STHMAC-BDFOFP technique is introduced. This contribution is achieved through the splay tree and Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly algorithm.
 To minimize the computation time of floorplanning, a splay tree-based non-slicing model is introduced. The splay tree is constructed through modeling the geometric relationship between the modules taken from the benchmark dataset. As a result, the modules are arranged in the tree.
 To obtain the optimal floorplanning in VLSI, Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly algorithm is introduced. Initially, modules in splay tree are initialized as population to find local best optimum through the fitness measure with multicriteria function namely energy consumption, heat generation, space occupied, and wire length. Then the global solution is obtained by applying the Bregman Divergencive ranked Firefly algorithm. This helps to obtain the energy and heat optimized floor planning in VLSI design. Besides, the wire length and space occupied results also gets reduced.
 Finally, extensive simulations are conducted using a benchmark dataset to evaluate the performance of our STHMAC-BDFOFP technique and other related works. The obtained result demonstrates that our STHMAC-BDFOFP technique is highly efficient than the other methods.

Paper outline
The rest of article is ordered as follows. Section 2 describes STHMAC-BDFOFP technique for solving the multicriteria floorplanning problem. Experimental evaluation of STHMAC-BDFOFP is presented in sections 3 with benchmark dataset. The simulation results are offered in Section 4. Section 5 concludes the article.

Proposal methodology
Floorplanning is the basic process of physical design in the VLSI domain. The floor planning is employed to estimate the relative position of blocks inside the fixed outline. The planning is to optimize the Wirelength and area occupied by the circuit. This directs the quite high attention to tend for VLSI floor planning. So our objective is to attenuate the chip area and fix the modules or blocks within the fixed outline. During this paper, a novel hybrid technique called STHMAC-BDFOFP is applied to enhance efficiency and accuracy than the conventional single optimization techniques. It is an essential design step to estimate the chip area by considering the optimal placement of modules and their interconnections. Each block consists of several hundred or thousands of cells that perform a specific operation. The block diagram of the proposed STHMAC-BDFOFP technique is designed as given below, Figure 1 given above illustrates the architecture of the proposed STHMAC-BDFOFP technique which comprises the two stages such as tree construction and optimization. At first, numbers of modules are gathered from dataset. Splay tree is constructed based on the relationship between the modules. Followed by, the hybrid optimization technique discovers optimal solution for achieving energy and heat aware floor planning. These two processes of the proposed STHMAC-BDFOFP technique are explained in the succeeding sections.

Splay tree-based non-slicing floor planning
The proposed STHMAC-BDFOFP technique starts to perform the floorplanning based on tree construction. In general, the floorplanning is performed based on two processes namely slicing and non-slicing operation. The slicing operation is the process of repetitively partitioning the floorplan either horizontally or vertically. Whereas, the non-slicing operation not bisecting the floorplan repetitively. In our work, the non-slicing operation is taken to create trees with number of modules from dataset.
Let us consider dataset ' ', and modules = 1 , 2 … that represents the floor plan membership. Each specific module has its height (H), width (W). Every module is free to rotate. The objective of floor planning is to present certain space for each module without any overlie between them. A splay tree is a binary search tree employed for quick access again. Splay Let us consider the modules = 1 , 2, 3 , 4 , 5 . In the splay operation, a node Figure 3 illustrates the tree construction based on the relationship between the modules.
To perform a splay operation on the node ' 1 ' and it moves to the root and each of other node moves ' 1 closer to the root. By applying the splay operations on the node after every access, the newly accessed nodes are kept near the root and the tree other nodes are balanced. Then the join operation is performed by concatenating the two auxiliary trees that the top node of one tree is a child of the bottom node of the other. Then the split operation is carried out by partitioning the chosen path into two parts at a particular node such as a top part and a bottom part. Finally, the Insertion process is carried out using the splay process. The newly inserted node becomes the root of the tree. In the deletion operation, the particular node is removed. Then the splay is performed to parent of the removed node to top of tree. Splay tree is constructed based on the non-slicing method.

Energy and Heat Aware hybridized Optimization
After the tree construction, based on input modules taken from dataset, hybridized Optimization is performed for optimized floor planning with lesser heat generation. The proposed technique uses multicriteria hybridized Optimization for finding the global optimum.
The single ant colony and firefly algorithm are hard to optimize the more than one objective functions at the same time to obtain the global optimum solution.
The ant colony optimization technique combined with the firefly algorithm effectively finds the global best solution through the ranking approach concerned with more than one objective function. The proposed technique uses multi-criteria optimization to find the best optimal paths in weighted graphs. The proposed optimization is a population-based metaheuristic to resolve complex multicriteria optimization issues depends on real ants behavior. The behavior of the ants is to search their food source. While searching the food source, the ants moved from one place to another by depositing an organic compound called pheromone on the ground. The communications between the ants are performed through the pheromone trails. The pheromone deposition is based on the amount of food the ant carries. Afterward, other ants also smell the deposited pheromone trails and follow that path. The shorter path from nest to food source having a higher probability of choosing that path since it has a more pheromone value. Figure 4 illustrates the flow process of the hybrid optimization to obtain the global optimal solution. Here, the ants are related to the modules in splay tree and the food source is represented as the multicriteria functions such as energy consumption, heat generation', space occupied, and wire length'. Initialize the population of the ants in the search space, For each ant in the population, the fitness is measured based on the multicriteria function.
The fitness is measured as follows, Where, denotes a fitness, ' ' symbolizes the aspect ratio to control the floor plan indicates a constant value ranging from 0 to 1. From the above (), the 1 , 2 , 3 , 4 indicates a multi-criterion function such as ' 1 is the energy consumption',' 2 ′ is the heat generation', ' 3 denotes a space occupied' and ' 4 indicates a wire length'. Let ' 1 * , 2 * , 3 * 4 * are the average value of the energy consumption, heat generation, space occupied, and wire length based on randomly generated 1000 kinds of floor plan calculation. Therefore, the objective functions are measured as follows.
Initially, the energy consumption is calculated as given below, Where, ' 1 ' indicates energy taken by module ' ', '∆ ' indicates temperature rise at module' ' with respect to transfer resistance at module ' '. Heat generation of Module is given below, Where, denotes a transfer resistance at module ' ', ' ' are power consumed by the ℎ module, ' ' stand for ambient temperature. Then the space occupied by the module is evaluated as given below, Where, 3 denotes a space occupied by the module , 'ℎ ' indicates a height and ' ' denotes a width of the th module. Then, the wire length of ' ' module is measured using Half-Perimeter Wire length (HPWL). The wire length of the module is formulated as given below, Where, 4 indicates a wire length of the module, ' ℎ ' and ' ' indicates greater and lower values of -coordinates of HPWL bounding box of th module. ' ℎ ' and ' ' denotes a higher and lower value of y-coordinates of HPWL bounding box i th module.
Based on the fitness value, the local optimum solution is determined from population.
Local optimum solution is finding out by sorting modules according to fitness function.
Once the modules are sorted according to the fitness, then the local optimum is  Output: Accurate Floor Planning in VLSI Design

Begin
Step 1: Collect a set of modules = 1 , 2 … from dataset ' ' Step 2: Construct a splay tree based on the relationship between modules Step 3: Initialize the population of modules in the search space Step 4: For each module ' ' Step 5: Measure multiple objective functions 1 , 2 , 3 , 4 Step 6: Measure the fitness ' ' Step 7: While (T < Max_iteration) do Step 8: Sorting the based on Step 9: Select local optimum ' ' in a splay tree Step 10: Initialize the population of fireflies Step 11:

Formulate light intensity based on fitness
Step 12: if ( > ) then Step 13:

Move firefly towards firefly
Step 14: end if Step 15: Update the light intensity +1 Step 16:

Rank fireflies according to the light intensity
Step 17: T=T+1 Step 18: end while Step 19: Best_solution← global best ' ' end Algorithm 1 illustrates process of Floor Planning in VLSI Design. Initially, the set of modules are collected from the dataset. Based on the relationship between the modules, the splay tree is constructed with different operations such as splaying, join, split, insertion, and deletion.
After that, modules in the tango trees are initialized and measure the multicriteria functions such as energy consumption, heat generation, space occupied, wire length. Based on the above-said function, the fitness is measured. After finding the fitness, the local best solution is identified by sorting the modules. Then the local best solutions are given to the firefly algorithm for identifying the global best. Initialize the population of local best solutions in search space. Then, the light intensity is formulated to fitness function based on multiple objective functions. If light intensity of one firefly is higher, then movement takes place. After movement, the position of firefly is updated based on Bregman divergence. The process gets repeated until it reaches the termination. Finally, the fireflies are ranked and find the best solution. As a result, efficient floor planning is obtained in VLSI design with minimum time.

Implementation scenario
In this section, the implementation of the proposed STHMAC-BDFOFP technique is discussed with the Benchmark Circuits Data Set. Initially, the apte Circuits is taken from the MCNC Benchmark dataset. In apte circuit, 9 modules are considered for experimentation.
Initially, the splay tree is constructed with the 9 modules taken from the apte circuit.
Here, the ants are related to the modules in splay tree and the food source is represented as the multicriteria functions such as energy consumption, heat generation', space occupied, and wire length'. Initialize the population of the ants in the search space,

Performance results discussions
The performance evaluation of STHMAC-BDFOFP technique and existing LOA floorplanner [1], ISI-APSO [2] are performed with metrics namely space occupied by circuits, heat generation, wire length, and processing time. The results of the various parameters are discussed using a table and graphical representation. The description of the various parameters are discussed as given below, Space Occupied by the circuit: It is calculated as product of width of every module and height of module. It is mathematically formulated as given below, Where, indicates a Space Occupied by circuit, 'ℎ ' denotes height of module, ' ' indicates width of module. It is measured in square of millimeter (mm 2 ).
Heat Generation: It is measured as the product of thermal resistance and power consumed by module. The heat generation is mathematically formulated as given below, Where, indicates a heat generation of i th module, ' ' is thermal resistance of i th module. ' ' indicates power consumed by i th module. It is measured in degree Celsius ( o C).
Wirelength: Wire length of circuit is calculated as maximum and minimum values of both ' ' and ' ' coordinates of each module. The length of the wire is calculated as given below, Where, ' ' and ' ' indicates maximum and minimum value of ' ' coordinates.
' ' and ' ' indicates maximum and minimum value of ' ' coordinates. It is calculated in millimeter (mm).
Processing time: PT is calculated as amount of time taken by the algorithm to find optimized modules for efficient floor planning. Therefore, the overall time is calculated as given below, Where ' denotes a processing time. is measured in milliseconds (ms).    [1] and 8% when compared to existing [2].

Figure 6 performance results of heat generation
The graphical representation of the performance results of heat generation using three methods is illustrated in figure 6. As shown in figure 6, where the horizontal axis illustrates the five different circuits taken from the benchmark datasets and the vertical axis demonstrates the heat generation (in degree celicious). The above simulation results illustrate the heat generation of the STHMAC-BDFOFP technique is minimal when compared to the existing LOA floor planner [1], ISI-APSO [2] respectively. This major enhancement is achieved by applying the

Conclusion
A new optimization algorithm called STHMAC-BDFOFP has been presented in the physical design of VLSI Chip with minimum time. STHMAC-BDFOFP is presented by combination of splay tree as well as hybrid optimization techniques. Here multicriteria floorplanning problem is solved by arranging and placing the modules in a chip in such a way that aim like minimum space occupied, lesser heat energy, wirelength area achieved. The splay tree is constructed based on the relationship between the modules. Then the integrated optimization technique is applied to the modules in the splay-tree. The hybrid optimization discovers the better modules which have lesser energy and heat generation for designing the VLSI Chip. This provides efficient floor planning with lesser computation time. Simulation is performed to estimate the performance of the STHMAC-BDFOFP technique over the two conventional methods and different performance metrics such as space occupied by circuits, heat generation, wirelength, and computation time. Statistical results illustrate that STHMAC-BDFOFP produces improved performance in minimization of wirelength, space occupied and heat generation than the conventional methods.