Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in Presence of Interfacial Trap Charges

The most notable accumulation of trap charges occurs on the oxide/semiconductor interface of MOS devices and it degrades the device’s performance and reliability. In this literature, we proposed a gate-engineered Schottky tunneling MOSFET(GE-ST-MOSFET) for ON state performance improvement, and a detailed analysis of the effects of interface trap charges (ITCs) on the DC characteristics and analog/RF performance metrics have been analyzed. In this device, the electrostatically doping-based dopant segregation layer (DSL) is introduced at the source side in the channel end by the Tunneling Gate(TG). A comparative study between the proposed GE-ST-MOSFET and conventional Schottky tunneling MOSFET(ST-MOSFET) has been carried out in presence of interface trap charges at the HfO2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{HfO}_{2}$$\end{document}/Si interface. A significant improvement in ION\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{I}_{\textrm{ON}}$$\end{document} and ION/IOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{I}_{\textrm{ON}}/\textrm{I}_{\textrm{OFF}}$$\end{document} ratio has been achieved 563 ×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document} and 1472×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document} respectively in the GE-ST-MOSFET as compared to the ST-MOSFET. To analyze the linearity behavior, higher-order transconductance parameters are also studied considering the effect of ITCs. Furthermore, the circuit-level performances of both devices are analyzed using the Verilog-A based models. The effect of OFF current variation on switching performance has been investigated. It has been found that the average switching delay and Power Delay Product (PDP) have improved by 97% and 81% respectively in comparison to the conventional device-based inverter. The GE-ST-MOSFET-based circuit also shows better immunity to interface trap charges. In addition, the implementation of the electrostatically doping concept for the proposed device could make fabrication very simple.


Introduction
In recent years, many novel nanoscale device architectures have been introduced for low-power circuit applications.These high-performing nanoscale devices can be considered as suitable candidates to replace conventional CMOS devices [1][2][3][4].Continuous downscaling in device dimensions of conventional MOSFET causes several short channel effects(SCE), higher leakage currents, reliability issues, and self-heating effects.In addition, the necessity of abrupt doping and shallow junctions limits the device performances [5][6][7][8][9].The ultra-thin fully depleted SOI MOSFETs can give better solutions to the above problems [8].As the source/drain series resistance(R SD ) is another problem in highly scaled B Arnab Som phec190004@nitsikkim.ac.inSanjay Kumar Jana skjnit@nitsikkim.ac.in 1 ECE, NIT Sikkim, Ravangla 737139, Sikkim, India thinner devices, several techniques like raised source/drain and heavily doped source/drain regions have been introduced to minimize the R SD problem but the above-mentioned solutions are very difficult to realize due to fabrication issues [10][11][12][13].The Schottky Barrier MOSFET(SB-MOSFET) can provide the best solution to the earlier-mentioned obstacles as it provides several benefits like an abrupt junction, lesser SCEs, and an uncomplicated fabrication process [10][11][12][13].However, it exhibits a lower ON current due to the metalsemiconductor Schottky barrier.Several research works have been reported to decrease the barrier height of SB-MOSFET for improving the ON current [14][15][16][17][18].A dopant segregated layer (DSL) has been introduced to decrease the Schottky barrier height and thus it increases the ON current, but a high thermal budget causes fabrication complexity [19][20][21][22].To overcome these difficulties several structures like source engineered [13], electrostatically doped DSL SB-MOSFET [23], Gate Drain underlapped heterostructure SBFET [24], Dual material gate SB-MOSFET [25] have been demonstrated.However, the ON state performance is still needed to Silicon (2023) 15:7265-7278 be improved.In [26], the authors have proposed Source Drain junction engineered SB MOSFET for Mixed Mode Applications with improved I ON /I OFF .In this proposed device, Subthreshold Slope is 93.3 mV/Dec which is needed to be improved.Recently dual material double gate Schottky tunnel MOSFET with floating gates has been proposed to improve the drive current considering 20 nm channel length [27].In this literature, the sub-threshold slope(SS) is 83.34 mV/dec, which affects the switching performance of the device and is unable to fulfill the criteria of 2026 nMOSFET as per ITRS roadmap [28].To reach high ON state performance parameters, at lower technology nodes, more studies are required.
In addition to these, reliability becomes a major issue for nanoscale devices because of two factors such as the higher electric field and higher temperatures due to the high density of transistors in a single chip.The trap charges at the oxide semiconductor interface are the key factors on which the reliability of a device depends upon [29].The process-induced damages during fabrication cause those trap charges [30,31].The different trap charges at the oxide/semiconductor interface deteriorate the device performance by shifting the flat band voltage [32].The trap charges can be acceptor-type or donor-type.In general, the accepter-type traps can always be located near the conduction band and donor-type traps can always be located near the valance band of the channel material.In Schottky barrier MOS devices, to reduce the Schottky barrier width at the source-channel junction, a larger electric field is required and as a result, it enhances the ON current.There is a high possibility of the existence of ITCs at the oxide/semiconductor interface in the Schottky barrier Tunneling devices [33].In Schottky barrier MOSFETs, the I OFF increases or decreases depending on the positive or negative ITCs respectively.As a result, the device's I ON /I OFF ratio also changes, which affects the original switching performance of the device, this is also a major reliability issue for digital circuit applications [34].Therefore, in this literature, the effect of trap charges on the DC and Analog/RF performances of gate-engineered electrostatically doped DSL Schottky Tunneling MOSFET with high-k dielectrics has been studied.In this work, we have used Schottky barriers in our devices because of many key benefits such as better off-current control, decreased parasitic capacitances, increased channel mobility because of reduced channel doping, and a low-annealing process required for the formation of source and drain regions.A simple and affordable fabrication process, complete reduction of bipolar parasitic effects, and large scalability are the other reasons for using Schottky barriers in these devices [35].This work also investigates the circuit-level performance assessments to analyze the effects of ITCs on the switching performance of the proposed device in presence of different ITCs and compared it with the conventional device.In the proposed GE-ST-MOSFET, the tunneling gate(TG) is introduced at the source side which induces an n-type charged plasma-based DSL layer.A calibrated simulation study has been carried out by the Silvaco Atlas simulator [36] for all the devices.It has been observed that there is a remarkable enhancement in transconductance (616×) and cutoff frequency (83×) of the GE-ST-MOSFET to the ST-MOSFET respectively.To investigate the circuit-level behavior, conventional and proposed devices have been simulated, then the Verilog-A model has been developed from the simulated results.The NMOS inverter circuits have been simulated using the Verilog-A based model in the Cadence Virtuoso platform and analyzed.The literature has been partitioned into five sections.Different device architectures considering various simulation parameters are shown in Section 2. The simulation results are analyzed in Section 3. The performances of device-based circuits are analyzed in Section 4. The conclusion part of the work is discussed in Section 5.

Different Device Structures and Different Simulation Parameters
Figure 1(a) and (b) show schematic views of the conventional device and the proposed device respectively.In this simulation study, the same input parameters are considered for all devices to have a precise comparative analysis.The source, channel, and drain lengths are considered as 20 nm respectively with Erbium silicide (ErSi 1.7 ) used in both the source and drain regions for all devices.The work function of ErSi 1.7 is 4.5 eV [23].Channel doping concentration of 10 16 /cm 3 has been considered for all the devices.Here, the Si film thickness (T Si ) is considered as 10 nm.HfO 2 is used for the gate oxide material in the GE-ST-MOSFET.The thickness (T OX ) of gate oxide material is 2nm.The work function of gate metal is 4.65 eV.Hafnium(Hf) with the work function of 3.7 eV is used to realize the tunneling gate(TG).The width of TG is 3 nm.For accurate calibration, the device structures with all parameters and dimensions are kept the same as published in [17].A good similarity between the experimental I D − V GS characteristics and simulated characteristics is seen in Fig. 2. To include the effects of tunneling across the metal-semiconductor junctions for all the devices, the universal Schottky tunneling model (UST) is used [13].
Two different mobility models, field-dependent mobility and concentration-dependent mobility have been incorporated into the simulation.To capture the effects of transport phe- Figure 3 shows the steps of process flow which can be followed for fabricating the proposed GE-ST-MOSFET.The deposition of HfO 2 on the lightly doped p-type Si wafer(10 16 cm −3 ) can be the first step of the process flow.Remote plasma Atomic Layer Deposition can be used to deposit HfO 2 thin films on Si substrates [41].Then etching can be performed.After that, the oxidation can be done in the pit up to 1nm followed by the implementation of the tunneling gate above the oxide layer [27].Metallization can be performed for the implementation of the Tunneling gate [35].During metallization Low-Pressure Chemical Vapor Deposition can be performed to achieve more purity and less chemical contamination [42] and then GATE 1 deposition can be done.In the next step, etching can be done followed by silicidation with ErSi 1.7 [18].Thin films of ErSi 1.7 can be grown on < 100 > orientation based Silicon substrate [43].Rapid Fig. 3 Fabrication steps of the process flow of the proposed device Thermal anneling can be performed to form ErSi 1.7 [27].After that, the device can be flipped and Oxidation can be performed to deposit HfO 2 .Then metallization can be performed to deposit GATE 2 and in the final step flipping can be done followed by oxidation.4(a) indicates a large barrier width between the source and channel junction for all devices at the OFF state condition (V gs = 0.0V, V ds = 0.5V) condition.It causes the probability of electron tunneling in the channel from the source, which is minimal.Under ON state condition (V gs = 0.5V, V ds = 0.5V), the Schottky barrier thining causes proper alignment in source and channel regions and that allows electron tunneling from source metal to channel region.

Simulation Results and Analysis
Figure 4(b) indicates that the tunneling width of GE-ST-MOSFET is less than that of the ST-MOSFET under ON conditions.As a result, the I ON increases in the GE-ST-MOSFET.Figure 4(c) indicates the electric field distribution with position along the channel for all the devices, considering different trap charges.In the GE-ST-MOSFET, the tunneling gate induces highly dense charge plasma, as a result, a larger electric field is produced at the channel region near-source end.The higher electric field increases the bandto-band tunneling rate (Fig. 4(d)), as a result, it increases the I ON .The results clearly show that the conventional ST-MOSFET is less immune to energy band diagram change than the proposed GE-ST-MOSFET considering different trap charges.The reason for the better immunity to ITCs can be explained by the change of flat band voltage.Due to the use of a high-k dielectric (HfO 2 ) in GE-ST-MOSFETs, the flat band voltage varies less when ITCs are present.That can be explained [44] by Eq. (1).The result also demonstrates the lower variations in both the transfer characteristics and output characteristics for GE ST-MOSFET in comparison with the ST-MOSFET for different ITCs.The threshold voltage is calculated for the drain current at 10 −7 A/μm by the constant current method.Table 1 compares the V th of the two devices, and it is observed that the GE-ST-MOSFET has a smaller V th due to the high-k gate dielectric, which enables improved gate coupling on the source-channel junction with increased tunneling phenomena of the charge carrier [45].Furthermore, the V th of the devices lowers (increases) in of positive (negative) ITCs due to degradation (enhancement) of the tunneling width in the source-channel junction.The decrease or increase in I ON is observed with negative trap charges or positive trap charges for both devices.Table 1 shows that negative ITC lowers I OFF , whereas positive ITC increases I OFF .This changes the device's I ON /I OFF ratio, which has an impact on the switching performance of the device.Table 1 indicates that a negative charge induces a lower OFF current for both the devices, which induces a larger I ON /I OFF ratio.Figure 6(a)-(b) shows that the I ON /I OFF ratio of the proposed GE-ST-MOSFET is less sensitive in presence of ITCs in comparison with the conventional ST-MOSFET.

Impact of Trap Charges on Analog/RF Performances
In this part, detailed comparative investigations are performed to study the influence of ITCs on the analog and Radio The controlling parameters in analog and Radio Frequency applications are the gate-to-source capacitance (C gs ) and gate-to-drain capacitance (C gd ).The above-mentioned parasitic capacitances(C gs , C gd ) are derived from a small signal analysis considering 1 MHZ as input frequency.Figure 7(a) and 7(b) show a graphical depiction of overall parasitic capacitance i.e C GG (C GG =C GS + C GD ) in relation to V gs at various trap charges.The result shows that due to positive (negative) trap charges the C GG of both the devices increases (reduces).The C GG of GE-ST-MOSFET is less sensitive to the trap charges in comparison with ST-MOSFET.One of the key parameters for this investigation is transconductance (g m ).The g m displays the device's electrical characteristics, which relate the I d to the applied V gs and define the device's current driving capabilities.We need a high g m for improved device performance.Figure 7(c) and (d) indicate the effect of ITCs on g m in relation to V gs .The result shows that g m grows with applied V gs for both devices, but it begins to decline after reaching the maximum peak owing to current saturation for the GE-ST-MOSFET.The proposed device exhibits higher transconductance and that is due to the thinning of tunneling width across the source and channel junction.Furthermore, as a result of the influence of positive (negative) ITCs, plots of g m move higher (lower) when the value of I d increases (decreases), resulting in an improvement (degradation) of analog/RF performance characteristics.One of the key parameters for high-frequency applications is the cutoff frequency( f T ).f T can be mathematically expressed as shown in (2).
Figure 7(e) and (f) show that the GE-ST-MOSFET has a greater value of f T than the ST-MOSFET because of higher g m in GE-ST-MOSFET.The figures show that the f T of both devices increases with V gs owing to an increase in g m , and for the GE-ST-MOSFET, after reaching its maximum value, it decreases due to carrier mobility saturation.Furthermore, we investigated the influence of ITCs on f T and saw that with positive or negative trap charges, the f T of both the devices increases or decreases, similar to the g m curve.The result also shows that f T of GE-ST-MOSFET is less sensitive to different ITCs than conventional one.
Gain Bandwidth Product(GBP) is also a key performance parameter for high-frequency applications while evaluating device performance.It is expressed by Eq. ( 3) The GE-ST-MOSFET has a larger value of GBP, which increases with V gs due to the TG-induced Schottky barrier lowering at the source-channel junction, which enhances the tunneling phenomena of charge carriers and results in higher g m .Figure 8(a) and (b) indicate the effect of different trap charges on GBP for all devices.GBP obtains a larger (smaller) peak in a direct connection with g m in presence of positive (negative) ITCs.The result also shows that GBP of GE-ST-MOSFET is less sensitive to different ITCs than conventional one.It is the most important method for estimating circuit performance by determining device speed.For high-speed applications, we need less transit time for reduced switching delay.Equation (4) gives the expression for transit time(t), which shows that f T has an inverse relationship with Transit time.The effect of ITCs on transit time is indicated in Fig. 8(c)-(d), where it is observed that the GE-ST-MOSFET shows a lesser value than the ST-MOSFET due to a greater value of f T .The proposed GE-ST-MOSFET exhibits negligible variation in transit time compared to Conventional ST-MOSFET while considering different trap charges.The comparison of the overall performances of the GE-ST-MOSFET with other reported results has been summarized in Table 2.The table shows the proposed device exhibits comparatively improved performance considering the supply voltages and channel length against other published results.Table 3 indicates the comparison of device characteristics of the GE-ST-MOSFET and ST-MOSFET considering different ITCs.It shows that the GE-ST-MOSFET gives better immunity to the trap charges than the ST-MOSFET.
For high-speed wireless communication networks, a device with a high signal-to-noise ratio is required to provide the best possible linearity performance with less power.Higher linearity performance leads to lower output distortion.If the system's linearity performance is not maintained, non-linearity behavior causes noise or distortion.Many researchers have reported that ITCs have a remarkable influence on the linearity performance of the device [29,33].As a result, it is essential to study the effect of ITCs on device linearity metrics.The nonlinear behavior of both the devices is investigated using higher order transconductance values, which are the higher order (2nd and 3rd order) derivative of I d for V gs , i.e., g m2 and g m3 .To achieve more linearity, these parameters should be as large as possible.g m2 and g m3 for the conventional device and proposed device in the presence of different ITCs are indicated in Fig. 9(a)-(d).This figure shows that the values of g m2 and g m3 increase (decrease) for positive and negative ITCs.The fluctuation in g m2 and g m3 for the proposed GE-ST-MOSFET is observed to be very insignificant when compared with the conventional ST-MOSFET with different ITCs.For improved linearity performance, higher peaks at lower V gs are desirable for g m2 and g m3 [33].The result also shows that the maximum value of g m2 and g m3 occur at lower V gs for the proposed GE-ST-MOSFET, demonstrating that the proposed device has higher linearity in the presence of ITCs.[47].In this article, N-MOS Inverters using proposed GE-ST-MOSFET and Conventional ST-MOSFET have been designed by the Verilog-A model and analyzed.We have considered 20 nm technology node while performing the simulation in Cadence Virtuoso simulator tool.ers, we calculated the total average delay(t av ) = [0.5 × (t pLH + t pHL )], where t pLH is the rise delay and t pHL is the fall delay.The t av in the GE-ST-MOSFET-based inverter(=70ps) is considerably small (36×) compared to the ST-MOSFET-based inverter (=2518.7ps).It can be attributed to the TG induced ON state Current improvement in the proposed device.Figure 10(f) indicates the variation of PDP for different ITCs.The GE-ST-MOSFET-based inverter provides 81% improvement in PDP than the conventional one.The higher switching speed in the proposed device causes a reduction in PDP.In addition to this, the GE-ST-MOSFET-based inverter gives lesser variation to the ITCs than the conventional device-based inverter which proves that the proposed device provides better reliability in Circuit-level also.

Conclusion
A precise investigation is made to analyze the impact of gate engineering on the overall performance of Schottky tunnel MOSFET.It is observed that the use of a tunneling gate at the source end lowers the Schottky barrier width and enhances the tunneling rate, hence improving the I ON .
The Tunneling gate along with the high-k dielectric in the GE-ST-MOSFET assists to reduce the SS.The use of TGinduced charge plasma-based DSL enhances the OFF-state performance.The GE-ST-MOSFET also gives better key analog/RF performances than other devices.The proposed device provides better immunity to the interface trap charges in DC and Analog/RF performances.In addition to that, to analyze the circuit behaviors of the corresponding devices, N-MOS inverters are simulated in Cadence virtuoso.Transient analysis and Power Delay Product analysis show that the proposed GE-ST-MOSFET is suitable and better reliable for high-speed switching applications.Furthermore, fabrication issues like random dopant fluctuations will not be present in the proposed device.

Fig. 2
Fig. 2 Calibration of our I D vs V GS Characteristics against the experimental data [17]

Figure 4 (
Figure 4(a) and (b) indicate the energy band(E-B) diagrams at different biasing conditions with and without different ITCs.These figures indicate the effects of different ITCs on E-B diagrams.Figure4(a) indicates a large barrier width between the source and channel junction for all devices at the OFF state condition (V gs = 0.0V, V ds = 0.5V) condition.It causes the probability of electron tunneling in the channel from the source, which is minimal.Under ON state condition (V gs = 0.5V, V ds = 0.5V), the Schottky barrier thining causes proper alignment in source and channel regions and that allows electron tunneling from source metal to channel region.Figure4(b) indicates that the tunneling width of GE-ST-MOSFET is less than that of the ST-MOSFET under ON conditions.As a result, the I ON increases in the GE-ST-MOSFET.Figure4(c) indicates the electric field distribution with position along the channel for all the devices, considering different trap charges.In the GE-ST-MOSFET, the tunneling gate induces highly dense charge plasma, as a result, a larger electric field is produced at the channel region near-source end.The higher electric field increases the bandto-band tunneling rate (Fig.4(d)), as a result, it increases the I ON .The results clearly show that the conventional ST-MOSFET is less immune to energy band diagram change than the proposed GE-ST-MOSFET considering different trap charges.The reason for the better immunity to ITCs can be explained by the change of flat band voltage.Due to the use of a high-k dielectric (HfO 2 ) in GE-ST-MOSFETs, the flat band voltage varies less when ITCs are present.That can be explained[44] by Eq. (1).

Fig. 4 Fig. 5 (
Fig. 4 Plot of E-B Diagrams for conventional Device and proposed device (a)-(b) under OFF-state and under ON-state in presence of different ITCs, (c) Plot of Electric Field distribution for ST-MOSFET and GE-ST-MOSFET in presence different ITCs, (d) Plot of Tunneling Rate for ST-MOSFET and GE-ST-MOSFET for different ITCs

Figure 5 (
a) indicates the electron concentration contour plot under ON state conditions.This figure shows the presence of tunnel gate-induced charge-plasma-based DSL at the source side in the channel end.This TG-induced DSL decreases the tunneling width across the source and channel junction of the proposed GE ST-MOSFET.The simulation results show that the electron concentration variation towards the different Interface Trap Charges is less for the GE-ST-MOSFET than the ST-MOSFET in the channel region.The effects of ITCs on transfer characteristics and output characteristics are indicated in Fig.5(b) to (d).The enhanced electric field causes a noticeable reduction in the tunneling width.So, the higher electric field in the GE ST-MOSFET has resulted in a significant improvement in the Schottky tunneling rate and thus enhances the I ON and I ON /I OFF ratio.The I ON has been determined for V gs = 0.5V and V ds = 0.5V.The I OFF has been determined for V gs =0.0 V and V ds = 0.5 V.The simulation result shows I ON for the proposed and conventional devices are 1.97×10 −04 A/μm and 3.5×10 −07 A/μm respectively.The simulation result shows a reduction in sub-threshold slope (43.6%) and I OFF (2.6 ×) in the Proposed GE-ST-MOSFET(SS=73.25mV/dec,I OFF = 8.10 × 10 −10 A/μm) in comparison with the Conventional ST-MOSFET(SS=130mV/dec, I OFF = 2.14 × 10 −9 A/μm).

Fig. 6 Fig. 7
Fig. 6 Plot of I ON /I OFF for (a)-(b) Conventional device and Proposed device considering different ITCs

Fig. 8
Fig. 8 Plot of GBP (a)-(b) for ST-MOSFET and GE-ST-MOSFET considering different ITCs.Plot of Transit time (c)-(d) for ST-MOSFET and GE-ST-MOSFET considering different ITCs

Figure 10 (Fig. 10
Fig. 10 Plot of (a) Schematic of N-MOS Inverter with resistive load (R D ) of 300-kilo ohm, Transient response of (b)-(c) conventional device based inverter and proposed device based inverter, the Power dissipa-

Table 1
Effect of different ITCs on V th , I ON , I OFF , and I ON /I OFF for the conventional and proposed devices