A 77-GHz Down-Conversion Mixer with +18.4 dB High Gain, +12.2 dBm OIP3, and Low Noise in 90-nm CMOS Technology

In radio-frequency (RF) transceiver system, the receiver is used to convert RF signal to low/medium frequency for signal processing and information gathering. In the paper, a novel high-gain, low-noise CMOS mixer is designed and analyzed. In the design, gain-boosting and PMOS dynamic switching current are employed to achieve better effects of noise cancellation and trans-conductance enhancement. In order to improve the mixer’s performance, the designed structure is mainly based on the double-balanced Gilbert lattice mixer combined with the parallel LC resonant and optimum biasing networks. The mixer shows high conversion gain (CG), low noise figure (NF), and low power consumption performances based on made possible by 90-nm CMOS technology. Operated at 77 GHz, the input third-order intercept point (IIP3) is −6.14 dBm, and the maximum conversion gain is 18.4 dB. At an IF frequency of 200 MHz, a bilateral band noise figure of 9.2 dB is recorded, while 6.96 mW is consumed with 1.2-V and 2-dBm LO power.


Introduction
The down-conversion mixer is a crucial component of the millimeter-wave receiver system. It can take the signal from the low-noise amplifier (LNA) of the preamplifier module for amplification and demodulation. There are many key parameters to evaluate its performance, including power consumption, inter-port isolation, linearity, NF, CG, impedance matching, and the cost. In recent years, people have witnessed 1 3 the development of high-frequency RF CMOS, and the next hot area of RF IC design will focus on V-band and beyond [1]. The potential applications include ultra-wideband long-range wireless networks, automotive image radar, and medical diagnosis instrumentation that all depend on high-speed information transmitting/ receiving.
Although CMOS passive mixers are becoming more and more common due to their high linearity and low flicker noise angle, the presence of conversion losses and inadequate reverse isolation in these mixers frequently results in dangerous NF and IQ crosstalk problems, necessitating additional complexity circuit modules to address the performance issues [2]. Contrarily, the Gilbert double-balanced mixer architecture is frequently utilized in millimeter-wave applications due to its compact layout, excellent port isolation properties, moderately high performance, and improved noise rejection for subsequent building blocks. However, the traditional Gilbert mixer shows the drawback of high NF and large power headroom, which materially reduces the total receiver performance. In particular, the local oscillator (LO) on/off switching phase of the mixer produces a considerable amount of flicker noise, which is conveyed to the output and reduces the transceiver's sensitivity. In the context of enhanced linearity and CG, the discharge structure of the circuit offers an interesting topology for a high-performance mixer [3]. In recent years, a number of studies have been reported on improving mixer noise. Major efforts have been made to suppress the indirect/direct noise mechanism [4] while enhancing the gain performance of the circuit by employing current bleeding and resonance techniques in the tail node of the switching pair. To achieve the low noise, the mixer uses a noise-reduction trans-conductor with noise-canceling technology found in LNA [5]. In order to suppress the noise effect of LO switching pairs, the inductive source degradation technology is designed, which can obtain good noise performance by improving the linearity and input coupling [6]. The dynamic current bleeding technique is also proposed to improve the flicker-noise performance [7]. It injects a dynamic current during the LO switching event, which is equal to the bias current of the LO switches. Additionally, a capacitor cross-coupled (CCC) trans-conductance is used as the input stage to reduce the NF of the mixer while providing wideband input matching [8]. However, these structures still need to be improved for the balanced merits. In particulate, it is still challenging to balance noise and CG within low-power restrictions while providing the growing bandwidth demands of multiband and multi-mode transceivers.
In the paper, a novel Gilbert down-conversion mixer is presented, which can work in 71 to 86 GHz. In the design, multiple improvements, such as the good CG, the low noise, and low DC power consumption, are implemented by the adoption of a PMOS dynamic current switching method technique with a tuned inductor, an improved gain-boosting method, and an active load design. The tuned inductor L T and PMOS cross-coupled pairs serve as the dynamic current switching circuit topology. The branch currents can independently control the DC current during the switching stage and the trans-conductance stage. This method reduces the current passing through the switching stages and lessens the parasitic capacitance of the switching devices, by which improving the switching efficiency, and reducing the flicker noise while increasing the gain. To further improve the gain of the mixer, a modified gain-boosting circuit in the trans-conductance stage is used to increase CG and decrease NF, in which the g m and the output resistance of the amplifier are increased and the second-order harmonics are suppressed.
A sine wave LO signal driver is used, which can be helpful for high gain and low noise. Additionally, the limitation of the switch-to-tail node parasitic capacitance C P of the mixer at high-frequency operation is substantially alleviated by the peak inductor L P . An IF buffer is added to the IF output stage to increase the gain, while can also separate the receive link from the digital baseband connection.
The proposed mixer architecture is designed and simulated based on 90-nm CMOS standard technology. The paper is organized as follows. Section 2 describes the general circuit structure of the down-conversion mixer, with circuit design enhancements for the performance metrics of CG and NF. In Sect. 3, comparative simulation results for the mixer are provided. Section 4 presents the results.

Improvement of the CG and the NF of a Gilbert Mixer
An active double-balanced Gilbert cell mixer is used for the investigation due to its high isolation between the LO and RF ports to eliminate the DC bias. Figure 1 shows the mixer's schematic diagram, including three primary components: the trans-conductance stage, the switching stage, and the load stage. The commutated RF current is down-converted to the IF voltage. To attain good CG and NF, the transistors should be operated in the saturation region.
The overall circuit diagram of the 77-GHz CMOS Gilbert double-balanced downconverter mixer is shown in Fig. 2. It is composed of a trans-conductor pair of six transistors (M 1 -M 6 ) acting as the RF input stage, a differential LO input common-source stage transistor (M 7 -M 10 ) acting as the switching stage for switching the bias current, a pair of PMOS transistors (M 11 -M 12 ) constituting the active output load stage, and the IF buffer for the IF signal output. As shown in Fig. 2, currentcontrolled switching devices and ideal transformers are used at each of the signal input ports to change the single-ended signals to the differential ones. The transconductance and the switching stages are matched to be 50-Ω impedance using an LC matching network with additional capacitors (C pad ) and inductors (L wire ). The structure is passive in order to decrease the active device loss and the NF. So CG is increased. Optimal biasing methods are employed at the input stage to improve the mixer's linearity while increasing the gain.
The mixer's performance is sensitive to the LO power, particularly to the balance between the gain and the linearity. The two differential ports of T2 are linked in series with coupling capacitors C 3 , accounting for the inductive impedance of their inputs for better matching the inputs of the LO switching stages M 7 -M 10 . Additionally, C 3 is used to isolate the DC level between the center ground tap of T 2 and the bias voltage of the switch to the transistor. In this way, the gate voltage swing of the switching device is immune to the LO power. The mixer's stability can be improved by preventing changes in 1-dB compression power (P 1 dB ) and CG by the power. The designed parameters of the proposed mixer are listed in Table 1.
The mixer's conversion gain is a crucial parameter. The switching pair approximates an ideal switch when the LO signal is an ideal square wave. Ref. [9] provides the voltage conversion gain of a typical mixer when the LO signal is an ideal sine wave.
(1) where (V GS − V TH ) sw is the switching tube's overdrive voltage, R L is the mixer load impedance, V LO is the magnitude of the local oscillation signal, and g m is the RF input stage's trans-conductance.
In order to get the desired voltage gain of the mixer, increasing g m would be an effective way. However, high g m would increase the circuit's power consumption, and boost the load impedance R L , thus limiting the CG of the circuit. The C P charging and discharging currents of the common-source nodes P and Q appear as spike pulses when the LO signal amplitude is large. A strong LO signal causes the high leakage current. If the overdrive voltage of the switch device is reduced, the size of the switch device is increased to remain the same the current flowing through the device, resulting in a reduction in the mixer's performance. To keep the device be operated by LO signal, the transistor is biased near the edge of the NMOS triode area, i.e., V GS = V TH . The MOS device may reach a narrower gate width W because of the gain-boosting and noise-canceling techniques utilized in the trans-conductance stage construction. This can decrease parasitic capacitance and lower the overdrive voltage, which results in a reduction in voltage gain.
The suggested mixer, as shown in Fig. 3, employs an enhanced gain-boosting circuit based on the g m -boosting approach and the noise-canceling technique utilized in the LNA in Ref. [10]. Transistors M 1 -M 3 are used to convert the RF input voltage into RF current. During the first stage, the common-gate transistor is an inputmatched network with an impedance of 1/g m . The input impedance of the trans-conductance stage is comparable to the input impedance of the common-gate amplifier when the noise caused by the common gate transistor is considered. A high input impedance and equivalent trans-conductance may be attained.

3
M 3 is a common-source transistor with negative feedback at the source stage, allowing the output device to become more linear in order to make up for the mixer design's IIP3 performance. The current from the LO stage is utilized by M 3 as the trans-conductance current when the transistor's gate is connected with the RF input. Its gain is increased due to the high output impedance of the common-gate stage matching network. In addition, in order to increase the equivalent trans-conductance of the circuit and suppress the noise, a g m -boosting circuit is added after the matching circuit. The g m -boosting circuit consists of two amplifiers (M 2 , M 3 ) in a common-source configuration. The topology has a higher gain compared to the common-source amplifier by adding the input signal to the gate of transistor M 3 .
The suggested trans-conductance stage also has the benefit of reducing noise. The trans-conductance stage has no more effect on the contribution of the flicker noise due to the frequency conversion to IF. As shown in Fig. 4, the noise in the noise reduction trans-conductance is mainly generated by M 1 , M 3 with parasitic resistance, and the total output noise current. M 2 has an upward noise current that partially cancels out the noise and reduces the trans-conductance level noise. The noise current of M 1 provides a negative noise voltage at the M 2 's gate port through Z in2 at node y.
Half circuit of the proposed improved differential trans-conductance stage To evaluate the sizes of M 2 and M 3 , high g m is necessary as it is proportional to the gain of the mixer, which can reduce the NF. So large M 3 is always required. However, big size could lead to large gate-source capacitance (C GS ) and gate-drain capacitance (C GD ), which could impact the circuit's input matching and increase the noise. Therefore, a PMOS dynamic current switching circuit with a tuned inductor is adopted in the design in the paper.
When the LO signal is positive, the switch turns on transistors M 7 and M 9 , while turns off transistors M 8 and M 10 . During the second half cycle, the switches are opposite. During the switching, the varying v n modulates the switching time, and the v n moves directly to the IF output to affect the NF of the circuit. As seen in Fig. 5, noise can be generated when both switching devices are turned on simultaneously, or at the zero-crossing point.
The goal of this research is to optimize the switching device flicker noise. In theory, the mixer switch stage's opening is controlled by the LO signal. 1/f noise is presented in reality. The switching device's output noise current is shown in Eq. 7: where I is the bias current flowing through the stage, v n is the 1/f noise, S is the slope of the LO signal, and T LO is the period of the LO signal.
Because the output frequency spectrum is affected by the switching device, the primary source of output 1/f noise is as follows: where K f is a constant related to the process and V 2 n,1∕f is the flicker noise voltage produced by the MOS transistor.
According to Eq. 8, it shows that the increasing of the switching transistor's size can reduce the noise. However, the parasitic capacitance C P can be increased during the processes of the charging and the discharging, which can generate the flicker noise and transmit to the output. It would be an effective way to minimize the noise pulse amplitude since the amplitude of the switch-stage bias current is doubled.
The output resistance can be increased by decreasing the bias current through the switching devices. This can lower the switching device's overdrive voltage without affecting the bias current through the trans-conductance stage. Dynamic Current-Bleeding (DCB) [11] is a method that can greatly improve noise performance as well as mixer gain performance. In the DCB approach, certain current is required to be injected at the moment of switching pair switching to eliminate the flicker noise at the output.
Due to lower flicker noise angle of PMOS device, the PMOS-based switching circuit can prevent the noise injection. It can sharpen the on/off of the LO switching stage by injecting current into the mixer core during the on/off switching. As shown in Fig. 6a, a similar fixed current injection is used in the traditional static current injection approach. It is ineffective for reducing the direct flicker noise since it creates more white noise and increases the effect of parasitic capacitance at the common-source node. If a dynamic current is injected at the common-source node, as shown in Fig. 6b, the problems encountered in injecting a fixed current can be avoided. However, there is still the influence of device capacitance on the noise of  Fig. 6b. To further enhance the NF of the PMOS switch current injection circuit, an efficient current injection technique is needed to lessen the injection of noise at all stages during the simultaneous conduction of the switching pair. In order to address these limitations and restrictions, a PMOS dynamic current injection approach with a tuned inductor L T is proposed, as shown in Fig. 6c.
In Fig. 6c, a tuned inductor L T and a cross-coupled transistor pair (M 13 -M 15 ) made of PMOS transistors are constructed. The voltages at the P and Q nodes are varied with the input LO signal, which are controlled by M 14 and M 15 when the current I is injected into the common-source node. The branch current of the mixer switching pair is decreased by injecting current without altering the branch current of the trans-conductance stage during LO signal oscillation transition, so minimizing the noise pulses at the mixer's output IF port. To make sure that only the dynamic current can be injected with the LO signal at the zero-crossing point, a bias voltage design is needed. The bias voltage is small at the zero-crossing point. When the cross-coupled PMOS pair is injected, the top current source is turned on with current I flowing into the common-source node. Away from the zero-crossing point, due to the higher bias voltage, the PMOS device is disconnected. So there is not any Fig. 6 Current injection technique. a Traditional static current injection structure. b Effect of the parasitic capacitance in dynamic current injection circuits. c Proposed PMOS dynamic current injection circuit with a tuned inductor injected current and the mixer works normally. With this method, the mixer's flicker noise is significantly reduced without adding more white noise. The mixer's linearity and bandwidth performance are not deteriorated at all. M 14 and M 15 need to be sized reasonably to inject enough current while avoiding extra parasitic capacitance to the switching pair's common-source end. In particular, the parasitic effect might produce a different flicker noise. Therefore, the tuned inductor L T is added in the PMOS cross-coupling pair to balance the PMOS device's device capacitance and enhance the mixer circuit's NF. According to the final testing findings, the circuit with the inductor shows 3 dB better NF than the other ones. Figure 7 shows the effects of the parasitic capacitors on the device. C GS in the saturation zone can influence the frequency response. The inter-stage parasitic capacitance C P can bypass some signal current to ground, which is another factor contributing to the considerable deterioration of the common-source commongate amplifier in the millimeter-wave region. The high-frequency operating characteristics of the mixer are substantially controlled by the parasitic capacitance at the tail nodes P and Q of the switch pair, as illustrated in Fig. 2, which also has a considerable influence on the mixer's NF and gain. Figure 8a shows typical method for removing parasitic capacitance by adding an inter-stage series inductor L S . A π-shaped matching network is created by L S with the parasitic capacitors C P1 and C P2 . In fact, since the difference between the common-source output resistance r O3 and the common-gate input resistance 1/g m is so considerable, it is difficult to match with only one inductor and two parasitic capacitors. Employing two series inductors for differential circuit design would need extra chip area.
A series-parallel inter-stage hybrid LC network is shown in Fig. 8b. The signal current shunted by C P2 is reduced by resonating L P with C P2 . The source of M 7 has a tail node impedance Z P of Fig. 7 The effect of parasitic capacitance on devices where r O3 represents the small signal output resistance of transistor M 3 .
Since the LO signal drives the switching device set in the saturation operation region, its Z P is quite small. Practically, resonance with C P2 requires a quite big inductor with large area. In addition, the PMOS' nonlinear capacitance tends to produce harmonics and create leakage for the insertion current with the increment of the PMOS size.
An improved LC resonant network with the resonant point at the LO frequency of 77.2 GHz is designed, as shown in Fig. 8c. A peak inductor L P at the commonsource end of the LO switching devices is added to improve the noise performance. It can reduce the flicker noise by canceling the influence of C P2 between the switching and trans-conductance stages, which also increases the CG due to the lack of signal leakage through the parasitic capacitance. The parallel inductor L T is the tuned inductor in the dynamic current injection module. The LC parallel resonant network with the inter-stage parasitic capacitor C P1 can neutralize the parasitic capacitance of the PMOS cross-coupling to the circuit. The tuned circuit can suppress the harmonics and the leakage current caused by the inductive filling effect in the nonlinear capacitance. The RF high-impedance circuit by the inductor and C P at circuit nodes P and Q can decrease the loss of the switching circuit near the RF frequency. The indirect formation of flicker noise by the LO big signal charging and discharging low-resistance channel can be reduced due to the closer frequency of the RF and LO signals. The proposed mixer circuit in the paper is assisted by the L P and L T resonance effects, with Z P being approximated by r O3 . The higher impedance of the switching stage corresponds to better common mode interference rejection at the RF input port. The inductor L P needs to be optimized for the design, and its value is chosen by maximum linearity and minimum NF. The peak gain of the mixer increases by roughly 12 dB and the noise decreases by around 9 dB when the inter-stage parallel inductors L T and L P are added.
PMOS cross pairs are utilized as active loads to reduce the load-level noise. The system noise is increased by the current injection module of the circuit. The crosscoupling approach is used to mitigate the noise deterioration. The gate length L of the MOS device can be chosen as large as necessary to reduce the flicker noise of the transistor and to lessen its channel modulation impact, in favor of increasing the output impedance and the gain of the mixer.
As long as the buffer circuit itself does not introduce excessive signal attenuation, no additional noise can be generated due to the high gain of the mixer before the IF buffer circuit. A self-biasing inverting amplifier is used as the IF output buffer circuit, including M 10 -M 13 and R 4 . The load circuit's output signal swing is considerable, and the buffer needs a sizable enough linear range to guard the mixer's linearity.
The input and output DC levels can be expressed as The transistor's stability factor is defined to be K > 1 over the whole frequency range. It is feasible to improve the output gain by adjusting the value of R 4 . To keep the amplifier's front stage from being impacted by the input signal's DC level, the off-chip blocking capacitors C 4 is used. The buffer circuit can reduce the complexity of the circuit since no additional bias circuit is needed. The flicker noise and the channel modulation effect can be minimized by increasing the gate length L and gate width W of MOS devices. Filtering is necessary to obtain the IF signal because fundamental signals and harmonic signals can leak from the RF and LO ports to the IF side. Capacitor filtering is employed since each harmonic signal's frequency is far from that of the zero IF signal.

Simulation Results
The mixer proposed in this research is implemented in TSMC 90-nm RF CMOS process and simulated with ADS (Advanced Design System). Figure 9a shows the way the overall circuit of the mixer is implemented. The RF and LO ports convert single-ended to differential signals using an external ideal transformer during simulation. Both the trans-conductance stage of the mixer and the LO switching stage employ the same load resistance and same bias for a fair comparison. Figure 9b shows a micrograph of the circuit with a chip area of 0.5 × 0.5 mm 2 for the core circuit of the mixer.
The simulation results for the mixer with various inter-stage network architectures are compiled in Fig. 10a and b, respectively. Figure 10a shows the simulation results of the LO input power versus the conversion gain. With RF frequencies 71-86 GHz and IF frequencies at 200 MHz, the mixer's CG varies from 12.6 to 18.4 dB. The maximum CG is achieved when LO power is 2 dBm. The PMOS dynamic current injection can increase the mixer's voltage gain. The mixer shows CG of 18.4 dB due to the addition of the inductor L P and the improved gain-boosting circuit in the trans-conductance stage.
As shown in Fig. 10b, the addition of the inductor L P lowers the mixer's SSB NF by 2.6 dB. The SSB NF is decreased by around 3.3 dB by adopting a dynamic current injection circuit with tuned inductor L T , with a final SSB NF of 12.2 dB. As shown in Fig. 11a, with the frequency from 71 to 86 GHz, the reflection coefficient S 11 is less than −40 dB at the RF port, and the transmission coefficient S 21 is less than −30 dB at the IF port. Figure 11b displays the test results for the LO-to-IF port, LO-to-RF port, and RF-to-IF port isolation, with isolation values larger than 50 dB, 60 dB, and 45 dB, respectively. The measurements reveal a significant LO leakage, which should be brought on by the layout design's asymmetries in the LO port matching network.
The mixer also provides enough linearity to maintain high gain and low noise. The IP 1 dB and the IIP3 at RF frequency of 77 GHz are −17.2 and −6.14 dBm, respectively. Figure 12a shows simulated and measured conversion gain and NF versus LO power, with fixed LO of 77.2 GHz and RF of 77 GHz. Figure 12b shows the relationship between IF output power and RF input power. Figure 13a shows the relationship between RF input power and the conversion gain. Figure 13b shows the impact of various IF frequencies on the gain performance with 40-dBm RF power. The mixer's core circuit consumes around 6 mA of current at a supply voltage of 1.2 V. Fig. 11 a Input return losses S 11 and insertion losses S 21 versus the mixer input frequency. b Simulation results of the isolation degree of each mixer port Fig. 12 a The simulated and measured conversion gain and NF versus LO power. b IIP3 (f LO = 77.2 GHz, f RF = 77 GHz) and P 1 dB measurement results A figure-of-merit (FOM) suitable for evaluating the performance of a downconversion mixer, a low-noise amplifier, or a receiver front-end can be defined as below [12]: where CG [dB] is the average CG in magnitude, IIP3 [dBm] represents the input third-order intercept point, NF [dB] is the DSB NF in magnitude, P DC [mW] is the power dissipation in milliwatts, and f RF is the value of the RF input frequency.
The FOM shown in Eq. 12 includes the most relevant parameters for evaluating down-conversion mixer for low-power, high-gain, low-noise, and high-linearity applications. Moreover, in numerous pieces of previous work, the information of NF and linearity are not available. To compare with them, the following simplified FOM can be used. Table 2 summarizes the performance of the proposed down-conversion mixer and compares the parameters with the recently reported mixers. Due to the application of an improved gain-boosting approach, the proposed mixer exhibits a significant enhancement in CG and the noise compared with the mixers published in [13] and [14]. Comparing with the 76-77-GHz CMOS mixer in [9], the proposed mixer shows better CG, larger port-to-port isolation, and larger FOM value. The proposed mixer consumes less power than the mixers described in [9], [14], and [15]. In comparison to the mixer described in [16], the proposed mixer offers better noise performance. It can be concluded that the proposed mixer exhibits a competitive performance with the low-power, the high-gain, and the low-noise performance.

Conclusions
In the paper, a novel mixer is designed, with the improved gain and better noise performance. In the design, an improved trans-conductance circuit and a PMOS dynamic current switching technique with inductance are adopted. At the input transistor's trans-conductance stage, the gain-boosting approach is used to increase the trans-conductance and the output resistance. At the same time, the circuit noise can be suppressed effectively. The second-order derivative trans-conductance is kept zero in the input transistor by using the optimal biasing technique, which enhances the linearity without decreasing the gain. To further increase the mixer's gain and better NF, a dynamic current injection circuit with a tuned inductor is added at the LO input stage. Simulation results based on TSMC 90-nm CMOS process show that the proposed mixer consumes only 6.96 mW with 1.2-V supply, and DSB NF of 9.2 dB, CG of +18.4 dB, and OIP3 of 12.2 dBm. The proposed mixer shows potential application in the field of vehicle radar system, providing the benefits of high-gain, low-noise, and low power consumption.