An All-in-One Biomimetic 2D Spiking Neural Network


 In spite of recent advancements in bio-realistic artificial neural networks such as spiking neural networks (SNNs), the energy efficiency, multifunctionality, adaptability, and integrated nature of biological neural networks (BNNs) largely remain unimitated in hardware neuromorphic computing systems. Here we exploit optoelectronic and programmable memory devices based on emerging two-dimensional (2D) layered materials such as MoS2 to demonstrate an “all-in-one” hardware SNN system which is capable of sensing, encoding, unsupervised learning, and inference at miniscule energy expenditure. In short, we have utilized photogating effect in MoS2 based neuromorphic phototransistor for sensing and direct encoding of analog optical information into graded spike trains, we have designed MoS2 based neuromorphic encoding module for conversion of spike trains into spike-count and spike-timing based programming voltages, and finally we have used arrays of programmable MoS2 non-volatile synapses for spike-based unsupervised learning and inference. We also demonstrate adaptability of our SNN for learning under scotopic (low-light) and photopic (bright-light) conditions mimicking neuroplasticity of BNNs. Furthermore, we use our hardware SNN platform to show learning challenges under specific synaptic conditions, which can aid in understanding learning disabilities in BNNs. Our findings highlight the potential of in-memory computing and sensing based on emerging 2D materials, devices, and circuits not only to overcome the bottleneck of von Neumann computing in conventional CMOS designs but also aid in eliminating peripheral components necessary for competing technologies such as memristors, RRAM, PCM, etc. as well as bridge the understanding between neuroscience of learning and machine learning.

Therefore, designing spike-based and low-power neuromorphic hardware systems that resemble the functionality, organization, and plasticity of BNN can not only accelerate the development of hardware artificial intelligence (AI) and benefit edge computing and smart sensing for Internet of Things (IoT), but also offer a platform to model plasticity-related learning disorders of the CNS.
Artificial neural networks (ANNs) are highly simplified, but most prevalent abstraction of BNNs that have already demonstrated breakthroughs in many applications including image classification, speech recognition, and game playing [1]. While in early days, performance of ANNs primarily relied on supervised learning, more recently, reinforcement and unsupervised learning using deep neural networks (DNNs) have shown remarkable improvements in challenging domains such as mastering the game of Go without input from human experts [2]. However, these computerscience-oriented learning algorithms require tremendous computational resources when implemented in neuromorphic hardware using traditional complementary metal-oxidesemiconductor (CMOS) technology leading to orders of magnitude higher power consumption compared to brain. One of the key differences is in the computing architecture, whereas CMOSbased computation embrace von Neumann architecture that physically separates the compute (logic) and storage (memory), BNNs dissolve such gap by placing neurons, the computational primitives, and synapses, the storage units, right next to each other.
Acknowledging the aforementioned limitations, non-von Neumann architectures leveraging silicon CMOS technology have been developed, such as the True North from IBM [3]. While the chip shows remarkably low power consumption of 63 mW for multiobject detection and classification in real-time using 1 million artificial spiking neurons and 256 million artificial synapses, at the implementation level, only marginal similarities with brain-like spike-based computing can be recognized. The benefits of spike-based computation was recently demonstrated through the hardware realization of spiking neural network (SNN) in a chip named Loihi from Intel [4]. Note that SNNs require stronger interaction between memory and compute in mimicking the rich spatiotemporal dynamics of spike-based encoding and learning rules. While SNNs promise to bridge the energy gap between ANNs and BNNs [5][6][7] hybrid ANN/SNN artificial general intelligence systems such as the Tianjic chip [8] are equally attractive accommodating both computer-science-based and neuroscience-based learning algorithms. However, these chips are based on CMOS technology, which is experiencing a steady decline in scaling and may not compete well in the emerging IoT market necessitating material discovery and device level innovations to closely imitate the functionalities of biological neurons.
In this context, field programmable gate arrays (FPGAs) [9] and crossbar architectures utilizing memristors [10,11], resistive random-access memory (RRAM) [12], phase change memory (PCM) [13][14][15], etc. with tunable conductance states are accelerating the development of energy efficient and non von Neumann computing architectures. These devices naturally lend themselves towards unsupervised learning using spike-time dependent plasticity and spike-rate dependent plasticity found in neurobiology. In fact, hardware SNNs have been constructed using memristorbased artificial synapses [16] and spiking neurons [17]. However, unlike BNNs, where specialized afferent neurons transduce the continuous time and analog valued information obtained from the environment into spike trains, memristive SNNs involve extensive CMOS-based peripheral circuits for spike encoding. Such pre-processing can ultimately limit the energy efficiency and scalability of memristive SNN architectures [18,19]. Furthermore, sensing is an integral part of BNN, which is unfounded in memristive networks necessitating integration of peripheral sensors.
Finally, neuroplasticity of learning in changing environment, and modeling of learning disabilities even at a high level of abstraction is yet to be demonstrated using memristive SNNs.
Here we demonstrate an "all-in-one" biomimetic hardware SNN which is capable of sensing, encoding, and spike-based unsupervised learning and inference using monolayer MoS2 based multifunctional optoelectronic and programmable memory devices. First, we use photogating effect in MoS2 phototransistor to directly sense and encode optical information into graded spike trains. Next, we develop MoS2 based encoding cells to implement spike-count and spike-timing based encoding algorithms. And finally, we use MoS2-based electrically programmable nonvolatile synapses for spike-based unsupervised learning and inference. Furthermore, we demonstrate low-power operation and adaptability of our SNN to learning under different ambient conditions mimicking neuroplasticity of BNN. Our SNN hardware also offers a platform to model learning disabilities and disorders of BNN at a high level of abstraction. To the best of our knowledge, this is the first experimental demonstration of an integrated SNN exploiting inmemory computing and sensing based on emerging two-dimensional (2D) layered materials and devices that can accelerate the development of energy efficient neuromorphic hardware.
The motivation behind using two-dimensional (2D) layered MoS2 as a hardware platform for neuromorphic computing is multifold. First, there are several demonstration of photodetectors [20], chemical sensors [21], biological sensors [21], touch sensors [22], and radiation sensors [23] using MoS2 based devices, which can naturally serve as artificial sensory afferent neurons eliminating the need for peripheral sensors for MoS2 based intelligent systems. Next, MoS2 being a semiconductor, almost all peripheral analog or digital signal processing units can be build using MoS2 field effect transistors (FETs) largely eliminating the need for hybrid design involving CMOS circuitry. Additionally, the atomically thin body nature of MoS2 allows aggressive channel length scaling without the loss of superior gate electrostatic benefiting high integration density. In fact, recent studies show high performance monolayer MoS2 FETs with the channel and contact lengths scaled to 29 nm and 13 nm, respectively [24]. Moreover, some of the early criticism of 2D FETs have also been successfully addressed in recent years through the realization of low contact resistance [25], high ON current [26], integration of ultra-thin and high-k gate dielectric [27], and wafer scale growth using chemical vapor deposition (CVD) and metal organic CVD (MOCVD) [28,29]. Similarly, MoS2 based microprocessors [30], analogue operational amplifier [31], and RF electronics components [32] have been reported. Finally, unlike silicon CMOS, MoS2 can enable flexible [33] and printable [34] electronic circuits adding value towards a MoS2 based biomimetic and neuromorphic hardware platforms [35][36][37].   Finally, MoS2 based non-volatile and electrically programmable synaptic arrays (Fig. 1g) imitate the visual cortex (Fig. 1c) where learning and inference take place. Note that all components of our SNN hardware are derived based on monolayer MoS2 FETs integrated with programmable analog memory gate-stack (Al2O3/Pt/TiN/p ++ -Si) (Fig. 1e) allowing in-memory computing and sensing overcoming the bottleneck of von Neumann architecture. Furthermore, as we will demonstrate, each module can be reconfigured to adapt to different learning environments. Fig.   1h-k, respectively, show an example experimental demonstration of pattern illumination using a light emitting diode (LED), sensory transduction using MoS2 phototransistor, spike encoding using MoS2 encoding module, and unsupervised learning using MoS2 synapses.
MoS2 used in this study was obtained from 2D crystal consortium (2DCC) [28] grown epitaxially on a sapphire substrate using MOCVD technique at 1000 0 C. Carbon-free and high-temperature growth ensures high film quality, which is critical for low-power operation of the SNN hardware.
The MoS2 film was transferred from the growth substrate on to another substrate with a back-gate stack that comprised of atomic layer deposition (ALD) grown 50 nm Al2O3 on Pt/TiN/p ++ -Si for the FET fabrication (Fig. 1e). As we will elucidate later, this gate stack resembles the floating-gate architecture used in FLASH memory devices and in spite of being present globally allows local programming of individual MoS2 synapses. Details on monolayer MoS2 synthesis, film transfer, and fabrication of the back-gate stack and MoS2 synapses can be found in the Methods section. Clearly, the device can be used as a photodetector. Note that, instead of LASER illumination, conventionally used to study photoresponse in monolayer MoS2 [38], we have used LED to provide optical stimuli since it represents more realistic lighting ambience where most neuromorphic sensors will be deployed. Finally, Fig. 1o shows the programmability of our MoS2 FET to achieve analog conductance states by applying electrical voltage spikes to the back-gate terminal which form the basis for synaptic learning as we will discuss in detail later. Overall, the platform offers all capabilities including sensing, computing, and non-volatile storage that are key to develop a fully integrated, reconfigurable, and biomimetic hardware SNN system.

MoS2 based neuromorphic sensor:
Monolayer MoS2 based phototransistors have been studied extensively in the recent years including our own work [20,[38][39][40][41][42]. The phototransduction mechanism in MoS2 PT is typically attributed to two mechanisms: photocarrier generation in the MoS2 channel and photogating effect arising due to charge trapping/detrapping mechanisms at the MoS2/gate-dielectric interface. Here we exploit the photogating effect in MoS2 PT for direct encoding of analog optical stimuli into spike trains (Fig. 2).  The detrapping mechanism can be rather slow and can take hours to several days, which is why the TH shift is visible post-illumination. Higher LED and more negative write naturally result in more trapping and hence larger TH shifts.
We exploit the unique photogating effect in MoS2 PT for direct encoding of the optical stimulus using spike-count and spike-timing based encoding.  First, the DS spikes ( Fig. 3b) are converted to voltage spikes, C1 (Fig. 3c), by using a switch capacitor cell (SCC1) that comprises of a capacitor ( 1 ) and a switch ( 1 ). The switch, 1 , is a MoS2 FET, which allows charging and discharging of 1 for every DS spike by switching between off-state and on-state. The magnitude of the C1 spikes are determined by 1 = DS C 1 � , where 1 ≈ 350 pF, and charging time, C = 100 ms. Note that the C1 spikes, as expected, follow the trend in DS . Next, these C1 spikes are applied to the drain terminal of another MoS2 FET ( 2 ), which is referred to as the spike reshaping cell (SRC) and the output current spikes ( S2 ) are recorded (Fig 3d). � by using another switch capacitor cell (SCC2) comprising of 2 = 350 pF and 3 . Finally, these C2 spikes with inverted polarity, P (Fig. 3f), are used for spike-count based programming of non-volatile MoS2 synapses for unsupervised learning.
As we will discuss later, the magnitude of P spikes play a critical role in determining the learning rates. Interestingly, our encoding module offers tremendous design flexibility since the magnitude of 1 , 2 , and the biasing of 2 can be adjusted for obtaining desired magnitude of P spikes. For example, Supplementary Information 4 shows that by changing the gate-bias for 2 , different magnitudes of S2 spikes and subsequently, C2 and P spikes can be obtained for the same set of C1 spikes. This can be exploited for adaptive learning under scotopic conditions by encoding lower number of spikes using higher magnitude P . The reconfigurability of the encoding module can also be exploited for modeling learning disabilities. For example if bright light is encoded into low-magnitude P spikes, potentiation of synapses can be severely limited invoking learning difficulty.   (Fig. 3h) are converted to analog voltage C4 (Fig. 3i) 3j). The magnitude of S4 saturate at ~10 µA for C4 > 1.5 V, which corresponds to DS = ST = 3 nA. Note that higher current levels are required for S4 since S4 is converted to S5 (Fig. 3k) using another MoS2 FET ( 5 ), which is used as a linear resistor following S5 = S5 S4 and hence both 4 and 5 must be operated in their on state (see Supplementary Information 6). 5 is also referred to as the resistor cell (RC). Finally, S5 with inverted polarity, P (Fig. 3l) is used for spike-timing As expected, lower number of spike invoke lower depression and vice versa, which can be exploited for spike-count based forgetting. Note that learning and forgetting capabilities enable unsupervised relearning using same synapses. Also note that smaller number of spike can achieve higher potentiation/depression if encoded using higher P/D . As mentioned earlier, this aspect can be exploited to achieve learning plasticity. For example, under scotopic condition the photocurrent spikes from the neuromorphic sensor can be encoded into higher magnitude programming spikes by the neuromorphic encoder to achieve necessary potentiation of the MoS2 synapses allowing a learning rate that is similar to the photopic condition. This will be illustrated further in the subsequent sections.

Spike-based unsupervised learning and inference using MoS2 synapses:
In this section, we demonstrate spike-count and spike-timing based unsupervised learning, forgetting, and relearning using MoS2 synapses under various synaptic conditions (Fig. 5). Fig. 1g shows the optical image and Fig. 5a shows the schematic of a fully connected 2-layer SNN with 9 presynaptic input neurons and 1 postsynaptic output neuron for learning and inferring patterns from 3×3 pixelated images. Fig. 5b shows   Video 3 and 4). Learning of the left diagonal followed by relearning of the right diagonal when potentiation and depression are both strong for g) spike-count and h) spike-timing based learnings (also see the Supplementary Video 5 and 6). Two sets of 9×1 synapses with synaptic weights for i) "Yes" postsynaptic neuron learned using the actual pattern and j) "No" postsynaptic neuron learned using the inverse of the pattern. The output currents from the "Yes" and "No" neurons are integrated using capacitors ( / ) to obtain and to determine the winner.  Video 2 and 3). Following are the key observations. When potentiation is weak but depression is strong, it is difficult to learn irrespective of the initial state of the synapses, however, when potentiation is strong but depression is weak, learning from LCS is fast, but forgetting and hence relearning from HCS is slow. This is expected since synapses that are For inference, we have used a 9×2 fully connected neural network implemented using two sets of 9×1 synapses as shown in Fig. 5i- For spike-timing based inference, a similar approach is adopted, except for the fact that only one voltage spike ( , = 1,2,3…, 8,9) is obtained at the output of the encoding module corresponding to each pixel of the 3×3 image with different spiking durations. In this case, Yes and No are given by Eq. 2. For the "Yes" neuron to be a winner, Yes > No and Yes ≥ Win , where Win is the winning threshold determined by the learned pattern. Clearly, the "Yes" neuron should be the winner only when the pattern similar to the learned one is inferred, whereas the "No" neuron should win for all other patterns. However, the experimental inference accuracy was found to be ~96%. This is because the patterns which contain one or two off-diagonal pixels in addition to the diagonal pixels also make the "Yes" neuron the winner. There are total 6 C1 + 6 C2 = 21 such patterns, which accounts for ~4% of all 2 9 = 512 patterns that are wrongly inferred. Note that if 3 or more pixels in addition to the diagonal pixels are bright, the "No" neuron wins. The inference accuracy was improved to 100% by making No ≥ Win even when only one off-diagonal pixel is present in the input pattern. This was accomplished through greater potentiation of the synaptic connections between the input neurons and the "No" neuron during the training with the inverse pattern resulting in an order of magnitude higher learned conductance value.
Finally, Fig. 6a-d and Supplementary video 6 show a complete demonstration of our SNN hardware from sensing to encoding to learning. Input pattern obtained by illuminating the blue LED (Fig. 6a) is directly encoded into graded spike trains using the MoS2 based phototransduction module ( Fig. 6b) with spike-count reflecting (Fig. 6c) reflecting the analog nature of the input stimulus. Graded spike trains are reshaped by the encoding module into corresponding programming voltages which is subsequently used for learning the pattern via MoS2 based nonvolatile synapses (Fig. 6d). For this demonstration, all synapses were initially programmed in their LCS and exact programming spike profiles obtained from the neuromorphic encoding modules were used without invoking any depression to learn the analog pattern. This demonstration highlights the fully integrated nature of our MoS2 based hardware SNN and distinguishes it from other hardware SNN architectures based on CMOS or emerging technologies such as RRAM, PCM, memristor, all-optic, as well as hybrid approaches.

Conclusion
In conclusion, we have experimentally demonstrated a fully integrated and biomimetic SNN hardware platform based on monolayer MoS2 that combines sensing, encoding, unsupervised learning, and inference. We have employed both spike-count and spike-timing based encoding, learning, and inference inspired by the energy efficiency of spike-based computing in the brain.
Similarly, we were able to show adaptive learning in photopic and scotopic conditions and impact

Methods
Film growth: Monolayer MoS2 was deposited on epi-ready 2" c-sapphire substrate by metalorganic chemical vapor deposition (MOCVD). An inductively heated graphite susceptor equipped with wafer rotation in a cold-wall horizontal reactor was used to achieve uniform monolayer deposition as previously described [51].

Competing Interest
The authors declare no competing interests