The paper present here analyses the modeling and performance of CMOS inverters using surrounded channel Junction less field effect transistor (SCJLFET). A mathematical model for different parameters like low input voltage and high input voltage, low output voltage and high output voltage, power dissipation, noise margin, rise time, fall time, propagation delay of the CMOS inverter circuit has been established. To design the model for various parameters, potential models at the channel source boundary and the potential at the channel drain boundary are considered. The variations in the voltage transfer characteristics, output current and the power dissipation with respect to the input voltage for steady-state conditions and transient states were evaluated for different gate dielectrics, gap lengths and gate oxide thicknesses. The models were compared with technology computer aided design (TCAD) simulation results for validation. The noise margin, rise time, fall time and propagation delay of the SCJLFET based Complementary metal oxide semiconductor (CMOS) inverter is evaluated and compared with those of a conventional junction less transistor. It has been observed that the SCJLFET exhibits an improvement in the noise margin and propagation delay compared with conventional junction less transistors.