Emerging Tunnel FET and Spintronics based Hardware Secure Circuit Design with Ultra-low Energy Consumption

Present CMOS technology with scaled channel lengths exhibited higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption with increased vulnerability. Additionally, spin transfer torque magnetic tunnel junction (STT-MTJ) and CMOS based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel FET (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET based sense amplifier based logic (SABL) gates have been proposed that achieve 3× lower energy consumption compared to Si FinFET SABL designs. Further, utilizing TFET SABL gates, TFET Pride S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption compared to FinFET designs. With resulted lower static power consumption, TFET SABL based crypto systems can show lower vulnerability to static power side-channel attacks. Besides, proposed STT-MTJ and TFET LiM gates achieves 4× lower energy consumption compared to STT-MTJ and FinFET designs. Moreover, these gates have been explored in logic encryption/locking technique that shows 3.1× lower energy consumption compared to STT-MTJ and FinFET based design.

Offshore manufacturing of integrated circuits (ICs) show increased vulnerability to hardware security attacks in the modern internet of things (IoT) era [1][2]. In support of this, the national institute of standards and technology has observed an exponential growth in hardware vulnerabilities in the last few years [3]. Moreover, the hardware security aided techniques or systems market is growing rapidly to avoid the counterfeiting of ICs [4]. There exist diversified hardware security attacks in the literature including hardware reverse engineering, counterfeiting of IC, and side-channel analysis (SCA). Among different hardware security attacks available, the SCA is effective in recovering the hidden secret information [5]. SCA utilizes the side-channel signals like power consumption, electromagnetic and photonic signals to reveal encryption key of the cryptographic circuits/systems [6]. Differential power analysis (DPA) process the power consumption information of encryption engine and require comparatively less effort in recovering secret key information [7]. Additionally, static CMOS logic style shows higher vulnerability to DPA attacks due to the data dependent power consumption profile [8][9]. To avoid this, several researchers explored novel logic styles that show higher DPA resilience [10]. Sense amplifier based logic (SABL), FinFET based secure adiabatic logic (FinSAL), randomized multi-topology logic (RMTL), homogeneous dual-rail logic (HDRL), secure positive feedback adiabatic logic, and differential symmetric pull-down network gates have been demonstrated to mitigate the data dependency on device power consumption [11][12][13][14][15][16]. Among the novel logic designs, SABL logic style is proved to be secure and show several challenges including higher power and energy consumption overheads [11]. Moreover, at sub-50nm channel lengths, CMOS SABL exhibited higher static power consumption that revealed the confidential information against static power SCA [17]. To avoid this, emerging hyperFET devices have been leveraged for DPA resilient SABL logic. However, this technique has exhibited relatively 3× higher energy consumption compared to CMOS [18]. Thus, CMOS SABL logic shown unavoidable disadvantages that need to be addressed for DPA resilient crypto graphic circuits with ultra-low energy consumption.
On the other hand, spin transfer torque based magnetic tunnel junction (STT-MTJ) has attracted wide attention due to their lower static power, non-volatility and higher compatibility with CMOS technology [19][20]. Moreover, integrating STT-MTJ and CMOS provided flexibility to build logic-in-memory (LiM) architectures for high speed data transfer [21]. Several researchers demonstrated logic gates and arithmetic circuits by exploring STT-MTJ based LiM cells [22][23]. However, STT-MTJ require relatively large write current to change the state that demands to maintain higher supply voltages [24]. Besides, CMOS technology scaling lead to serious problems including lower ON current, short channel effects, high power density, and unreliability [25]. Consequently, the STT-MTJ based LiM circuits exhibited large energy consumption due to the poor performance of MOS devices at scaled channel lengths (or supply voltages). In support of this, recent STT-MTJ LiM cells based crypto circuits exhibited increased energy consumption [26]. In the recent past, emerging tunnel FET (TFET) with its band-to-band tunnelling mechanism exhibited steep-slope characteristics (lower subthreshold swing) and higher ON to OFF current ratio (I ON /I OFF ) [27][28][29]. As a result, TFET based digital, analog and mixed signal circuits/systems achieved higher energy efficiency at lower supply voltages [30][31]. Apart from the low energy consumption and higher speed benefits, TFET devices with the special characteristics have been leveraged to enhance hardware security [32]. TFET based current mode logic and adiabatic logic have been proposed for differential power analysis resistant crypto systems [33][34]. TFET based compact polymorphic logic gates were designed by exploring the onset of tunnelling for both positive and negative gate bias [35]. The p-i-n forward current of TFET is explored as favourable feature to design true random number generator and low area overhead DPA countermeasure [36][37]. Thus, at scaled supply voltages, emerging TFET device has utilized to enhance hardware security of electronic systems [38]. Therefore, this work leverages TFET device characteristics for hardware security techniques that exhibit lower energy consumption. The SABL logic gates have been designed by exploring TFET device to reduce the energy consumption. The proposed TFET SABL gates are applied to design PRIDE S-box. Further, DPA attack is performed on proposed TFET SABL based S-box and also the performance is benchmarked with the base line Si FinFET designs. Additionally, STT-MTJ and TFET based LiM gates have been proposed to reduce the energy consumption. These designs have also benchmarked with STT-MTJ and FinFET based LiM gates. Moreover, the proposed LiM gates have been utilized in logic encryption/locking to obtain enhanced hardware security with ultra-low energy consumption. The rest of the paper is organized as follows: Section 1 demonstrates the state-of-the art and the motivation of the proposed work. Section 2 presents the device characteristics of TFET and STT-MTJ that are explored for circuit design. Section 3 demonstrates TFET SABL based logic gates and Sbox design for DPA analysis. Further, these TFET SABL designs have been benchmarked with FinFET designs. Section 4 presents STT-MTJ and TFET based LiM gates and logic encryption/locking technique. Moreover, the performance of the STT-MTJ and TFET based logic encryption circuit is compared with STT-MTJ and FinFET designs. The fabrication compatibility of TFET and STT-MTJ technologies is also discussed in this section. Finally, conclusions are drawn in Section 5.

Device Characteristics
This section presents device characteristics, Verilog-A models of TFET and STT-MTJ that are required for circuit design. Further, the motivation to introduce TFET into SABL logic and STT-MTJ LiM circuits have also been discussed.

TFET Technology
TFET device works based on band-to-band tunnelling mechanism and exhibits high ON to OFF current ratio. Several TFET devices experimentally demonstrated lower subthreshold swing i.e., below 60mV/dec [28][29]. This work explores LUT based 20nm InAs TFET Verilog-A models for circuit design [39]. The TFET based circuits have been benchmarked with equivalent LUT based 20nm Si FinFET designs [39]. The device architectures of n-channel TFET (N-TFET) and n-channel Si-FinFET (N-FinFET) are as shown in Fig. 1. Various device parameters considered in this model are shown in Table 1. TFET and FinFET symbols were created by calling Verilog-A models into the industry standard Cadence tool. Later, circuits have been designed using the device symbols created. Figure 2 shows the I D -V GS characteristics of both N-TFET and N-FinFET by varying gate-to-source voltage (V GS ) from 0 to 0.4V. Initially, when N-TFET switches OFF, it shows 2× lower OFF current compared to N-FinFET. With sufficiently positive V GS voltage, N-TFET switches ON and current through N-TFET increases abruptly due to the band-to-band tunnelling mechanism. From Fig. 2(a), it can be observed that N-TFET shows 3.4× and 1.23× higher ON current at V GS of 0.3V and 0.4V respectively. Further, NTFET exhibits lower subthreshold swing (30mV/dec) compared to N-FinFET device as shown in Fig. 2(b). From this, it can be concluded that, NTFET exhibits abrupt transition from OFF-state to ON-state (steep slope characteristics). TFET based circuits also achieve lower energy consumption due to high ON to OFF current ratio.
Recently, it has been revealed that SABL circuits become secure against DPA with the abrupt transitions from pre-charge to evaluation phase [18]. This behaviour requires abrupt transitions in the device characteristics that are used for circuit design. However, introduction of emerging steep-slope hyperFET devices in SABL based crypto system exhibited 3× higher energy consumption compared to CMOS based designs [18]. To reduce this energy consumption, this paper introduces steep-slope TFET devices in SABL circuits that can achieve ultra-low energy consumption with enhanced security assurance.

STT-MTJ Device Characteristics
Magnetic tunnel junction (MTJ) is a nano-stacked structure that consists of two ferromagnetic (FM) layers, separated by a thin oxide layer as shown in Fig. 3 [19]. Among two FM layers, the magnetic orientation of one layer is fixed and it is named as reference layer.
Conversely, the magnetic orientation of other layer varies in same or opposite direction to that of the reference layer, named as free layer. Upon providing sufficient current through MTJ, the magnetic orientation of free layer can be changed. When the magnetic orientation of free layer and reference layer point in the same direction, MTJ exhibits lower resistance (R P ) and it is called as parallel state. In contrast, if the magnetic orientation of free layer and reference layer point in opposite direction, MTJ exhibits higher resistance (R AP ) and it is called as anti-parallel state. Due to the non-magnetic layer, MTJ exhibits variation in resistance, it is defined as tunnel magneto resistance (TMR) (Equation 1). MTJ is supposed to exhibit high TMR for faithful reproduction of stored value.
Among several switching mechanisms available, spin transfer torque (STT) switching exhibits high TMR that is suitable to commercialize MTJs [20]. The perpendicular STT-MTJ devices eliminate the several challenges exhibited by in-plane devices. As a result, perpendicular STT-MTJ devices have attracted wide attention. This work explore a compact Verilog-A model of CoFeB/MgO perpendicular magnetic anisotropy STT-MTJ [21,40]. The STT-MTJ described in this model is

Energy Efficient and Secure TFET SABL based Crypto circuits
This section demonstrates TFET based SABL gates design and analyses. Additionally, PRIDE S-box is designed and evaluated by performing DPA attack on it. Furthermore, the energy consumption of TFET based S-box design is benchmarked with FinFET based designs.

TFET based SABL logic
The proposed TFET SABL architecture that explores TFET based differential pull-down network (DPDN) is as shown in Fig. 4. The logic gates based on this architecture works in precharge and evaluation phase. In precharge phase (clk=0), transistors T 1 , T 2 switch ON and T 3 switches OFF. Consequently, the outputs (Y, Y b ) discharges to ground because of inverters. In the evaluation phase (clk=1), transistor     Fig. 5 where K 1 and K 2 are denoted to indicate the connection between pull-up and pull-down networks. For example, consider the TFET XOR gate wherein input B is at logic '1' and B b is at logic '0'. As input A is at logic '0' and A b is at logic '1', the node N 1 discharges (through transistor T 2 and T 3 ) faster compared to node N 2 . As a result, the transistor I P1 in the inverter design (in pull-up network) switches ON and output Y b discharges to ground. When Y b discharges to gnd, Y charges to supply voltage (V DD ). Figure 6 shows the transient characteristics of TFET SABL gates at a supply voltage of 0.3V. It can be observed that TFET SABL gates exhibit proper functionality at ultra-low supply voltage of 0.3V with 100MHz frequency.

TFET SABL based PRIDE S-box design
This section performs the DPA attack on the TFET SABL based PRIDE S-box. Further, the performance of TFET SABL Pride S-box is benchmarked with FinFET design.

i. DPA mechanism on 4-bit PRIDE S-box
PRIDE is a block cipher based on substitution and permutation networks with a 64-bit input/output and 128-bit key for encryption [18]. The complete encryption of PRIDE cipher is performed in 20 rounds. One round consists of mainly three operations including XOR with round key, 4-bit parallel substitution box (S-box) operations followed by permutations and linear operations. As it is widely accepted that S-box is a most vulnerable part of block cipher. Henceforth, this work considers 4-bit PRIDE S-box to perform differential power   analysis attack [18]. The 4-input and 4-output PRIDE Sbox is a combinational block and the relation between inputs and outputs is expressed as the boolean equations (2-5).
The DPA attack is performed to retrieve the secret key information of crypto engine. The adversary contains the cryptographic algorithm with required input patterns to be applied. The DPA attack is performed on PRIDE S-box design which is shown in Fig. 8. Here XOR operations (as simple encryption) have performed between randomly generated inputs (D) and a 4-bit key (K). This produces the output that is applied to 4-bit S-box. Finally, S-box produces output (Y) by performing substitution operation. The detailed DPA attack mechanism is explained as follows.
• Firstly, the S-box is designed using Cadence Virtuoso environment and the current traces (i Vdd ) are recorded by applying random inputs (D) with a fixed key (K i ).
• Finally, each column of H matrix is correlated with all the columns of current trace matrix S. This results the correlation matrix (C) of size K×D. The correct key used for encryption will show the highest value of correlation compared to other keys.

ii. Security evaluation of TFET SABL based PRIDE S-box
The PRIDE S-box circuit is designed using proposed TFET SABL gates. The proposed TFET SABL based PRIDE S-box is compared with TFET based static complementary PRIDE S-box to highlight the security benefits. Both the designs have been implemented using 20nm InAs TFET technology. Each design individually simulated using 100 random inputs with a fixed key (K=5). The power traces which are obtained from the TFET static and SABL based S-box circuits have been depicted in Fig. 9. From this, it can be observed that the power traces of TFET SABL based S-box circuit have proved to be uniform compared to TFET based static complementary design. The obtained power traces have been sampled with a rate of 1000 and arranged as a matrix S. The resulted power trace matrix S is correlated with the hypothetical power values matrix (H) by following the DPA mechanism. Figure 10(a) shows resultant correlation coefficients of TFET based static complementary S-box design with all possible keys. It can be seen that the DPA attack performed on this design is successful and shows highest correlation coefficient for the correct key (K=5). Besides, the DPA attack performed on TFET SABL based S-box design is observed to be unsuccessful as shown in Fig. 10(b). The correlation coefficient of wrong key (K=12) is observed to be high compared to the original key (K=5). Moreover, the correlation coefficient of original key is hidden in the analysis result and cannot be observed by the adversary. This robustness is obtained from the favourable SABL structure and the sharp switching behaviour of TFET device.

iii. Performance benchmarking
The performance of TFET SABL based S-box design is benchmarked with equivalent FinFET SABL based S-box design as shown in Table 4. At a supply voltage of 0.3V, TFET and FinFET based designs have shown an energy consumption of 13.09fJ and 41.229fJ respectively. Thus, TFET SABL based S-box design exhibited 3.15× lower energy consumption compared to FinFET design at a supply voltage of 0.3V. Moreover, static power consumption of TFET SABL based S-box design is observed to be 3.5× lower compared to FinFET design. Due to this, TFET SABL based crypto circuits can exhibit lower vulnerability to static power side channel attacks.

STT-MTJ and TFET Logic-in-Memory (LiM) cells for Logic locking
This section presents the STT-MTJ and TFET based LiM gates and benchmarked with the STT-MTJ and FinFET based designs. Further, these gates are applied to logic locking/encryption and energy consumption is calculated. Moreover, the fabrication compatibility and challenges of TFET and STT-MTJ have been discussed.

STT-MTJ and TFET LiM based logic gates
The proposed STT-MTJ and TFET LiM cells are identical to SABL gates wherein STT-MTJ devices are explored to store one-bit input as shown in Fig. 11. This stored input can be accessed by logic tree and the final output of logic-in-memory cell is produced with the help of pre-charge sense amplifier. An additional writing circuit is used to write the data into STT-MTJ devices. The STT-MTJ and TFET LiM cell works in two phases that is similar to TFET SABL gates. When the clock signal is at logic '0' (clk=0), the sense amplifier works in precharge phase. In this phase, logic tree is disconnected from the sense amplifier, the transistors T 1 and T 2 switches ON. As a result, outputs Y and Y b of the cell discharge to logic 0. When the clock signal is at logic '1' (clk=1), the sense amplifier works in evaluation phase. In this phase, with the resistance difference between the MTJs and depending upon input, the charging/discharging speed of the two braches varies. As a result, the sense amplifier evaluates one output to be logic '1' while the other output to be at logic '0'. Figure 12 shows the STT-MTJ and TFET based AND/NAND, OR/NOR, and XOR/XNOR LiM gates corresponding to  anti-parallel configurations respectively. Consequently, resistance of MTJ 1 is lesser than that of MTJ 2 . With relatively lower resistance, current through MTJ 1 is greater than the MTJ 2 . As input A is at logic '1' and A b is at logic '0', the charge stored at node N 2 discharge (through transistor T 1 ) faster compared to node N 1 . As a result, the transistor I P2 in the inverter design (pull-up network) switches ON and output node N 1 charges to V DD . Due to this, Y and Y b result into to gnd and V DD respectively. Figure 13 shows the transient characteristics of logic gates at a supply voltage of 0.3V. From this, it can be observed that STT-MTJ and TFET based logic gates exhibited proper functionality at low supply voltage. Figure 14 shows the energy consumption comparison of STT-MTJ and TFET based logic gates with equivalent STT-MTJ and FinFET designs at a supply voltage 0.3V. STT-MTJ and TFET based gates achieved 4× lower energy consumption compared to STT-MTJ and FinFET designs. With the higher ON current of TFET devices, STT-MTJ exhibited lower propagation delay in changing its state. As a result, proposed LiM based gates achieve lower energy consumption. Further, these gates are explored for energy efficient logic encryption/locking application.

STT-MTJ and TFET LiM cells based logic locking
Logic locking is a hardware security technique that protects the circuit/design by adding key based gates into original design.   Consequently, the circuit/system cannot provide proper functionality without the correct key input. Figure 15 shows the block diagram of conventional and proposed LiM based logic locking in which both input and key will be provided to the design and proper functionality can be achieved upon applying correct key. In conventional logic locking technique a separate non-volatile memory is used to store the key bits. Recent research revealed that fetching of the data from external memory exhibits large energy overhead [19][20]. To reduce the energy overhead, this paper explore STT-MTJ and TFET LiM cells based logic locking wherein the STT-MTJ and TFET LiM cells are used to store and process the data. For example, consider ISCAS C17 benchmark (Fig. 16) that is explored for logic locking application [41]. This design uses six two input-NAND gates wherein two NAND gates are designed using STT-MTJ and TFET LiM cells that are operated by key inputs (K 1 and K 2 ) as shown in Fig. 16. As a result, the STT-MTJ stores key bits and the logic is processed using TFET based logic tree. The remaining four NAND gates are designed using TFET SABL based NAND gates as shown in Fig. 16. The Out 1 and Out 2 of ISCAS C17 circuit are expressed as equations 7 and 8.  ( ) For example, the key bits K 1 K 2 are fixed as "10", the equations 7 and 8 are simplified as equations 9 and 10 Figure 17 shows the transient characteristics of proposed ISCAS C17 based circuit at a supply voltage of 0.3V. With key bits of K 1 K 2 = "10", the circuit shows correct functionality as mentioned in equation 9 and 10. The energy consumption of STT-MTJ and TFET LiM cells based C17 circuit is calculated at a supply voltage of 0.3V. It can be observed that STT-MTJ and TFET based logic encryption circuit achieves a lower energy consumption of 6.96fJ. On the other hand, STT-MTJ and FinFET based logic encryption circuit shows energy consumption of 21.64fJ. From this, it can be seen that proposed design shows 3.11× lower energy consumption compared to FinFET designs. STT-MTJ and TFET LiM based logic encryption achieves lower energy consumption due to the higher ON current and low leakage characteristics of TFET at lower supply voltages.

Fabrication Compatibility of STT-MTJ with TFET
The homo-junction TFET and CMOS FinFET devices have been fabricated using identical manufacturing process since architecture of both devices is observed to be similar [28]. It is experimentally proved that complementary TFET devices fabricated in standard CMOS foundry exhibited higher compatibility for commercial production and enhanced flexibility for heterogeneous TFET-CMOS systems [28]. Several research groups have demonstrated the benefits of mixed MOSFET-TFET circuits/systems and corresponding layout rules with both simulations and experimental fabrication [31]. Besides, STT-MTJ exhibits higher compatibility with CMOS process by fabricating them in back-end-of-the-line. This encouraged the researches to explore logic-in-memory architectures that achieve low area and energy overheads. Recent research demonstrated the heterogeneous 3D integration for STT-MTJ based memory-on-logic applications that separates memory, logic blocks and stacks memory tire on top of logic block [20]. This STT-MTJ based 3D integration achieved silicon area saving with performance gain. CMOS exhibited higher compatibility with STT-MTJ and TFET is fabricated using identical manufacturing like CMOS. Therefore, the TFET technology can show ease of integration and flexibility in manufacturing with STT-MTJ. However, secondary effects including ambipolarity, p-in forward current and enhanced miller effect still exist in TFET which make it unpopular and less suitable for commercialization now [31]. More research efforts are require to make these emerging technology integration a reality.

Conclusion
Existing CMOS SABL based circuits and CMOS based STT-MTJ LiM circuits exhibited large energy consumption with increased vulnerability towards hardware security attacks. To reduce the energy consumption, emerging TFET is introduced into these circuits that achieved ultra-low energy consumption with enhanced security. TFET SABL based gates and PRIDE S-box design achieve approximately 3× lower energy consumption compared to FinFET designs while maintaining higher DPA resilience. Moreover, TFET SABL based crypto systems with lower static power consumption can show vulnerability to static power side-channel attacks. Additionally, proposed STT-MTJ and TFET LiM gates achieves 4× lower energy consumption compared to STT-MTJ and FinFET designs. The proposed STT-MTJ and TFET LiM gates have been explored in logic encryption/locking technique that shows 3× lower energy consumption compared to STT-MTJ and FinFET designs. STT-MTJ and TFET based circuits have exhibited higher compatibility in fabrication. However, STT-MTJ and TFET devices exhibited several second order effects including low reliability, process variations and other leakages (ambipolarity and p-i-n forward current) that make commercialization of these devices difficult. More research efforts are required in future from the device-circuit community to resolve the existing challenges.