Design and Investigation of Gate Stacked Vertical TFET with N+ SiGe Pocket Doped Heterojunction for Performance Enhancement


 In this paper, a novel delta-doped N + Silicon-Germanium Gate Stacked Triple Metal Gate Vertical TFET (Delta doped N + GS TMG VTFET) is proposed and investigated using the Silvaco TCAD simulation tool. Four different combinations were presented and compared with and without the gate stacking method and Si0.2Ge0.8 N + pocket delta-doped layer to render the optimized results. Among all, Delta doped N + GS TMG VTFET structure comes out with a very steep sub-threshold slope (9.75 mV/dec), 40 % lower than the first configuration of TMG VTFET. The inclusion of the N + delta-doped layer between the source and channel and gate will enhance the ON-state drive current performance by reducing the OFF-state leakage current. This happens due to the lower bandgap of the N + delta-doped layer cause narrow BTBT, which results in a high drive current. The Triple metal gate is designed to mitigate the ambipolar conduction by modulating the optimized wok function at 4.15, 4.3, and 4.15 eV. The distribution of the source channel in the vertical structure will enhance the device's scalability due to the electron tunneling moves in the vertical electric field direction. The optimally constructed structure demonstrates improved performance, such as a high ION/IOFF current ratio (~ 1013) and sub-threshold voltage (0.33 V). The results obtained from the proposed device make it suitable for the ultra-low-power device application.


I. INTRODUCTION
Over the past decade, CMOS has been found as a continuous scaled device in nanometer regimes to improve the integrated density, speed, and efficiency [1]. However, in the era of miniaturization, CMOS devices were continuously facing the problem of fundamental limits due to various short channel effects (SCE) such as hot-electron carrier, high subthreshold slope (SS) with the Boltzmann limit of 60 mV/decade [2,3]. To overcome all these technical issues, tunnel field effect transistors (TFET) are found to promise the candidate for the next-generation low power devices. TFET uses a band-to-band tunneling mechanism instead of thermionic emission [4,5]. This device can easily overcome the SS fundamental limit of 60 mV/decade with a low OFF state current [6]. In the TFET device, the tunneling probability T(E) is directly proportional to the ON-state current via quantum band to band tunneling mechanism using equation (1), given as: Where m*, Δφ, Eg, tox, tsi, and εox are the effective mass of the charge carrier, energy range, energy bandgap, gate oxide, silicon film thickness, and dielectric constant [6,7]. From the above equation (1) & (2), it can be concluded that the high dielectric constant and reducing bandgap optimize the implementation of TFET drive current.
However, conventional silicon-based TFET has various drawbacks, which include low ON state drive current (ION), a high threshold voltage (Vth), and ambipolar conduction with drain, induced current due to large silicon bandgap material [8][9][10]. Therefore, it is necessary to remove these constraints and further enhance the current of the ON-state as well as suppress the ambipolar behavior to allow it for different applications.
Multiple methods and devices to solve these problems structures to enhance the unit's efficiency have been suggested [10][11][12]. Since these techniques mitigate the ambipolar currents, they are known only at the cost of complexity in the fabrication method [13,14]. However, in the proposed device, we can overcome ambipolar by introducing the triple metal gate with optimized work functions.
To conquer these technological obstacles, the implementation of heterojunction TFET structures and source areas consist of new materials, such as germanium, silicon Germanium, or low bandgap Group III-V [15][16][17][18]. This will achieve a higher ION current and steeper subthreshold slope (SS). The use of high-k gate oxide in the stack with SiO2 is a significant way to improve further the SS of the short-channel TFETs [19][20]. The gate stacking process can be observed using high-k gate oxide like HfO2 in the stack with SiO2 is a significant way to improve further the SS of the short-channel TFETs [21][22]. The ratio of the width used of SiO2 with high-k gate oxide can be calculated using the Equivalent Oxide Thickness (EOT) equation (3).
It has also been experimentally demonstrated the utilization of vertical TFET (V-TFET) will remove the scaling constraints of the TFETs. This happens due to the mechanism under which the BTBT takes place parallel with the gate electric field that Design and Investigation of Gate Stacked Vertical TFET with N + SiGe pocket doped heterojunction for performance enhancement will significantly boost the tunneling current density as it is not directly dependent on the device's channel thickness [23][24][25]. To improve the current ratio, it has also been reported that by introducing the delta-doped or pocket layer in the middle of the source channel area of the low bandgap of Si0.2Ge0.8 material will improve the current ratio and the subthreshold slope, which was earlier restricted to the range of 30-50 mV/dec [26,27]. However, individually, these methods effectively work to the system but not efficient when it comes to the high-performance requirement of densely packed circuits.
In this paper, a combined effect of gate stacking and deltadoped SiGe heterojunction layer between the source-channel interface in the triple metal gate vertical Tunnel FET has been implemented for the first time to TFET structures. Also, to suppress the ambipolar current with ON-sate current's unintended performance, a vertical TFET with the triple metal gate is introduced and optimized by the work function engineering method through the TCAD simulation tool [28]. Finally, the proposed device, Delta doped N+ GS-TMG-VTFET (Gate stacked triple metal gate Vertical TFET) with N+ delta-doped structure, gives a detailed analysis of how the device design varies with the different parameter to optimize the performance and the characteristics of the device. This paper has been divided into three sections. The first part of the article contains the system's parameters, and in the second segment, simulation effects are discussed, while in the last segment, findings are concluded.    region is lightly doped (1 × 10 16 cm -3 ), the p+ drain region is heavily doped (5 × 10 20 cm -3 ), while the n+ drain region is moderately doped (1 × 10 18 cm -3 ) to mitigate the ambipolarity.

II. DEVICE STRUCTURE AND SIMULATION FRAMEWORK
In Fig. 2(b), the second configuration, a delta-doped n+ pocked with Si0.2Ge0.8, has been introduced to the first structure of TMG Vertical TFET with the dimension of 8 nm to 2 nm as length vs. height. This is done due to the lower bandgap range of the germanium material, which will boost the ON-state current by varying the mole fraction x. As the source of p+, Ge material consisting of a lower bandgap of 0.66 eV than that of Si (1.1 eV) is used. In contrast, the channel and drain regions use more extensive silicon bandgap material to maintain a low leakage current. A higher electron BTBT (e-BTBT) efficiency is achieved in this way, which significantly improves the ONstate current. In the third case, a layer of a 0.5 nm SiO2 layer is stacked with a 3 nm HfO2 layer, as shown in Fig. 2(c). Rest all the configuration will remain the same as that we have considered in the first one.
Finally, all the configurations jointly collaborated to form the fourth vertical structure for optimized results, as shown in Fig. 2(d). The value chosen for the device design parameter is summarized in given table I. To estimate the device performance, a TCAD 2D-ATLAS Silvaco device simulator has been used [28]. However, the simulated device is first calibrated with the reported work of Vertical TFET with the help of plot digitizer software. Conventional VTFET [29] Vertical TFET (Simulation Work)  Figure 3 represents the conventional calibrated Vertical TFET structure compared to the simulated device's drain characteristics curve [29]. The charge carriers' generations and their recombination at the Semiconductor-semiconductor and insulator-semiconductor interface are modeled on SRH (Shockley-Read-Read-Hall) Model. For better carrier transport simulation, we used the recombination model with dopingdependent mobility. However, the electrons' tunneling is estimated via the non-local band model to band tunneling [30,31]. This model will consider the point-to-point tunneling at the energy band gradient.
Additionally, this model also supports the abrupt heterojunction with any arbitrary tunneling barriers, a non-uniform electric field. It calls the results of direct tunneling and phono-assisted tunneling, so that accurate simulation results based on the models of both Kane and Keldysh [32,33] retrieved. The newton trap method is eventually invoked as a solution method . For the nonlocal path BTBT model, table 2 gives the comprehensive A and B parameters of both silicon and germanium.  Initially, the Id-Vgs characteristics will be compared for all the different device structures TMG VTFET, GS TMS VTFET, Delta doped N+ TMG VTFET, and Delta doped N+ GS TMG VTFET. Fig. 4 shows that the drain drive current is continuously improved by one order when introducing gate stacking and n+ delta-doped layer at the source-channel interface. In addition to the SS, 40-45 % of the improvement shown that to the TMG VFET. The mole-faction value x of delta doping layer N+ Si(1-x)Gex layer will decide the germanium percentage added to the device. For the proposed device, we have taken the value of mole fraction x as 0.8. As a result, the continuous lowering in the band gap between source to channel region, which boots the tunneling current, will increase the device drain current. The impact of Gate stacking improves the SS by 20-25 % because the work function increases the band's slope bends along with the bands' narrowing. Molecular beam epitaxy (epitaxial growth technique) and chemical vapor deposition will allow the growth of these kinds of heterojunctions. The overall performance of the Delta doped N+ GS TMG VTFET design was found to be the best without affecting the OFF-state current. A comparison chart of threshold voltage (Vth) and SS for different configurations is shown in table 3. The subthreshold slope is defined as the change in drain current per decade with respect to the change in gate-source Vgs voltage. However, the threshold voltage of the TFET is derived from the constant current method at the value of Vgs, for which the drain current cut the line at 10 -7 A/um. It can also be defined as the minimum energy barrier for which the charge carriers start tunneling from the source valance band to the channel conduction band. In simple words, "the applied gate voltage for which the energy barriers narrowing start to saturate" [34]. Figure 5 shows the variation of energy band diagram for all the different device structures TMG VTFET, GS TMS VTFET, Delta doped N+ TMG VTFET, and Delta doped N+ GS TMG VTFET, respectively. It is noted from the figure that tunneling is maximum narrower for the Delta doped N+ GS TMG VTFET concerning other device designs. This happens because of the lower bandgap material introduced between the tunneling barrier to reduce the overall path and resulting in high electron tunneling.   6 shows the distribution of the charge carriers' concentration of (a) hole and (b) electrons, respectively. Both the carrier concentration distributed in a vertical direction from source to drain. Figure 6(a) observed that the concentration of the holes will start decreasing suddenly at the initial level of the channel length (i.e 50 nm). Moreover, the holes concentration will more deteriorate for the configuration of N+ TMG VTFET and N+ GS TMG VTFET. This happens due to the addition of N+ delta doped layer at the source-channel interface will increase the electron concentration.
In the next Fig. 6(b) distribution of the electron charge carrier concentration with respect to the vertical position of the device and case is the vice-versa condition of the holes charge carrier concentration. It will compare the Delta doped N+ GS TMG VTFET configuration having the highest graph variation compared to the TMG VTFET, GS TMS VTFET, Delta doped N+ TMG VTFET structures, respectively. This happens due to the increase in the number of electrons that will proportionality increase in the tunneling current and also improve the drain drive current. Recombination rate and band to band tunneling rate for the electron and the holes are plotted and validated for all four structures. From Fig. 7, it is depicted that the structure which consists of the N+ delta doping layer will have a negligible recombination rate with respect to the vertical dimension of the device design. It happens due to the lower bandgap material (N+ delta doping) introduce in between the tunneling path will mitigate the minority charge carriers to accelerate the overall process.  show the e-band to band tunneling rate with respect to the vertical distance of the device design. The maximum electron tunneling rate can be differentiate from the non-delta doped structure. Due to N+ delta doping the band gap between valance to the conduction band will become narrower at sourcechannel inter junctions that will allow to flow high tunneling rate. Now in Figure 8(b) holes band to band tunneling rate for all the four configurations into order to find the determine the holes impact on the tunneling rate. However, the it is observed form the figure that the hole tunning is almost same for all the four different structures i.e. very smaller variation in graph analyzed.  In Figure 10, we will discuss the electric field validation for all four structures. It can be analyzed from the figure that the electric field is high for the configure of Delta doped N+ TMG VTFET and Delta doped N+ GS TMG VTFET rather than TMG VTFET and GS TMS VTFET. This is because of the linear relation between the surface potential and the electric field. As a result, the electric field also high before the sourcechannel interface, which causes more tunneling phenomenon when the barrier will suppress.  Using equation (4) to (7), we can find out the relation between transconductance and Subthreshold Slope [26]. Form equation (7), the transconductance value inversely dependent upon the SS value. Since Delta doped N+ GS TMG VTFET holds the lowest SS value, it comes with the highest transconductance value, as can be justified from Fig. 11.

IV. CONCLUSION
An N+ delta-doped SiGe layer Gate Stacked Triple Metal Gate Vertical TFET (Delta doped N+ GS TMG VTFET) is employed in this paper. Four of the different configurations: 1. TMG VTFET 2. Delta doped N+ TMG VTFET 3. GS TMG VTFET 4. Delta doped N+ GS TMG VTFET has been analyzed and compared with different electrical parameters using the 2D Silvaco TCAD simulation tool. The proposed structure takes advantage of a triple metal gate to mitigate the ambipolarity, and gate staking with the high k dielectric constant will improve the On-state current. The gate stacking combination of SiO2 and HfO2 will improve the controllability of the device tunneling current. The N+ SiGe delta-doped layer will narrow the tunneling path due to the lower bandgap of germanium and enhance the band to band tunneling drive current. The vertical structure shows the advantage of having the source-channel distribution in the vertical direction, directly proportional to the vertical electrical field. The optimized structure simulation result will show a very high ION/IOFF ratio (~10 13 ). The ON-sate and OFF-state current reported to be 1.4 × 10 -4 A/µm and 7.45 × 10 -18 A/µm with 0.33 V as sub-threshold voltage. In the case of short channel Effect, the sub-threshold slope is rendered as (9.75 mV). These results show the superiority of the proposed device in terms of SS and drive current. Therefore, with these results, it can be concluded that the proposed device (Delta doped N+ GS TMG VTFET) is a promising candidate for power device technology application.

Declarations
Funding statement: The author(s) received no financial support for the research, authorship, and/or publication of this article.

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