Scalable High-Speed Hybrid Complementary Integrated Circuits based on Solution-Processed Organic and Inorganic Transistors

Printed electronics offer a cost-efficient way to realise flexible electronic devices. The combined use of p-type and n-type semiconductors would yield silicon-like integrated circuits with low power consumption and stability. However, printing complementary circuits is challenging due to a lack of suitable material systems. To counter this, we employed a hybrid system to integrate p-type organic semiconductors (OSCs) and n-type amorphous metal oxide semiconductors (MOSs). These damage-free patterned OSC- and MOS-based thin-film transistors with improved process durability allowed the fabrication of hybrid complementary circuits on flexible substrates. These inverters functioned well even after exposure to air for 5 months. A large noise margin and power gain of 38 were realised with a supply voltage as low as 7 V. Furthermore, a five-stage ring oscillator with a stage propagation delay of 1.3 µs was achieved, which is the fastest operation ever reported for printed, flexible complementary inverters.


Introduction
The rapid implementation of Internet of Things (IoT) in everyday applications and devices has increased the demand for trillions of electronic devices. Though the conventional Si-based technology can meet the electrical performance requirements of these devices, the complex, vacuum-based, and high-temperature processes required to fabricate them are driving up costs. In addition, in terms of flexible applications, the mechanical properties of conventional devices are far from satisfactory. Printed electronics, which allow the ideal production of lowcost and flexible electronic elements, are of vital interest to both industry and academia.
Printing complementary integrated circuits (ICs) with high-mobility and performancebalanced p-and n-channel thin-film transistors (TFTs) is crucial in advanced applications such as radio-frequency identification (RFID) tags and sensors as they can enable high operation speeds, low power dissipation, high noise margin, and an easy and compact circuit design.
Among the available printable semiconductor materials, organic semiconductors (OSCs) are the most promising owing to their low fabrication temperature and high compatibility with flexible substrates 1 . Thus far, several materials and device-fabrication methods have been developed to facilitate the implementation of OSCs in ICs, especially for single or wellaligned crystals 2−9 . Meanwhile, solution-processable amorphous metal oxide semiconductors (MOSs) have been developed as potential candidates for printed n-channel TFTs 10−15 because of their high electron mobility, excellent uniformity, and good ambient stability. Despite the advancement of p-type OSCs and n-type MOSs, both systems are encumbered by a unipolar nature 16−18 . The development of n-type OSCs is still lagging behind that of their p-type counterparts owing to their less effective packing structure and energetics of electron injection 19 . Similarly, p-type MOSs rarely exhibit high performance owing to difficulties in hole formation and the unfavourable hole-transport path due to the presence of highly 3 occupied localised oxygen 2p orbitals 20 . Such a lack of suitable material systems restricts the implementation of solution-processed semiconductors in advanced complementary ICs composed of p-and n-channel TFTs on the same substrate. Therefore, most of the reported solution-processed ICs are used for ambipolar operation with single p-type OSCs or n-type MOSs 21−25 or complementary circuits with an unsatisfactory performance 26−31 . Hybridisation is one way to overcome the limitations faced by a single material and this approach has been used to build complementary circuits 16 18,32,33 . This is probably due to the different and complex chemical characteristics of the materials being integrated into the same circuit. For instance, OSCs are self-assembled in solid states via weak van der Waals forces, whereas MOSs are covalently linked, which leads to inconsistencies between their processing parameters, such as temperature, heat and chemical resistance, and adaptability to lithographic processes. In addition, fine patterning is mandatory in both semiconductors and electrodes to avoid crosstalk and realise high-speed operations. Therefore, the scalable fabrication of highperformance OSC-MOS hybrid complementary ICs with a high degree of integration of their finely patterned TFTs on the same substrate is challenging. Although a few solutionprocessed hybrid complementary ICs have been demonstrated with photolithographic processes, their performances, such as mobility and the on-off switching rate of TFTs, were compromised because of the low mobilities of the macromolecular OSCs used and the chemical degradation of MOSs 34,35 . The fabrication of advanced flexible devices introduces additional difficulties due to the instability of conventional flexible substrates, such as their poor heat and chemical resistance 36−38 . 4 In this study, we demonstrate complementary ICs composed of solution-processed TFTs   based on single crystals of a small-molecule OSC, 3,11-dinonylldinaphto[2,3-d:2',3'd']benzo [1,2-b:4,5-b']dithiophene (C9-DNBDT-NW), and amorphous indium zinc oxide (IZO) as the p-and n-channel materials, respectively. These materials were selected because of their high carrier mobility, uniformity, and scalability 39,40 . A technology was developed for scaling up these systems for high-speed operations with a special focus on damage-free patterning for both OSC-and MOS-based TFTs and the process durability of MOS-based TFTs for further integration. In the following sections, we shall describe these flexible hybrid complementary inverters, which exhibit desirable switching properties, excellent long-term stability, and good flexibility. Five-stage complementary ring oscillators were used to discuss the stage propagation delay of the fabricated hybrid inverters. We achieved a propagation delay of 1.3 µs with an operation voltage of 10 V, which indicates that this facile method combining the advantages of p-type OSC and n-type MOS can potentially meet future IoT demands.

Integrated process
The hybrid complementary inverter on a polyimide (PI) substrate with C9-DNBDT-NW single crystals as the p-channel material and amorphous IZO as the n-channel material is schematically illustrated in Figure 1. Both the p-and n-channel TFTs have bottom-gate topcontact structures. As illustrated in Figure S1, for the IZO-based n-channel TFT, gate electrodes were fabricated by photolithography and a lift-off process. Meanwhile, the AlOx gate dielectric layer was formed by atomic layer deposition (ALD). The IZO layer was deposited by spin coating and patterned via photolithography and wet-etching. To reduce the number of photolithography steps, source/drain (S/D) electrodes of n-channel TFTs and gate 5 electrodes of p-channel TFTs were fabricated simultaneously. Polymethylmethacrylate (PMMA)/parylene acts as a gate dielectric for p-channel TFTs and doubles as a passivation layer for n-channel TFTs to protect the back-channel of IZO-based TFTs against potential damage during subsequent integration processes. C9-DNBDT-NW was formed using a continuous edge casting method 8,41 and then transferred to the top of the PMMA/parylene dielectric layer 42 .  (Figure S3), which was key to the successful fabrication of the C9-DNBDT-NW single crystal layer. OSC patterns and Au S/D electrodes were formed via a two-step patterning process, in which photosensitive dielectric materials (PDMs, a dry-film photoresist)/PMMA double sacrificial layers were employed for a damage-free patterning of OSC-based TFTs. As shown in Figure S4, PDM 6 (the top layer) enables the formation of the OSC and S/D patterns while PMMA facilitated the stripping of the resist with acetonitrile, thus causing little damage to the OSC. The dry-film photoresist PDM was laminated on the substrate and patterned by photolithography 43,44 , while the PMMA layer was deposited via spin coating and etched with O2 plasma. Furthermore, the PDM dry film contributed to the damage-free fabrication of OSC-based TFTs as the solvent content in the PDM dry film was less than 2 wt.% and the PDM patterning process is based on the polymerization of double bonds rather than the generation of photoacids. Therefore, the potential damage induced by solvents or acids in conventional photolithography could be eliminated effectively. The contact resistance (Rc) of C9-DNBDT-NW-based TFTs fabricated by this technology was studied using the transfer-line method, as described in the Supporting Information (Section S1). The intrinsic mobility (µint) of C9-DNBDT-NW TFTs was ~10 cm 2 V −1 s −1 and the normalised contact resistance (RcW) was ~230 Ω cm ( Figure S5), which is a low value for OSCs without extra doping 6 ; this implies a high effectiveness of carrier injection in the fabricated C9-DNBDT-NW-based TFTs.

Electrical performance of the hybrid inverters
The electrical properties of the p-and n-channel TFTs were evaluated. A micrograph of a complementary inverter with channel width/channel length (W/L) of 200 µm/9 µm for the C9-DNBDT-NW p-channel and 200 µm/13 µm for the IZO n-channel is shown in the inset of   Due to contact resistance, the effective mobility (µeff) is lower than µint, especially in shortchannel devices, as shown in Equation (1), where Ci is the gate capacitance per unit area, VG represents gate voltage, and Vth is the threshold voltage. The µeff of the C9-DNBDT-NW-based TFT was estimated to be ~5.9 cm 2 V −1 s −1 , which is similar to the experimental value. In the case of the IZO-based TFT, RC was estimated to be 29 Ω cm and the effective resistance measured after the integration process is at similar to that of IZO TFTs before integration 40 (Figure 3(d)). Although the static current at a high Vin was several orders higher than that at a low Vin, the static power consumption was still less than 0.76 µW at VDD = 7 V. Because the current (ID = 3 × 10 −7 A) of the p-channel TFT at VG = 0 V or Vin = 7 V was 5 orders of magnitude higher than that (ID = 1 × 10 −12 A) of the n-channel TFT at VG = 0 V or Vin = 0 V ( Figure S6) higher static currents were observed at high Vin values. Our future work will aim to control Von for p-channel TFTs to further lower the static power consumption of hybrid complementary inverters. It is particularly important to note that the hybrid complementary inverter exhibited a decent performance even after exposure to the ambient atmosphere (air) for 5 months (Figure 3(f)).
The transfer characteristics of p-and n-channel TFTs before and after exposure to air for 5 months were recorded ( Figure S7). In the case of both C9-DNBDT-NW-and IZO-based TFTs, the off current increased slightly. This may be attributed to a self-healing effect in which the number of carrier traps decreased slightly over time 6,46 . One possible reason for the slight Von shift of the IZO TFT may be the diffusion of environmental molecules such as oxygen and water because the current passivation layer, PMMA/parylene, could not isolate the device completely. The passivation technique is being studied to further stabilise these devices.

Flexibility of the hybrid inverters
The PI substrate was delaminated from the glass support using a laser lift-off (LLO) method to evaluate the flexibility of the as-fabricated inverters. Figure 4(a) shows a photograph of the ICs on a free-standing PI film and Figure 4(b) compares the VTCs obtained before and after delamination at VDD = 4, 6, 8, and 10 V. The overlap between the VTCs at each VDD indicated that the LLO process did not adversely affect the electrical performance of the inverter.

TFTs exhibited decent transfer characteristics under the action of a bending stress. The slight
Von shift is probably due to system error during measurement 40,47 .The bending stress applied on semiconductors depends not only on the bending radii but also device structure and substrate thickness. The corresponding surface strain (ε) can be calculated using the following where R is the bending radius and hs is substrate thickness. In addition, when a substrate is bent, there is always a layer with zero bending stress and while the inner surface suffers compression stress, the outer surface suffers tensile stress. In this study, compared with the thickness of substrate PI (~10 µm), the total thickness of the other layers (<500 nm) was negligible; hence, the TFTs experienced a tensile force perpendicular to the channels. In other words, the tensile force was applied in the c-axis direction, i.e., the preferred carrier-transport direction in the herringbone packing structure of the C9-DNBDT-NW single crystal, which might decrease carrier mobility 48 . Meanwhile, amorphous IZO was isotopically stressed.
Using Equation (2), the maximum tensile stress was estimated to be 0.08% with a bending radius of 6 mm, at which the decrease in mobility was small (1%) 48

Performance of hybrid ring oscillators
Unlike direct calculation by propagation delay, ring oscillators provide a simple and effective way to evaluate the maximum switching speed of larger logic gates. In a ring oscillator, each 14 inverter delays the input signal for a specific time, which is defined as the stage propagation delay (tp). To simplify, we assume that all inverters have the same property and the same delay time. The delay time at the output can hence be written as where n is the stage number and T is the period of the ring oscillator. By measuring the operation frequency of the ring oscillator (fROSC), tp can be calculated as shown in Equation The VTC of a single inverter with a supply voltage of 10 V (Figure 6(b)) suggests that even those inverters with short channel lengths exhibit a full rail-to-rail swing, symmetric transition of VM ~ 5 V for both forward and backward voltage sweep, and a high noise margin with an 15 NMH of 3.2 V and NML of 2.9 V. The output signal at a VDD of 10 V is shown in Figure 6(c).
In this case, fROSC = 77 kHz and the propagation delay per stage was estimated to be 1.3 µs.

We compared several complementary ring oscillators based on solution-processed OSCs or
MOSs with respect to propagation delay in terms of scalable fabrication and flexible circuits.
As there only a few studies on flexible substrates, ring oscillators fabricated on rigid substrates were also added to the list (Table 1). Because the frequency of a ring oscillator is approximately proportional to VDD 50 , different devices were compared by converting VDD to 10 V and the corresponding propagation delay after conversion was defined as tp(10V).
Notably, the hybrid ring oscillator described in this study exhibited the fastest operation speed when compared to all other compared oscillators. substrates. We believe that the operation speed can be further improved by optimising the photolithography and semiconductor-deposition conditions.

Discussion
We demonstrated scalable hybrid complementary ICs on flexible substrates using solutionprocessed semiconductors. Using high-performance semiconductor materials, viz. p-type C9-DNBDT-NW single crystals and n-type amorphous IZO, and carefully designed integration processes, we could fabricate hybrid inverters with excellent electrical characteristics, including an almost rail-to-rail swing, negligible hysteresis, voltage gain as high as 38 V/V, large noise margin, and superior long-term stability. A five-stage ring oscillator operating at 77 kHz with a supply voltage of 10 V proved the potential of this hybrid technology for highspeed operations and highly complex ICs. Furthermore, the hybrid complementary inverters worked well even under bending conditions at radii as high as 6 mm. To further improve the operation speed of these inverters, it is required to further improve their carrier mobility and reduce their dimensions. We are currently working on optimising the fabrication conditions to achieve finer patterns and these results will be reported in near future. In addition, appropriate passivation is being studied to further improve the stability of this hybrid system. Finally, because the proposed technology enables the direct printing of advanced complementary circuits on flexible substrates, we envision that it will contribute significantly to IoT applications.

Substrate preparation
All the devices used in this study were fabricated on PI substrates. film was attached to a glass support during fabrication and delaminated using an LLO technique to achieve free-standing films for flexibility evaluation.

Fabrication of n-channel TFTs based on IZO
IZO films were fabricated using a sol-gel method. Initially, In and Zn precursor solutions (0.1 M) were prepared by adding In(NO3)3·xH2O (Aldrich) and Zn(NO3)2·xH2O (Aldrich) to 2methoxyethanol, respectively, and stirring at room temperature in the air for more than 6 h.
The IZO precursor was then prepared by mixing the In and Zn precursors at an In/Zn ratio of 3/2 and stirring under the conditions described above.
Both n-and p-channel TFTs exhibit a bottom-gate top-contact structure, as shown in Figure   S1. Gate patterns of IZO-based TFTs were formed by photolithography with a photoresist (TLOR, Tokyo Ohka Kogyo Co., Ltd.). Cr/Au/Cr (5/25/5 nm) was deposited via thermal evaporation, followed by a lift-off process. An AlOx gate dielectric layer was formed by ALD. Before IZO deposition, the substrate was treated with a UV ozone cleaner (Filgen, Inc., UV253H) for 10 min to remove any organic residues and improve its wettability. The IZO precursor was then spin-coated on the substrate at 500 rpm for 5 s and 5000 rpm for 30 s,

Fabrication of p-channel TFTs based on C 9 -DNBDT-NW
After the fabrication of n-channel TFTs, a PMMA/parylene bilayer was fabricated to act as a passivation layer for n-channel TFTs and it doubled as a gate dielectric for p-channel TFTs.
The More details on the printing and OSC transfer methods can be found in our previous reports 8, 41,42 .
Fine patterns of OSC and Au S/D electrodes were achieved by a two-step patterning process based on a dry film resist with a thickness of 5 µm (PDM, Taiyo Ink Mfg. Co., Ltd.) 43,44 . This process is illustrated schematically in Figure S10. A PMMA layer (Mw = 120,000, 5 wt.% in butyl acetate) was formed by spin coating at 500 rpm for 5 s and 1000 rpm for 30 s, followed by baking at 80 °C for 10 min before being laminated with a PDM dry film. The PDM layer 20 was patterned by photolithography and PMMA was patterned using O2 plasma with patterned PDM as a mask. After etching the OSC or S/D electrodes, PMMA and PDM were stripped together with acetonitrile. For OSC patterning, Au (30 nm) was deposited via thermal evaporation on the entire surface and it acted as a protection layer as well as S/D electrodes.
Subsequently, a two-step photolithography process was conducted. Au was etched using an AURUM S-50790 (Kanto Chemical Co. Inc.) instrument and the OSC layer was etched using O2 plasma. Subsequently, a solid-state laser (Delphi Laser, Inducer-6001-P, 355 nm) was used to create holes in the gate dielectrics for bottom electrodes. Next, Au (60 nm) was deposited by thermal evaporation and patterned by two-step photolithography to form S/D electrodes and conduction terminals for the bottom electrodes. Finally, the substrate was annealed at 110 °C for 1 h to remove the solvent used during fabrication.

Device characterisation
The electrical properties of the fabricated hybrid inverters were measured under ambient and dark conditions. The static properties of the TFTs and the VTCs of the inverters were measured using a semiconductor parameter analyser (Keithley, 4200-SCS). The output signals of the ring oscillators were recorded using an oscilloscope (Tektronix, MDO3014).
Micrographs of the complementary inverter and ring oscillator were acquired using an optical microscope. An FIB-SEM (JEOL, JIB-4700F) was used to observe the edge conditions of the gate electrodes in p-channel TFTs.
Carrier mobility (µ) and Vth were determined by measuring the dependence of drain current (ID) on VG and fitting with the following equations.
In the linear region,