Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (Ron) along with increased breakdown voltage (Vbr) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (ID) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (fmax) and cut-off frequency (ft). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak gm, ID, fmax and ft with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.


Introduction
The low voltage analog and digital circuits are integrated with power devices results in the development of smart power integrated circuits (PICs). The smart PICs are used in various applications such as, automotive electronics, industrial control circuits, personal communication systems programmable logic circuits, portable power management systems, etc. Nowadays, the energy resources are limited so that the requirement of such PICs which consumes less energy, and fulfilled the manufacturing and economic constraints with efficient, rugged and reliable features. However, to fulfill the demand of energy efficiency, there is a requirement of effective power MOSFETs which delivers the enormous amount of power without consuming a substantial part of it [1][2][3]. Among several possible options, a discrete power device with trench gate structure is more effective suitable for low voltage analog/digital and RF applications due to lower value of on-state resistance as compared to any other architecture with same specifications [4,5].
A trench gate MOSFET is having a unique feature it conducts the current vertically from one surface to another surface in order to attain a high drive capability which is considerable for making a complete chip [6][7][8][9] [10,11]. Presently, silicon-on-insulator (SOI) technology is dominantly used for making the RF power integrated circuits (PICs) due to its mature fabrication process with well-studied native oxide in order to get advantage of better reliability, improved performance, low power consumption, and reduction in size, weight and cost [12][13][14][15]. As the silicon (Si) based power electronic devices are approaching their physical limits, new materials are needed to overcome the challenges faced by the mature Si technology [16]. The III-V group compound semiconductors are emerging as the promising channel material for LDMOS due to their outstanding transport properties. High electron mobility material InGaAs is attractive as alternative channel material than Si which can replace silicon in power devices [2,16,17]. A parameter comparison of the Si and InGaAs is given in Table 1. Therefore, the motive of this paper is to propose the integration of low voltage MOSFET and high power dual-gate MOSFET on emerging InGaAs semiconductor material using trench technology for better performance of the device. Figure 1 illustrates the integration of junction isolated low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV-DG MOSFET). Both the devices are implemented in n-type III-V semiconductor material (i.e. In 0.53 Ga 0.47 As) using p-type substrate (InP). The proposed junction isolated HV DG MOSFET and LV MOSFET is isolated by using p + trench with − 1 V reverse bias. In both low voltage as well as high voltage dual-gate MOSFETs, n-channels are formed in p-region vertically and drain electrode is separately connected with source/p-region by oxide (Al 2 O 3 ) filled trenches. The I D flows through all the channels simultaneously from drain electrode to source electrode.

Device Structure
The HV DG MOSFET consists of stepped-gate structure with unequal oxide thickness t ox2 = 0.1 μm, t ox1 =

Results and Discussion
The 2-D simulations of proposed structure as junction isolated LV MOSFET and HV DG MOSFET are carried out by choosing CVT Lombardi and Fermi-Dirac models with the help of ATLAS device simulator [18]. The simulations accuracy is determined by comparing the results obtained with existing literature of a MOSFET [19].    Fig. 6. The device structure consists of high value of g m represents their suitability for RF amplifier applications.
The frequency/microwave characteristics (f max and f t ) of the HV DG MOSFET are shown in Fig. 7. In the proposed HV DG MOSFET the value of f t obtained is 3.8 GHz, while f max is found to be 9.75 GHz.
For the LV MOSFET, the frequency characteristics are shown in Fig. 8. The value of ft of the low voltage MOSFET is found to be 41 GHz at 0 dB current gain. This is due to the effect of enhanced g m of the device. The f max value of the proposed LV MOSFET is 132 GHz.
Moreover, at V GS of 0 V, Fig. 9 shows the breakdown characteristics of the HV DG MOSFET. In this study, the V br is extracted at which I D exceeds 10 − 9 mA/µm. This characteristic exhibits a high V br of 62 V. This is due to the reduction in the peak value of electric field in the proposed structure.
The dependence of R on,sp and V br on N d for the HV DG MOSFET is shown in Fig. 10. Figure 10 depicted the HV DG MOSFET gives maximum V br (i.e. 62 V) for N d = 1.5 × 10 16 cm − 3 due to RESURF effect (i.e. reduces the peak electric field inside the device). As increases the value of N d beyond 1.5 × 10 16 cm − 3 , the V br decreases due to increases the field lines inside drift region. From Fig. 11, as the value of N d increases the R on,sp decreases due to enhancement in drift current. Table 2 shows a performance evaluation of various MOSFETs.

Conclusions
In this work, a new integration technique is proposed based on junction isolation of LV MOSFET and HV DG MOSFET for making smart IC on III-V semiconductor material i.e. InGaAs. The architecture of proposed device is based on trench gates form multiple channels conduction in the p-body to obtained higher output current and lower on-state resistance. The enhancement in I D due to more control of gate also enhances the peak transconductance which improves the microwave characteristics of the proposed structure. In the HV DG MOSFET the obtained value of I D =0.086 mA/µm, BV = 62 V, R on −sp =51 mΩ-mm 2 , g m = 0.102 mS/µm, f t = 3.8 GHz, and f max = 9.75 GHz. For LV MOSFET the observed value of I D =0.50 mA/µm, g m = 0.998 mS/µm, f t = 41 GHz, f max = 132 GHz with SS = 76 mV/dec, and DIBL = 115 mV/V. With the help of 2-D analysis in the device simulator, the performance of LV MOSFET and HV DG MOSFET are evaluated and observed that both the devices exhibits better static and dynamic behavior. The proposed integration concept with trench gate technology can be used for making power ICs, high frequency communication systems also used in analog, digital and mixed signal applications.   -91  51  -----LV IC  --------PICs [11] HV DT MOS  -92  36  -----LV IC  --------