Retinal blood vessel extraction and enhancement is an intensively researched topic as it is an irreplaceable component in ocular disease screening systems. The matched filter method has been proven superior for blood vessel extraction and enhancement compared to edge detection algorithms in that it can extract blood vessel along its path and retain blood vessel depth information even when blood vessels are prone to be indistinguishable from the background. This work has implemented matched filter method with Verilog Hardware Description Language, taking advantage of the highly customizable feature and parallel computation capabilities by FPGA. The first proposed design method employs an innovative resource-efficient technique based on matched filter technique. It can be applied to situations where budget and physical resource is limited. The second design method is a time-efficient processing technique that provides further improvement in that it eliminates the gap incurred in convolution between two rows of data. As has been verified via simulation, it can offer a continuous output with about 9% increase in processing speed for conducted simulation compared to the first proposed technique.