Analog/RF Performance Analysis of  Heterojunction Tunnel FET with Temperatute


 In this paper, the analog/RF analysis of SiGe source-based heterojunction Tunnel FET is reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source capacitance (CGS), gate-drain capacitance (CGD), cut-off frequency (fT) and gain-bandwidth product (GBP) are studied. DC, as well as AC simulations, have been performed on the proposed device. We have achieved an ON current of 0.537 µA/µm and OFF current of 13 fA/µm, thus achieving ION/IOFF ratio as 3.72×1010. We have also performed temperature analysis of the analog/RF parameters. We have also investigated the device for the temperature analysis concerning the drain current and the capacitance calculations. We have observed that the OFF currents are strongly dependent on the temperature. All the simulations have been performed on Visual TCAD (licensed version 1.9.2-3).


I. INTRODUCTION
With continuous scaling of transistors in CMOS technology, it has been made possible to attain high drive currents with a high-frequency performance of conventional MOSFET. However, due to the shrinking of the device with scaling, short channel effects and leakage currents 1 put a constraint on its use [1][2][3][4][5]. Thus, extensive research has been made to develop novel devices that can overcome the scaling limitation in a MOSFET. Moreover, due to the thermionic emission mechanism, the subthreshold swing of a MOSFET cannot achieve less than 60 mV/decade at room temperature. In the recent past, Tunnel Field Effect Transistors (TFETs) have been proposed as a substitute for the conventional MOSFET structures [6][7][8][9]. The physics involved in the current transport mechanism of a TFET is based on the band to band tunneling (BTBT) rather than a thermal injection of electrons as in case of a MOSFET. So, it is possible to achieve steeper subthreshold swing and a high ION/IOFFratio, while operating at a supply voltage lesser than 1 Volt. Hence, TFETs are seen as promising devices for low power applications such as smartphones, laptops, etc.
Despite the given advantages, it has been seen that TFETs based on silicon material suffers from low ON current and high subthreshold swing (SS) thus rendering it unsuitable for practical use. Poor characteristics of a conventional TFET structure has been attributed to the larger energy band gap of the silicon material. Researchers have presented various performance booster techniques such as dual gates, gate all around, high-k dielectric material, use of low energy band gap, etc. to boost the ON current and to achieve sub 60 mV/decade subthreshold swing [10][11][12][13][14][15] However, seldom papers have been reported regarding the analog/RF performance of TFET structure [16][17][18][19][20][21].
In this paper, we have analyzed SiGe source-based heterojunction TFET device on the basis of the following analog/RF parameters: transconductance (gm), device efficiency (gm/ID), gate source capacitance (CGS), gate drain capacitance (CGD), cut-off frequency (fT) and gain-bandwidth product (GBP). Further, we have analyzed the device for the temperature variations from 200 Kelvin to 400 Kelvin. *Corresponding author sanjeetksinha@gmail.com .

II. DEVICE DETAILS AND SIMULATION
The schematic structure of the device is given in Fig. 1. The structure uses !"# # as the source material, where represents the amount of the molar fraction of Germanium added to the compound SiGe. Germanium has a smaller energy band-gap compared to the silicon. Thus, it helps in boosting the ON current of a device [22][23][24][25][26].However, the sole used of a Germanium also increases the OFF current at the same time, which is not desirable. While as, the leakage current in silicon is around 1000 time lesser than that of a Germanium. Thus, to combine excellent features of both materials, SiGe has been used in the source region. The values of molar fraction, work function and spacer lengths have been optimized for better ION/IOFF and SS [27][28][29]. The values of the device parameters have been provided in Table 1. Silicon on Insulator (SOI) has been utilized to suppress short channel effects [30][31][32].
All the simulations have been performed on Visual TCAD. Kane's local band to band tunneling model has been enabled while running the simulation. Lombardi Model has also been used in order to take high field mobility into consideration. The electron-hole tunneling current is calculated by WKB integral.  Fig. 2 represents the energy band diagram of a device in OFF and the ON state. When gate-source voltage VGS= 0 Volt, the valence band of the source lies above the conduction band of the channel, hence band to band tunneling is inhibited.

Fig.2. Energy Band Diagram for the proposed device
When the gate-source voltage is increased gradually, the electrical field around the gate-source region increases, thus enabling the band to band tunneling. This results in an increase in the drain current. Kane's model gives the rate of the tunneling as: Here A.BTBT and B.BTBT are empirical fitting parameters, E is the electrical field and ) is the energy band-gap. From (1), it is clear that the tunneling rate increases with an increase in the electrical field. A Fig. 3 shows the variation of an electrical field with the application of gate-source voltage. As the gate voltage is increased from VGS= 0 V to VGS= 1.5 V, the electrical field increases. Fig. 4 shows the surface potential of the device. It is clear from the figure that the potential is low at the source junction. As we proceed toward the drain junction, the surface potential increases. Moreover, the graph indicates that as the gate-source voltage is increased, the surface potential increases. Fig. 5 shows the drain current transfer characteristics of the device. The device shows an excellent subthreshold swing of 28.57 mV/decade and maintains ION/IOFF ratio of 3.72×10 10 . The threshold voltage of a device has been found out by using DIBL is basically a short channel effect phenomenon in short channel devices, where the larger drain voltage widens the depletion region hence lowering the potential barrier at the source. The value of DIBL obtained in our device is 3.636 mV. Thus, it can be said that the short channel effect of DIBL is greatly restrained in our proposed design. The equation used for DIBL calculation is given as: Where V + $%& andV + !"# are the supply voltages at the saturation and the linear mode. V * !"# andV * $%& are the threshold voltages obtained using the constant current method at the linear and the saturation mode, respectively.The variations with temperature from a range of 200 K to 400 K are performed on the drain current. It can be observed from the Fig.6 and Fig. 7 that the ON current is not affected with temperature variations. It is because the band to band tunneling is weakly dependent on temperature. However, it can be seen that the OFF current strongly varies with temperature.Transconductance plays an important role in terms of analog performance. It represents the change in the output drain current with respect to the variations in a gate voltage. It is clear from Fig. 8 that at the lower voltages, the transconductance increases with the increase of a gate voltage. However, at the higher voltages, it is observed that , decreases due to the mobility degradation.
Mathematically, transconductance is defined as: Transconductance to output drain current ( , 01 ⁄ ) or device efficiency is another useful parameter for analog/RF applications- Fig. 9 plots device efficiency of the device against the drain current for the device. The improvements in the device efficiency are attributed to the increase in the transconductance of the device. , 01 ⁄ ratio obtained shows that the device is capable of providing high energy efficiency at lower gate voltages, which is an essential parameter for low power analog/RF applications (Chander et  Hence, from Eq. (5), the theoretical limit of , 01 ⁄ is about 38.3 V -1 . However, since TFET based structure has been employed in this paper with an excellent subthreshold swing of 28.57 mV/decade, thus increasing the device efficiency tremendously. From equation (5), by substituting the value of the average subthreshold swing, the value of device efficiency , 01 ⁄ comes out to be 80.59 V -1 , which is more than twice the value achievable with the MOSFET structure. Thus, larger values of , 01 ⁄ than that of a MOSFET is achievable with TFET structure Also, there is no noted difference with the variations in the drain voltage.  Fig. 10 shows the variation of the gate-drain capacitance as a function of the gate voltage. It is clear from the figure that 20 increases with the increase of 21 due to the development of the inversion layer from the drain towards the source region. Fig. 11 shows gate-source capacitance variations with gate voltage. 21 depends on the electron concentration of the source side. It can be observed that 21 decreases with an increase in gate voltage VGS. It is because the coupling between the gate and the source decreases because of the increased inversion layer. 21 values obtained are lesser than that of 20 . The total gate capacitance can be calculated by summing up gate-source (CGS) and gate-drain capacitances ( 20 ).nThe values of the capacitance obtained lies in the range of 0.1 to 1 femto Farads. Furthermore, we have also performed a temperature analysis of the capacitance parameters. It can be observed from Fig. 12 and Fig. 13 that both the capacitances remain weakly dependent on the temperature at lower voltages, and shows a slight increase in the values at higher is another important parameter of interest, that represents the frequency range up to which a device can be amplified. It is defined as the frequency at which gain becomes unity. For better RF applications, 3 must be as high as possible. The value of cut-off frequency is given by: Thus, an increase in parasitic capacitances would decrease the cut-off frequency. It can also be deduced from the given equation with an increase in , , the cut-off frequency increases as well. This is mainly attributed to the injection of charges from the source and the increase in the band to band tunneling. The higher mobility for a device can be achieved if a drain voltage is increased. This, in turn, improves the transconductance of the device. Similarly, the gate capacitance 22 also reduces with an increase in drainsource voltage. Thus, the increase of , and the decrease of 22 leads to the higher cut-off frequency for the device.
The values obtained can be compared with the work of others in Table II.

IV. CONCLUSION
In this paper, the analog performance of has been studied and demonstrated. The proposed device shows enhanced improvements in the parameters of the drive current, transconductance, device efficiency , 0 ⁄ , gate-drain capacitance (CGD), gate-source capacitance (CGS), cut-off frequency (fT), and gain-bandwidth product (GBP). The maximum ION and IOFF values obtained for the device are 0.537 µA/µm and 13 fA/µm respectively, thus achieving ION/IOFF ratio of around 3.72×10 10 . The maximum transconductance value for the device is 0.68 milli Siemens/µm at the drain-source voltage, VDS= 1V. The best device efficiency , 01 ⁄ being obtained is 80.59 V -1 . The maximum cut-off frequency obtained for the device is around 446 GHz at the drain-source voltage, VDS= 1V. For studying the high-frequency response, Miller capacitances (CGSand CGD) have been studied, and it was found that the gate-drain capacitance (CGD) is the dominant factor in the Miller capacitance. The results obtained have also been compared to the existing TFET structures, and it is evident that the device shows superior performance. Therefore, it can be concluded that the proposed device can be useful for many analog and digital low power applications.