Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

— This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and RF stability performance metrics. Furthermore, the dc and analog figure of merits in the presence polarized interface trap charge densities has been analyzed at sub-ambient temperatures. The steep ON-OFF switching and the sub-threshold slope profile shows heavy reliance on temperature variations and confirm that the transistor electrostatics improve at lower temperatures. The study reveals the compatibility of the device to perform at cryogenic temperatures and can be integrated with CMOS technology for quantum computations.


I. INTRODUCTION
Device miniaturization in Complementary-Metal Oxide Semiconductor (CMOS) solid-state technologies in terms of gate length has been the vital concern for the researchers to abide Moore's law [1][2].Bottle-necks such as short-channeleffects (SCEs), OFF-state current efflux, static-power dissipation as well as source and drain junctions are major concerns that needs to be addressed for nano-scaled devices.Colinge et al proposed the first junction-less field-effect transistor (JL-FET) in the late 2000s [3], providing simpler fabrication process flow due to lack of source/channel/drain doping density variations thereby mitigating device draininduced barrier lowering (DIBL).Therefore, to efficiently manifest the FET electrostatics, we have inherited a dual gate junction-less MOSFET in this work.Additionally, a high-k (HfO2) gate dielectric stack with silicon dioxide (SiO2) as the low-k dielectric geometry has been implemented to minimize OFF-state current efflux (IOFF) for efficient power scaling and carrier drift along the channel [4].
Lately, the emergence of quantum computational systems with accelerated performance over the traditional systems has become a focal point for researchers world-wide to improve hybrid-computation [5][6].The CMOS-integrated quantum-bit (CI-qubit) systems are realized at deep cryogenic temperatures (DCT<10K) [7], that provides miniaturized quantum computational systems (processors) along with efficient manipulation of thermal/noise-budget, qubits readout, error recovery [8][9][10].Performance of Metal-Oxide-Semiconductors (MOS) technologies have been under supervision at liquid nitrogen temperatures (LNT=77K), over the past four decades finding real-time applications like space technologies [11].However, with the increase in computational complexity and bit stream encoding, it is valid to study the reliability of MOS technologies at sub-LNT.Fine trade-off between the scaled-supply voltage of the CMOSintegrated quantum computational systems and its performance in terms of timing boundaries of CI-qubit is reported in [12][13].CMOS characteristics like drive current (ION), density of states, sub-threshold slope (SS), ON-OFF switching, energy band diagram profile, transconductance, voltage transfer characteristics (VTC), noise margin gets heavily influenced by DCT [14].Thus, a precise currentvoltage simulation model to validate DCT is the need of the hour.Transistor performance is amplified at lower temperatures nodes along with impurity freezing and enhanced carrier mobility.It is known that IOFF and SS are functions of temperature, therefore, the ON-OFF ratio (ION/IOFF) and SS profiles gets highly driven by DCT providing a steep characterization [15].However, SS at DCT has no experimental evidence.So far, a saturation SS of 10 mV/dec at T=46K has been reported by [16].
In this work, a high-k stacked Dual Gate Junction-less MOSFET in DCT (DCT-DG-JL-MOSFET) has been designed to illustrate the transistor electrostatics at DCT considering dc, analog and Radio Frequency (RF) performance metrics like transconductance (gm), parasitic capacitances, transconductance generation factor (gm/ION), cut-off frequency, gain bandwidth product, Stern stability factor (Kstable) and unilateral power gain.Furthermore, to extent the transistor reliability analysis, the role of interface trap charge densities (ηitc) has been investigated for transfer characteristics and gm profiles at DCT.  1 School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, India.
overall transistor length of 90 nm.An N-type device is implemented for analyzing its behavior at cryogenic temperatures.A uniform doping density profile of 10 18 /cm 3 is maintained along the channel length.To mitigate the OFF current efflux, hafnium dioxide (HfO2) and silicon dioxide (SiO2) are considered as high-k/ low-k stacked gate dielectrics with thickness, T25 =2 nm and T3.9=1 nm respectively.Silicon thickness (TSi) of 10 nm is considered along the channel length.The gate consists of 4.8 eV work-function metal.SILVACO ATLAS TCAD simulator is utilized for the simulation of DCT-DG-JL-MOSFET [17].The temperature variations have been analyzed by activating a self-heating simulator called GIGA from the ATLAS instructions.'LAT.TEMP' and 'HEAT.FULL' models are included to facilitate lattice-heating and thermal activation of source/sinks respectively.Thermocontact commands are initiated to solve lattice-heating equations.Carrier drift is conducted by using a Drift-diffusion transport model within the 10 nm thick lattice.Shockley-Read-Hall (SRH) models have been included to address carrier recombination inside the lattice.High doping densities minimizes the band-gap therefore a Band-gap narrowing (BGN) model is activated.The temperature-relied mobility is determined using the 'ANALYTIC' model while the parallel electric field behavior is controlled by the 'FLDMOB' model.Furthermore, the validity of the DCT-DG-JL-MOSFET simulation data has been verified with the experimental results of a 20 nm gate length Junction-less transistor by Colinge et al [18] in terms of transistor I-V characteristics shown in Fig. 2.

A. Impact of DCT on the DC metrics
This article lays out an extensive analysis of the reliability of DCT-DG-JL-MOSFET under wide-ranging temperatures, 400 K to 50 K (DCT).Carrier-freezing phenomenon in FETs needs to be taken into account at cryogenic temperatures that firstly amplifies carrier mobility across the silicon lattice due to less-pronounced scattering and secondly affects the carriertransport which might result in thermal-noise [19].Fig. 3 Fig.6 shows the SS profile of the DCT-DG-JL-MOSFET at sub-LNT.The reliance of SS on temperature variations can is shown in equation ( 1) [19].SS improves by 85% as temperature falls from 400 K to 50 K.At 50 K, a saturated SS=14mV/dec is reported in this article therefore making the device suitable for qubits generation at scaled drain to source voltage values (VDS).
Where, e, γ and KBoltzmann denotes the electronic charge, SS factor and Boltzmann constant respectively.

B. Impact of DCT on the Analog metrics
The change in the transconductance (gm) as a function of temperatures with varied gate to source bias (VGS) at low VDS value is depicted in Fig. 7.When the device is ON, the rise in current due to increased carrier mobilities results in increased gm.However, gm degrades with increment in VGS indicating reduced carrier mobilities due to increased scattering in the lattice mitigating current.This observable gm oscillation in junction-less devices can accounted for quantum-mechanical conduct [20][21].The impurity-freezing at DCT results in enhanced carrier mobilities [22] that results in a peak gm = 3.9 mS at 50 K.Fig. 8 presents the transconductance generation factor profile formulated by gm/ION at DCT.The impact of gm/ION on analog/RF circuitry can be understood by its inverse relation with device SS that denotes circuit power-drain [20].Therefore, greater the gm/ION less will be the device which means lesser circuit power-drain.

C. Impact of DCT on RF metrics
The terminal parasitic capacitances (TPC) as a result of small-signal analysis in DCT-DG-JL-MOSFET during device freezing is shown in Fig. 9.The behavior of gate-tosource capacitances (Cgs), gate-to-drain capacitances (Cgd) and the total gate capacitances (Cgg) are observed in Fig. 9(a), (b), and (c) respectively.It can be observed that the TPCs rise as the device turns ON and more so at 50 K [23][24].Another vital radio-frequency (RF) metric is the FET cut-off frequency or transit frequency (Ftransit) that is determined by equation ( 2) at unit small signal current-gain [25][26].Since Ftransit relies on the device transconductance and TPCs, it understandably increases due to greater transconductance values and lower TPCs (10 -15 orders) as reported in Fig. 7 and Fig. 9 respectively.Therefore, a peak Ftransit of 245 GHz is reported at 50 K in Fig. 10.The cooling of DCT-DG-JL-MOSFET to cryogenic temperatures alters its unilateralpower-gain (Ugain) profile shown in Fig. 11.The peak-oscillation frequency can be determined from the frequency where Ugain=0 dB [27].Subsequently, the relation between the transistor gain and the loss-less amplifiable frequency range (bandwidth) is established by the gainbandwidth-product (GBW) shown in equation ( 3) and Fig. 12.
It is evident that GBW is a function of gm as well as Cgd and  increments at DCT.A peak GBW = 520 GHz is reported at 50 K.The radio-frequency (RF) stability of DCT-DG-JL-MOSFET based analog-circuitry at DCT is shown in Fig. 13 by the Stern Stability factor (Kstable) profile.Kstable values for varied temperatures are drawn from the small-signal yparameters to analyze the device reliability [28].It is observed that Kstable > 1 at greater frequencies, however, a small change of 12% in critical frequency is notable at Kstable=1 as the temperature falls from 400 K to 50 K denoting improved RFstable device at DCT [29][30].

D. Impact of DCT on interface trap charges
Transistor reliability is widely governed by the presence of the interface traps charges densities (ηitc) at the semiconductordielectric juncture post tape-out.These traps states are responsible for the SRH recombination and generation [31].
Thus, the impact of DCT on ηitc is thoroughly investigated via DCT-DG-JL-MOSFET electrostatics.Fig. 14 (a) and (b) highlights the transistor transfer characteristics (I-V) for ηitc= -10 12 cm -2 to +10 12 cm -2 at 300 K and 50 K.It is observed that negative ηitc results in reduced current mainly due to the fact that it leads to the formation of acceptor-states present above the valence energy-band which captures electrons.However, for positive ηitc, there will be donor-states formation below the conduction energy-band which will enable hole capturing thereby boosting the current [32].Further, the influence of ηitc on the transistor transconductance at 300K and 50K is analyzed in Fig. 15 (a) and (b).Higher transconductance for positive ηitc and lower transconductance for negative ηitc can be noted for both 300 K and 50 K.This can be accounted from the current behavior in the transfer characteristics profile in the presence and absence of polarized ηitc.

E. Transient response at DCT
Lastly, this article discusses about the transient response of the DCT-DG-JL-MOSFET when temperature is varied from 400 K to 50 K in Fig. 16.As the device is cooled, it is observed that the settling-time shrinks from the inset.This is notable since the impurity-freezing leads to enhanced carrier mobility thereby boosting the device electrostatics as observed so far.Thus, reduction in settling-times provides realizing low delay transient models for quantum computational systems [33].

IV. CONCLUSION
The influence of cryogenic temperatures on a high-k stacked dual gate junction-less MOSFET has been analyzed widely to pave a deterministic approach towards quantum computation.The impurity freezing leads to enhanced carrier mobilities and reduced scatterings thereby boosting the device electrostatics beginning with the dc, analog and RF metrics.Sharp ON-OFF current ratio, SS profile, excellent transconductance, reduced terminal parasitic capacitances, greater cut-off frequency, unilateral power gain, gainbandwidth product and improved RF stability is reported at deep cryogenic temperatures.The reliability check is further extended with the investigation of polar interface trap charge densities present at the silicon channel/oxide juncture.It is observed that negatively ionized trap charges provide degraded electrostatics in comparison to positively ionized trap states when analyzed at 300 K and 50 K temperatures.The analysis in concluded by the investigation of several settling-times for drain currents for varying temperatures in transient response.It is noted that cryogenic temperatures provide low delay and faster settling time.Therefore, the results from the analysis concludes that improved electrostatics and better RF stability of the DCT-DG-JL-MOSFET at deep cryogenic temperatures can be integrated with CMOS technology and used for various low-power, faster and accurate quantum computations.

Fig. 1
Fig.1 depicts a three-dimensional graphic of the DCT-DG-JL-MOSFET with silicon channel length, Lchannel=40 nm.The source and drain lengths are 25 nm each constituting an

Fig. 2 .
Fig. 2. Validation results in terms of transfer characteristics of the simulation and experimental data of Colinge et al.