Frequency and voltage-dependent electrical parameters, interface traps, and series resistance profile of Au/(NiS:PVP)/n-Si structures

A thin (NiS-doped PVP) interface layer was spin-coated on n-Si substrate, and between Au contact were prepared on the surface by the sputtering method and then their basic electrical features, for example, diffusion-potential (VD), doping density of donor-atoms (ND), Fermi-energy (EF), barrier-height (ΦB), and depletion layer-width (WD) were extracted reverse-bias C−2-V plots as function frequency and voltage. The voltage profile of interface/surface-states (Nss)/ relaxation-times (τ), and series resistance (Rs) were also obtained from the admittance and Nicollian-Brews method, respectively. Strongly frequency-dependent and voltage, especially in both accumulation and depletion regions due to the existence of Nss, Rs, and polarization as well as (NiS-doped PVP) organic interlayer. At low frequency, the observed higher value of C and G shows that thin (NiS:PVP) interlayer can be successfully used to obtain high charges/energy storage (MPS) structure/capacitor instead of conventional insulator layer performed traditional methods. As a result, the observed important changes in electrical parameters with frequency and voltage depend on Nss, their τ, Rs, organic interlayer and interfacial or dipole polarization.


Introduction
In electronics and semiconductor physics, the value of C and G of the electronic devices such as a diode, photovoltaic devices, and capacitor increase with increasing voltage, and hence C-V and G-V plots show three different zones and they are called inversion, depletion, and accumulation regions. The practical status is maybe different in these regions because of the existence of these N ss , interlayer, R s , and polarization. Therefore, the quality of electronic devices by an organic interface layer is dependent on different parameters like the interface/surface states (N ss ), surface-morphology/preparation, the thickness and permittivity of the interlayer, series-resistance (R s ), the doping level of acceptor/donor-atoms (N a / N d ) and their uniformity, frequency, voltage, and temperature [1][2][3][4][5][6][7][8][9]. When an oxide interlayer, for example, semiconductor insulator, metal, organic material, and ferroelectric performed between metal and semiconductor interface, MS structure turns into MIS, MPS, and MFS type structure and then gains capacitor features which can store electronic charges or energy [10][11][12][13]. Many N ss or dislocations may be occurred in the fabrication process of the electronic devices due to energy localization in the bandgap of the semiconductor and interface layer.
The relationship between the surface-state charging process and C/(G/w) of these structures under an external circuit was well interpreted by Nicollian & Goetzberger [5]. R s value is effective on the performance of these structures, and the voltage and frequency dependence of it can be extracted from impedance/admittance technique investigated by Nicollian & Brews [4] method by using the measured capacitance/conductance (C m /G m ) data. But the real value of R s of these structures is corresponding to the experimental results of C and G at accumulationzone (C ma /G ma ) in adequate high frequency (f C 0.5 MHz). The effects of R s may be eliminated by making C/G-V measurements at low or intermediate frequencies, which means that both the N ss and R s have a significant effect on the electrophysical properties of the fabricated device which should be considering the calculation to get more precise results [14][15][16][17]. While N ss is more important both in depletion and inversion zone at low-moderate frequencies, R s is effective only at accumulation zone at high frequencies. The charges at traps/states can easily follow the alternating ac signal and hence may be produced an excess capacitance/conductance (C ex /G ex ) to the real value of them by depending on their life-time (s) of them and the frequency or period of the measured C and G values [4,[7][8][9][10][11][12][13].
The first aim of this study is to use (NiS-doped PVP) organic interlayer instead of conventional insulators and then investigate their basic electrophysical features, for example, diffusion-potential (V D ), doping density of donor atoms (N D ), Fermi energy (E F ), barrier height (U B ), and depletion layer width (W D ) as function voltage and frequency. The next purpose is to obtain the extracted voltage-dependent profile of N ss , their relaxation-times (s) and R s . For these two aims, both voltage-frequency dependences of C and G/x were performed in wide range frequency (1 kHz-1 MHz) and voltage (-2 V/ ? 3 V). The measured electrophysical parameters show strong frequency dependence features in the depletion and accumulation region. The reasons for these effects are because of the existence of N ss , R s, and polarization as well as (NiS-doped PVP) organic interface layer.

Experimental details
In the first step, for preparation of NiS nanostructures, 0.2 M from Nickel chloride.6H 2 O (NiCl 2 , KBR) was dissolved in 40 ml distilled water and stirred 30 min, then 0.5 M Na 2 S 3 H 2 O(LOBA Chemie) added to solution drop by drop until pH of solution be 7. Then by adding the 0.5 M NaOH(Merk), reserved pH = 14. 15 min by Power = 180 in Microwave device, then the precipitate was washed five times in water and kept to dry in Oven for 48 h. Finally, the precipitate was annealed in 1000 centigrade. At the end of the process, the green powder was obtained.
The absorbance spectrum of NiS has been shown in Fig. 1. Absorbance peak of NiS calcined in 1000 8C, is in 380 nm. The MPS type SBDs were prepared on an n-type (phosphorus-doped) Si wafer with 300 lm thick and 4 X cm resistivity. Firstly, it was cleaned in H2O, H 2 O 2 , and NH 4 OH (3:1:1) solution at 70°C in the ultrasonic bath and then rinsed in the high-resistivity deionized water at a prolonged time. Secondly, ohmic contact with Au (99.999%) with 150 nm thick was prepared by thermal evaporation method on the other side of the Si wafer at the pressure of 10 -6 Torr. The prepared film was annealed at 500°C in the nitrogen-atmosphere for 5 min after the formation of ohmic contact. Firstly, prepared NiS nanostructures in powder form were dissolved in deionized water as used solvent to obtain PVP solution (8% w/w), while was heating up to 80°C temperature and mixture for 3 h. NiS-PVP solutions were mixed at room condition and then coated onto the front of the n-Si wafer by a spin coating method (SCM) because of its higher spin-velocity and longer spin-times leads to create a thinner film on the semiconductor substrate. Therefore, the prepared (NiS-PVP) solution was grown on the front side of the n-Si wafer by the SCM. Finally, Au rectifier contacts with 7.85 9 10 -3 cm 2 areas and 150 nm thick were formed on the (NiS-PVP) interlayer at 10 -6 Torr. Both back-ohmic and front-rectifier contacts were performed by using the BESTEC thermal evaporation system which four crucibles has made by tungsten to evaporate different metals onto substrate/semiconductor and metal-thickness-meter. Both the schematic diagram of the formed Au/(NiS:PVP)/n-Si structures and the measured impedance or admittance measurement system were given in Fig. 2 (a) and (b), respectively. HP 4192A LF impedance analyzer and an I-V measurement system were used for C-V and G/x-V analyses.

Experimental results
C-V and G/x-V characteristics of the fabricated Au/ (NiS:PVP)/n-Si Schottky structure are presented in Fig. 3 and Fig. 4, respectively, in frequencies from 1 kHz to 1 MHz and voltages -2 V to 3 V. As indicated in these two figures, both the C-V and G/x-V plots have three zones depends on the accumulation

regions for intermediate and high frequencies like a MOS type capacitor.
It is seen inset in Fig. 3, C-V plots at zero-voltage or in the weak inversion region because of a special distribution of N ss and dipole or surface polarization for low and intermediate frequencies [1,[4][5][6][7][8][9][10]. Because there are many kinds of N ss and they have different relaxation/life-times (s) and at low frequencies are depend on alternating ac signal. Because at very low or intermediate frequencies, the electronic charges located at any traps or surface-states can be easily followed an alternating ac signal and hence supplied both an excess C and G to the real value of them contrary to high frequencies because of the relaxation-time (s) of them have not enough time to charge movement by ac current. [4][5][6][7][8][9][10].
On the other hand, for low-frequencies, the polarization mechanism in the interfacial layer can change the trap mechanisms. In general, there are different polarization process, and all of them depends on the ac electric field and frequency, which are electronic, atomic, dipole, and interfacial/surface polarization [28]. But, among them, while electronic and atomic  polarization are effective only at very high frequencies (10 10 -10 15 Hz), but dipole and interfacial polarizations are effective only at low frequencies or a few kHz, respectively. Therefore, in the measured frequency range of 10 kHz-1 MHz in this study, the last two types of polarization which are usually known Maxwell-Wagner type polarization. While the R s and interlayer are effective only at accumulation or high forward bias voltages at high frequencies, N ss is effective both in depletion and weak inversion regions at low frequencies. If the MS structure has R s , N ss , and an interfacial layer, applied bias voltage (V a ) across the structure will be shared among them as Surface states (Nss) which are located at between metal and semiconductor (M/S) are usually originate from semiconductor surface imperfection like doping bonds, oxygen vacancies, structural re-arrangements due to metallization, doping level of donor or acceptor atoms and native or deposited an interfacial layer at M/S interface. These traps or states are considerably effective on the electrical parameters and conduction mechanism of the fabricated semiconductor devices. According to Card and Rhoderick, Nss can be also considered as electronic states generated by unsaturated dangling bonds of the surface atoms and some organic contaminations in laboratory environment [6]. On the other hand, series resistance (Rs) are usually originate from the contact made by the probe wires to the gate and back metal contact to the semiconductor, some impurities or dislocation at junction, the bulk resistance of the semiconductor, and extremely non-homogeneity doping distribution of donor or acceptor atoms. Therefore, in this study, we focused on the effect of Rs and Nss due to the significant effects on the electrical and conduction mechanisms [4,5]. As can be seen in Fig. 3, the C-V plot shows a concave curvature at the accumulation region, especially due to the existence of R s and interlayer. Therefore, both the draw of the N ss and R s versus frequency for various bias voltage in depletion region by using the C-V and G/x-V data are more important. The high-value of R s may be created errors in electrical parameters, especially at the accumulation region, but this effect may be minimized utilizing the proper washing and cleaning process of the semiconductor surface and device preparation processes and applying a correction or/adjustment these measurements before the desired information is extracted. The voltage-dependent profile of the resistance (R i ) can be extracted from the Nicollian-Brews method in the whole measured frequency and voltage range. But, according to this method, the value of R i at high-frequencies (f C 0.5 MHz) is corresponding to the real value of R s for MOS/MPS type structures and can be calculated from the measured capacitance and conductance at a strong accumulation-zone (C ma and G ma ) data as following [24]: In order to determine the effects of the R s on the impedance/admittance based on measured C-V and G/x-V, the voltage-dependent profile of R i was calculated by using Eq. (1) for each frequency and is illustrated in Fig. 5. The value of conductance (G = 1/R) is related to R s . In other words, the decrease of R s at the accumulation region for high frequencies is the result of the increase of conductance. As can be seen in Fig. 5, the R i -V plots have a peak, and while the magnitude of peak decreases with increasing frequency and the peak position shifts towards to accumulation region due to reordering and restructuring of surface states under the electric field. Therefore, the measured C m -V and G m /x-V curves of the MPS structure for adequate high frequency (1 MHz) were corrected as C c -V and G c /x-V curves and given in Fig. 6 (a) and (b), by using the following relations, respectively. While the values of Nss are usually effective both in depletion and inversion region, Rs is usually effective at accumulation region rather than depletion region. As shown in Fig.6 (a) and (b), after corrections were done to eliminate of Rs, the value of capacitance become increase whereas the value of conductance decreases. In other words, the observed concave curvature or peak in the C-V and increase in G/x-V plots at higher frequency is result of the Rs and interfacial layer effects [29][30][31][32][33][34]. Because, when applied bias voltage on the structure, it will be shared by interfacial layer, Rs and depletion Fig. 6 The plot of R i -V and Rs-ln(f) characteristics of the Au/(NiS:PVP)/n-Si structure for various frequencies layer. Therefore, the corrected G/x-V plot gives a peak in this region.
As shown in these figures, the corrected value of C c increases with increasing voltage and the observed concave-curvature of C m -V curve at the accumulation region becomes disappears due to the elimination R s effect. But, the corrected G c /x-V curve becomes decreases and gives a peak at about 1.45 V. As can be clearly seen in Fig. 6 (a) and (b), the value of R s is more effective on the C m -V and G m /x-V curves for high frequencies and hence should be taken into account in the calculation in the admittance measurements [2,4]. The electrophysical parameters of the prepared Au/(NiS:PVP)/n-Si structure such as V D = V o ? kT/ q, N D , E F , W D , E m , and N ss were extracted from the linear part of the reverse-bias C -2 -V plots for each frequency by [1,2].
In Eqs. (3)(4)(5)(6): A is the area of rectifier-contact, e s is the dielectric-constant of semiconductor (e s = 11.8e o Table 1 The values of various basic parameters for Au/(NiS:PVP)/n-Si structure calculated from the C-V and G/x-V plots in the frequency range of 10-1000 kHz f (kHz) V D (eV) N D x10 14   for Si), e o is the dielectric-constant of vacuum, N C is the density of states at conduction-band (E c ). The reverse bias C -2 -V characteristics of the Au/ (NiS:PVP)/n-Si structure measured at room temperature for various frequency is given in Fig. 7. As can be seen in Fig. 7, these plots have a good linear relation in the wide voltage range of (-1.6 V)-(-0.5 V). While the value of intercept-voltage (V o = V i ) was extracted from the intercept of the C -2 -V plot f at zero-bias voltage, N D was extracted from the slope of this plot for each frequency. As can also be seen in Fig. 7, the used an enough thick interfacial layer leads to a large intercept voltage which is becoming higher than the bandgap of a semiconductor depends on surface states. Therefore, the value of V o was modified by using the constant (c 2 ) which is given as following [2]: Since the value of c 2 is closer to 1, then the value of N ss is closer to zero, c 2 is closer to zero then the value of N ss becomes very high. Therefore, both the mean value of N ss for each frequency was calculated by using Eq. 6 and was tabulated in Table 1. Thus, the modified value of BH was calculated by using the following relation for each frequency [1,2]: It is seen in Table 1 and Fig.8 (a) and (b), the values of N D , U B , W D , and E m are a strong function of frequency and increase with increasing frequency as linearly because surface states cannot enough follow the external alternating signal at higher-frequencies. These values changed from 6.79 9 0 14 cm -3 , 0.443 eV, 72 lm, and 1.98 kV/cm for 10 kHz to Fig. 10 The plots of (C lf -C hf ) curves and inset Nss-V curve of the Au/(NiS:PVP)/n-Si structure Fig. 11 The C-ln(f) characteristics of the Au/(NiS:PVP)/n-Si structure for various bias voltages 8.88 9 0 14 cm -3 , 1.133 eV, 135 lm, and 8.50 kV/cm for 1 M Hz, respectively. In addition, the value of N ss decreases from 8.49 9 0 11 eV -1 cm -2 (at 10 kHz) to 4.70 9 0 11 eV -1 cm -2 (at 1 MHz). These lower values of N ss were attributed to the passivation effect used (NiS-doped PVP) organic interlayer. In other words, the higher value of N ss at low frequencies is the result of their capability to follow the ac signal and dipole or surface polarization. All these results are indicated that N ss can be able to keep up with the ac signal in both low and intermediate frequencies and hence yielded an excess capacitance and conductance to the real values. Therefore, the intercept point of the C -2 -V plot in the reverse bias decreases with decreasing frequency. As a result, both the surface states and polarization are usually more effective both in inversion and depletion regions, but R s is effective only at the accumulation region.
The voltage or energy-dependent profile of N ss can be determined by several methods such as Hill-Coleman, low-high capacitance (C lf -C hf ), and admittance or parallel-conductance [8,[14][15][16]. Among them, the first method (Hill-Coleman) is valid only when C-V or G-V plot has a peak. The second method (C lf -C hf ) requires only two C-V curves at enough low and intermediate-high frequency, and the last one (admittance) is a more sensitive and accurate method but requires a lot of C-V and G/w-V curves in a wide range of frequency and developed by Nicollian-Brews [4]. Therefore, voltage-dependent profiles of N ss and their life-time (s) extracted from both the low-high (10 kHz-1 MHz) and parallel-conductance techniques. Figure 9 shows the C-V plots for 10 kHz and 1 MHz, and the obtained N ss -V plot by using the following relation from these two plots was also represented inset in this figure [4,8,16].
In Eq. 9, C i is the interfacial layer capacitance that can be obtained by using the value of C and G at adequate high frequency at the accumulation region as follow [4]. As can be seen inset in Fig. 9, the N ss -V plot has peak behavior due to a special density-distribution of N ss between polymer layer and semiconductor in forbidden-bandgap of Si. It is clear that the observed discrepancies in low (10 kHz) and high frequency (1 MHz) C-V plots both in inversion and depletion are the results of existence N ss and polarization at low frequency, but is the result of Rs at high frequency at accumulation layer. Therefore, it is more important to take of N ss and R s effects in the C-V and G-V characteristics [4,5].
For more elucidation of the voltage and frequency effects on the C and G/x values, both the C-ln(f) and G/x-ln(f) plots were also drawn and given in Figs. 10 The G p /x is the result of loss mechanisms occurring when surface-states/traps capture or emit charge carriers and the values of G p /x-ln(f) curves give a peak (Fig. 12) at x = 1.98/s and hence the values of N ss for each bias-voltage can be obtained calculated from the peak value of these plots as follow: Figure 12 shows the Gp/x-ln(f) curves of the Au/ (NiS-PVP)/n-Si (MPS) structure for various forward bias voltages (0.4-2.0 V by 50 mV steps). The Gp/x In(f) curves have a clear peak, while its magnitude increase with increasing forward bias voltage, its position shifts towards the accumulation region depend on the density of N ss and their relaxationtime under external an electric field and oscillation voltage [1,4]. Such peak behavior of parallel-conductance peak was attributed restructure and reordering of charges at interface traps or states under an external electric field. For the peak value of G p /x-ln(f) plot, xs is equal to 1.98 and so N ss = (G p / x) max /(0.402qA). In this way, both the value of N ss and s were calculated from these equations for various applied bias voltage and given in Fig. 13 and Table 2.
It is clear from both Table 2 and Fig. 13, while N ss increases with increasing bias voltage, s decreases almost as exponentially. Also in Table 2, the values of N ss and s were found as 1.121 9 10 12 eV -1 cm -2 and 187 ls for 0.3 V and 1.214 9 10 12 eV -1 cm -2 and 151 ls for 1.3 V, respectively. The values of N ss are in order of * 10 12 eV -1 cm -2 , and this order is very suitable for such MPS and MIS type structures. These low-values of N ss are the result of the passivation effect of the used (NiS-doped PVP) organic interlayer. All obtained results confirm that the utilized (NiSdoped PVP) organic interface layer can be effectively utilized instead of widely used conventional interface layers. There are also similar expressions in the different previously published literature [35][36][37][38][39][40][41][42].

Conclusion
Au/(NiS-PVP)/n-Si (MPS) structures were performed and then the electrophysical characteristics of them have been studied in detail. C and G/x values were found the strong frequency dependence and electric field (E = V/d). The observed higher values of them at very low frequencies were due to the existence N ss located at Au/(NiS-PVP) interface and polarization processes. Some main electrophysical features such as V D , N D , E F , U B , W D , and E m were calculated from the intercept and slope of reversebias C -2 -V plot for each frequency. The value of U B was found to increase with increasing frequency as U B (lnf) = (0.158x ? 1.055) eV. The values of N D , W D , and E m were also found to increase with an increasing frequency almost linearly. Voltage-dependent profiles of R s , N ss , and s were extracted from the admittance method, respectively. As can be seen in Table 2, the values of N ss and s were found as 1.121 9 10 12 eV -1 cm -2 and 187 ls for 0.3 V and 1.214 9 10 12 eV -1 cm -2 and 151 ls for 1.3 V, respectively. These values of N ss are convenient for such MPS and MIS type structures as the result of the passivation effect of the used (NiS-doped PVP) organic interlayer. NiS-doped PVP organic interlayer has some advantages in comparison with other conventional interfacial layers.