Design and Investigation of F-shaped Tunnel FET with Enhanced Analog/RF Parameters

In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration is well optimized and analyzed for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric. Also, we optimized some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, sub-threshold swing and various capacitance to rectify the analog/RF performance of single gate F-shaped TFET. Regarding this, we concurrently optimize the lateral tunneling length between source and gate with optimization of source thickness. The variation in lateral tunneling length, the potential and strength of electric field at fixed Vgs voltage is varied which leads to effective change in the ON-current, average sub-threshold swing, and turn ON-voltage. Another side, as well as the source thickness vary, the electric field variation takes place near the edge of source, which leads to variation in the ON-current and ON-voltage. The performance parameters of single gate F-TFET is compared with single gate L-TFET, which is the incentive of this submitted work. The optimized single gate F-TFET have 0.30 V turn ON-voltage with 7.4 mV/decade average sub-threshold swing and high Ion/Ioff ratio approx 1013. Besides, a significant reduction in parasitic capacitance is beneficial to enhanced RF performance with better controllability on channel.


Introduction
To get the better of MOSFET, Tunnel FET (TFET) has been brought in as an auspicious candidate for a low power application because its sub-threshold swing (SS) can be scaled down than 60 mV/dec [1,2]. At the initial, the Sibased single gate Tunnel FET experience very low I ON with high ambipolar conduction because of approximately same band-to-band (B2B) tunneling on both drain/channel and source/channel interface [3]. Furthermore, Dual-Gate TFET (DG-TFET) was introduced for better channel controllability to improve the I ON current but again the Prabhat Singh ec1106831049@gmail.com Dharmendra Singh Yadav dsyadav@nith.ac.in 1 Electronics and Communication Engineering Department, NIT Hamirpur, Himachal Pradesh, 177005, India ambipolar conduction is a major issue [4]. Likewise, various type of techniques and strategies have been proposed to overcome the ambipolar behavior of Tunnel FET device [5][6][7]. Furthermore, there is some limited research article that has improved I ON and suppressed ambipolar conduction with reduced average sub-threshold swing (SS avg ) by increasing BTBT region [8,9]. Some of them, various structure/shape of TFET has been proposed to achieve the improved result in comparison to the previous one [10][11][12]. As well as the new structure came into existence, some parameter optimization also came into the picture like Threshold voltage (V T ), gate-to-drain capacitance (C gd ), gate-to-source capacitance (C gs ), cut-off frequency (f t ), Gain Bandwidth product (GBP), transit time etc.
For the low power application, we need low V ON , which is defined as minimum gate-to-source voltage (V gs ) at which a transition path has been created between the source and drain region [13]. A novel device structure for low power application named as single gate F-shaped TFET (SG-F-TFET) has been proposed and optimize which consists highly doped source enclosed by a lightly doped silicon region. With the help of the electric field crowding effect, the SG-F-TFET is supposed to minimize V ON as the source thickness is decreased [14,15]. 2D TCAD tool is used to simulate and analyses the analog/RF properties of the SG-F-TFET.

Schematic and Specifications of Designed Device
The 2D schematics of DG-TFET, Hetero Material DG-TFET (HMDG-TFET), Single Gate L-shaped TFET (SG-L-TFET), and Single Gate F-shaped TFET (SG-F-TFET) are set out in Fig. 1a-d respectively. Table 1 lists the basic device dimension parameters used for carrying out TCAD simulations. The simulated structures uses physical doping techniques to introduce the dopants in the device. In Fig. 1a, a low-k gate oxide (SiO 2 ) based homo double gate TFET structure is shown which consist Si/Si/Si semiconductor material for source, channel, and drain respectively with L S = 55 nm, L C = 50 nm, L D = 55 nm and t OX = 1 nm. Further, in Fig. 1b, a schematic of high-k gate oxide based hetero double gate TFET shown which consist Si/GaAs/GaAs semiconductor material for source/channel/drain region respectively. The higher bandgap material (GaAs) is used in channel and drain region to eradicate the ambipolar conduction. For further analysis, SG-L-TFET is simulated with source thickness 35 nm and drain thickness is set to 6 nm with oxide thickness 1 nm, considering these the ambipolar conduction is suppressed but the turn ON-voltage is quite high (Fig. 1c). So, a new device structure, SG-F-TFET is proposed to decimate the limitation of all previous simulated devices.
A physical doping-based SG-F-TFET is simulated and analyzed for the various device and analog parameters. This simulated structure called "F-shaped" because its channel resembles the finger like source and its 2-D cross sectional view shown in Fig. 1d. Different colors are shown in Fig. 1d define gate oxide, drain, source,channel regions, and electrodes. SG-F-TFET resembles an ultra-thin highly doped source that is enclosed by lightly doped silicon regions. For analysis and simulations, the doping levels were 1x10 20 cm −3 , 1x10 18 cm −3 and 1x10 15 cm −3 for the source, drain, and channel regions respectively with 4.5 eV gate work function (W F G ).
The simulation of designed devices is carried out on 2D device simulator TCAD tool [16]. To appropriate internal operation of devices, nonlocal band to band (B2B) tunneling model is used to incorporate the quantum tunneling phenomena at SCIn (source/channel interface)

Device Analysis Procedure
The vertical and lateral device dimension is chosen carefully during simulation process to compare the proposed device performance w.r.t to other simulated devices which were optimized earlier by researchers. In addition with, fine messing is defined near drain/channel and source/channel interface where B2B tunneling takes place. Mesh size near B2B tunneling interface is set to 1 × 10 −4 μm and mesh size = 5 × 10 −3 μm far of interface. The nonlocal B2B tunneling model was applied with Newton's numerical method based on iteration (up to 25 iterations) for better convergence of current [4,17]. Excluding this, to analyze RF functioning, a small signal AC analysis was performed by setting frequency at 1 MHz. The generalized decision making flow chart for device simulation is shown in Fig. 2.

Details of Device Analog/RF Parameters
This sub-section is considered for a concise front matter about analog/RF performance parameters e.g. Transconductance (g m ), f t , GBP, Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Transit time (τ ), and parasitic capacitance (C gd and C gs ) [18].
A mathematical expression of C gd and C gs has given in Eqs. 1 and 2 which play a pivotal role to extract device performance and responsible for parasitic oscillation at various operating frequencies. The first order differentiation of drain current (I ds ) w.r.t. V gs is known as g m , convey in Eq. 3. The value of g m is used to check the device speed. A higher value g m , faster switching response of device [19].

Fig. 2 Flow chart for simulation on TCAD tool
Another important device parameter is f t , it is the max. frequency at which a given device works properly without any performance debasement. f t is also interpreted as an operating frequency at which short circuit gain becomes equal to unity. To analyses, the f t parameter of device w.r.t to parasitic capacitances, the relation between both is given in Eq. 4.
The mathematical expression for GBP is given by Eq. 5. As per equation, it is directly in proportion to g m value and inversely proportional to C gd value of the device [20,21]. A high value of GBP is required for superior high frequency performance.
TGF and TFP are substantial parameters to account for device efficiency and the trade-off between power dissipation and operating bandwidth respectively. Both device parameter values should be high for low power circuit operation with high speed. The mathematical equations of TGF and TFP are given by Eqs. 6 and 7 respectively [5,22,23].
Another crucial operational factor for RF analysis is transit time which is defined as the time requires to charge carriers to be shifted from source to channel, given by Eq. 8. According to this mathematical equation, transit time is inversely proportional to f t . If the f t value increases the transition time decreases [24].

Performance Analysis of Devices
This section edifies the impact of the shape of source and channel regions on the performance of physically doped TFET. For this, the effect can be observed on alignment of energy bands and strength of electric field. At room temperature (T = 300 K), energy band alignment at source/channel interface (SCIn) is approximately close for all simulated device structures for OFF-state condition because week electric field is present without V gs application (Fig. 3a).
On the other hand, at T = 300 K, V gs > 0V is applied (ON-state condition), the source's VB (Valence band) and channel's CB (Conduction band) get aligned. From Fig. 3b, band alignment for DG-TFET and HMDG-TFET is close enough. Similarly for the SG-L-TFET and proposed device. Along with, a relative electron and hole concentration of all devices are shown in Fig. 4a at same doping levels. The electric field strength at SCIn is different for all devices because of the change in shape of source and the use of hetero material (Fig. 4b). The electric field strength for proposed device is significantly large compared to other simulated devices. This effect is reflected in terms of high ON-current with low V ON for the SG-F-TFET, as shown in Fig. 5.

Impact of Lateral Tunneling Length (L T )
The initially designed SG-F-TFET was simulated by varied the L T from 10 nm to 2 nm, to analyze the impact on I ON /I OF F ratio, ambipolar current (I ambi ), V ON voltage and analog/RF parameters. Figure 6a shows the EBD for different L T along the channel direction at thermal equilibrium condition. In this Fig. 6a, the steepness of tunneling junction in not significantly affected by L T variation but at other hand the electric field strength at SCIn diminished as well as L T value is increases. Due to  increment in L T value the surface potential at fixed gate to source voltage is decrease which impact shown in term of reduced electric field (up to 2.3 × 10 6 V /cm) (Fig. 6b). This can effect the I ON range because a high electric field helps to achieve better B2B tunneling rate [25,26]. In this concern, a comparison between I ds − V gs characteristics for different values of L T is presented in Fig. 7. For significant observation related to ON-current variation, I ds − V gs curve is plotted on linear axis (Fig. 7, Y-axis, Right-hand). Along with, I ds −V gs curve also plotted on log scale (Fig. 7, Y-axis, Left-hand) for extraction of SS avg and V ON of proposed device.
The I ds −V gs curve of proposed device is shifted towards the lower V gs value on X-axis, which indicates that V ON is reduced with miniaturization in lateral tunneling length because of potential value at fixed V gs is reduced [27,28]. Along with, the steepness of I ds − V gs curve also improved as L T reduces, it is imputed to the smaller tunneling width at 2 nm and 4 nm L T . Likewise, I ON increases as L T decreases (Fig.7), because of decreased tunneling width for ON-state condition. The I ambi of proposed device is not much affected by the L T because ambipolar behavior of TFET mainly depends on the drain/channel interface (DCIn) [29] and L T does not affect this interface in this proposed work.
The gate-gate capacitance is mainly composed of two capacitances C gd and C gs , shown in Fig. 8 [24]. A significant reduction in capacitances is reflected with decrease L T because of high tunneling effect which reduces the carrier accumulation rate. The C gd is a dominant capacitance due to the accumulation of the electron of channel-source and collected by the drain region [30,31]. The finger like source helps to reduce the capacitances by reducing the accumulation of opposite type charge carrier near channel-source and channel-drain interfaces. The reduced value of C gd helps to attain superior gate controllability over the channel region. The C gd value of SG-F-TFET is reduced up to 0.5 fF at L T = 2 nm and 4 nm because of reduced drain-channel interface (6 nm), as shown in Fig. 8a. As shown in Fig. 8b, the reduced value of L T reflected in terms of decreased C gs because of high tunneling at SCIn. In addition to C gd and C gs are also a parameter of interest for high-frequency introspection of device operations.
From Fig. 9a, the SG-F-TFET achieves a higher transconductance (g m ) value at the higher V gs for L T = 2 nm and 4 nm due to high steepness of I ds -V gs curve, whereas g m starts decreasing after achieving the peak because of less variation in I ds w.r.t V gs as mention in Eq. 3. The high frequency performance of the proposed device was analyzed by f t and GBP [32]. The f t can be evaluated by the ratio of g m to C gg (C gd + C gs ) as mention in Eq. 4. A higher range of f t is achieved for L T = 2 nm and 4 nm at higher value of V gs due to high g m at higher V gs and reduced total capacitance (C gg ) in comparison to other high values of L T , mention in Fig. 9b. After attaining its maximum value, f t graph starts decreasing because of the higher value of C gd for V gs > 1.25 V [27,33,34]. Along with, GBP is higher  (Fig. 8a) value as shown in Fig. 10a.
Another remarkable RF analysis performance parameter is transit time, which is inversely proportional to f t value. The transit time is decreased when f t increases. For a lower value of transit time, speed of the device is improved [2]. From Fig. 10b, it can be analyzed that, transit time is very less for L T = 2 nm for lower V gs . But for the higher V gs value, it is similar for all L T variations.
The TFP and TGF curve with L T variation is shown in Fig. 11. For L T = 2 nm and 4 nm we get very high TFP, which helps to enhance the device speed with low power consumption [35]. Figure 11b communicate the TGF variation for all L T value. For 2 nm and 4 nm of L T , TGF is maximum in sub-threshold region for V gs > 0.8 V . So proposed device with L T = 2 nm or 4 nm can be used effectively for switching applications. Considering the above analysis based on L T variation, the optimum L T is set to either 2 nm or 4 nm, since the increase in I ON , V ON , SS avg with improved analog/RF parameter. To select the optimum value of L T = 2 nm or 4 nm. We have performed further analysis on the source thickness by setting L T = 2 nm and 4 nm.

Impact of Source Thickness (T S ) at 2 nm L T
In the previous section, we analyzed the effect of lateral tunneling length on SG-F-TFET. We will examine the impact of source thickness on the proposed device performance by considering two cases:

I. Source Thickness (T S ) at 2 nm L T II. Source Thickness (T S ) at 4 nm L T
In this section, the consequences of T S variation on analog/RF parameters are analyzed at L T = 2 nm. Figure 12 shows the I ds − V gs curve depending on T S and L T set to 2 nm. From this graph, we can see that, as T S is increasing, the I ON is decreasing with a very small variation in I ambi and V ON . The I ON decreases because of electric field crowding effect at the edges of the source regions decreases as well as the T S increases i.e., the electric field at SCIn is the sum of two component, field at corner of source region (E C ) and the flat region of source (E F ). As the T S increases, the effect of E C field component is minimized, so a significant reduction can be seen in the I ds value, as mention in Fig. 12. Figure 13 shows the capacitances for various T S values. The C gd curve is increasing from low to high V gs (0 -    Fig. 13 Analysis of (a) C gd and (b) C gs for T S = 3 nm to 20 nm at L T = 2 nm for proposed device 1.5 V). As the T S increases, the accumulation of electron carriers is increased at SCIn which are collected by the drain region. So, the C gd increases as source thickness increases, as revealing in Fig. 13a. Apart from this, the same effect is reflected in the C gs capacitance data plot as shown in Fig. 13b.
The g m value of a device depends on the change in I ds w.r.t V gs . The change in I ds is higher for lower gate voltage, for the decreasing value of T S . Hence, the improved g m achieved at 3 nm source thickness, shown in Fig. 14a. The high frequency performance is investigated by using two important parameters f t and GBP . The higher f t archives at 3 nm source thickness due to the high g m at higher V gs as well as the reduced value of C gg (Fig. 14b). The GBP is also high, when T S is set to 3 nm by the effect of reduced C gd for T S = 3 nm, mention in Fig. 15a.
The transit time is used to verify the device speed and it is inversely related to f t . From Fig. 15b, transit time reduces as well as T S is minimized. When T S is set to 3 nm, we obtain lowest transit time due to high f t , as mention in Fig. 14b. For T S variation, TFP and TGF curves are shown in Figs. 16a and b respectively. Both the parameter directly proportional to g m . Hence, both the parameters obtain a high value at 3 nm T S .

Impact of Source Thickness (T S ) at 4 nm L T
In this section, the consequence of T S variation on different device parameters is analyzed when L T is set to 4 nm. In the previous section, we had analyzed the impact of source thickness variation w.r.t 2 nm L T , but in this case, L T is set to 4 nm due to this the tunneling width at SCIn is increased. This effect reflects in terms of increased or decreased device parameters values. From Fig. 17, for I ON , V ON , and steepness of I ds − V gs curve at 3 nm T S , the considerable deviation can be observed. Along with, for 5 nm to 20 nm of T S , I ON is decreased compared to 2 nm L T , as described earlier in Fig. 12. As the tunneling width increase, the dominating capacitances like C gd and C gs also deliberate. When T S and L T are set to 3 nm and 4 nm respectively, the lowest C gd obtain and it will increase for high T S value (Fig. 18a). Similarly, the C gs is decreased as the T S reduced w.r.t V gs , as depicted in Fig. 18b.
Another critical device performance parameter is g m , which represents the amplification quality of the device. The g m is initially increased and strikes the maximum value and then starts decreasing because, at higher V gs , C gd is dominating parameter, as shown in Fig. 19a. The increased tunneling width does not produce any significant effect on   For frequency analysis, f t and GBP are crucial parameters. From Fig. 19b, f t values increase at high V gs for various T S , and it attains peak its value at lower V gs because g m is dominating parameter. But, after attaining the peak value, it starts decreasing due to the high value of (C gd + C gs ). Figure 20a shows GBP versus V gs graph for different T S . The simulation results indicate increased GBP with increased V gs and the peak point is shifted towards lower gate voltage as T S decreases. At L T = 4 nm, the device transit delay is increased for low gate voltage compare to L T = 2 nm for T S variation, as display in Fig. 20b.
TFP determines the device performance at the operating frequency. It shows the relationship between power and bandwidth for high speed device applications. Ultra thin source (3nm) produces high TFP (Fig. 21a) when L T is set to 4 nm. Further, to examine the device's ability to convert power into speed, we can evaluate the TGF parameter. The higher value of TGF rewired for high speed of the device. Hence the appropriate TGF value is selected at 3nm source thickness, as shown in Fig. 21b.
To clarify and to select the optimized value of L T (2 nm or 4 nm) with optimized source thickness, a comparative analysis is performed w.r.t SS avg and V ON at different T S values. The lowest value of V ON is achieved at T S = 3 nm and L T = 4 nm, but as well as the T S increases the V ON is higher for 4 nm L T as compared to 2 nm of L T , mention in Fig. 22a. Same way, the SS avg of the device examines at different T S when L T set to 2 nm and 4 nm. from Fig. 22b, we can see that SS avg is minimum for T S = 3 nm and L T = 4 nm. But, the SS avg for higher source thickness is high for L T = 4 nm.

Optimization of Device Lateral Length
For future aspect, it is influential to analyze the scaling perceptiveness of SG-F-TFET. The channel length (L C and L C1 ) is already selected very carefully to get superior performance of proposed device, but the drain and source lateral length is consider w.r.t. comparative analysis. So, the down scaling is performed on L S and L D to optimize the total device length without affecting its performance.

Down Scaling of Source Lateral Length (L S )
In this sub-section, we will figure out the optimal value of the L S such that the characteristics of the device are not severely affected. Figure 23a and b shows the electric field     26 Analysis of (a) C gd and (b) C gs at various L D to optimize the proposed device lateral length. Inset: an magnified C gd − V gs and C gs − V gs graph to improve the visibility for better analysis strength at SCIn and I ds −V gs curve of the SG-F-TFET w.r.t. changes in the L S from 60 nm to 35 nm. Figure 22a shows that as the L S decreased up to 40 nm, there is no effect on the electric field strength. However, as L S is decreased below 40 nm, the electric field start decreasing. Because of this decrement in electric field the I ON current of the device also start decreasing with increased V ON , as shown in Fig. 23b. The impact of down-scaling of source lateral length also analyzed on the capacitances like C gd and C gs . From Fig. 24a and b, we can see that for L S lower than 40 nm the capacitances are increased because of the very high accumulation of carrier near the SCIn with application of the high gate voltage. So, considering the above observation related to source lateral length optimization, we conclude that L S = 40 nm is needed for the optimal performance of SG-F-TFET (proposed device).

Down Scaling of Drain Lateral Length (L D )
In this sub-section, we will find out minimum value of L D such that the device characteristics are uninfluenced significantly. Initially, the drain lateral length set to 58 nm in proposed device. Figure 25a shows the electric field variation at DCIn of proposed device, it is remain unchanged until L D value goes below 38 nm. For 38 nm L D , change in electric field strength not significant. On the other hand, the I ON is not significantly change from 58 nm to 38 nm of L D . But,lower than 38 nm, i.e., for L D = 35 nm, the V ON and I ON decreased which are considerable change to degrade the device performance (Fig. 25b).
To examine the effect of down-scaling of L D on device performance with respect to capacitances of device, we also analyze the C gd and C gs for different range of L D . The C gd remain unchanged up to L D = 38 nm, after this its value suddenly become very high (Fig. 26a) because the carrier collected from the channel become very high near the DCIn region which are responsible for the gate to drain capacitances. But, the opposite effect can be seen for C gs , it is remain unchanged until L D scaled down to 38 nm and after this its value sudden fallen down in the range of 0.19 fF. The down scaling of L D shows opposite impact on the C gd and C gs . As we know, the impact of C gd is more dominant than C gs on device performance. Hence, the optimum value of L D is determined as 38 nm.

Optimized SG-F-TFET
In Section 4.2, we have optimize the parameters (L T , T S ), which can affect the electric field crowding effect (Electric field strength at edges of source region). Along with, in Section 4.3 lateral length optimization have been performed and L S and L D are optimized. SG-F-TFET can achieve the higher drain current (A/μm) and improved analog/RF parameters as source thickness (T S ) and lateral tunneling length (L T ) decreases, as mention in figures which are listed in Section 4.2 and 4.3. The optimized SG-F-TFET consists, L T = 4 nm, T S = 3 nm, L D = 38 nm, L S = 40 nm and T OX set to 1 nm, SiO 2 as gate oxide material. The W F G set to 4.5 eV and N S , N C and N D is 10 20 cm −3 , 10 15 cm −3 and 10 18 cm −3 respectively. Considering the above optimum parameters related to dimensions, final L tt of device is 103 nm with T tt = 42 nm. The analog/RF parameters of optimized SG-F-TFET are listed in Table 2.

Conclusion
A new SG-F-TFET is designed and its fundamental physics of devices and working principle are investigated in detail using the 2D TCAD simulator. The proposed modification in SG-F-TFET improves ON-state current and reduced V ON with increased SS avg (below 9 mV/decade), ambipolar current suppress drastically (10 11 order) correspond to the DG-TFET. The results confirm that SG-F-TFET can achieve a relatively lower V ON (approximately 0.3 V) with L T = 4 nm and T S = 3 nm. Along with these advantages, proposed device also consist low C gd and C gs which are causative for improved device controllability. We have also demonstrated that SG-F-TFET device is exempt to reduction in L S and L D up to 40 nm and 38 nm respectively. For analog/RF parameters such as C gs , C gd , g m , f t , GBP, TFP, TGF and transit time are analyzed to determination the feasibility of the SG-F-TFET for high frequency application with low power operation. It was found that when the L T , T S , L S and L D set to 4 nm, 3 nm, 40 nm and 38 nm respectively, SG-F-TFET shows the better performance for high frequency parameters. At the last, SG-F-TFET is expected to be fabricated by self-aligned processes. So, optimized SG-F-TFET can be utilized as promising alternative for low power high frequency applications.