Thin film ferroelectric photonic-electronic memory

doi:10.21203/rs.3.rs-3142678/v1

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Thin film ferroelectric photonic-electronic memory

https://doi.org/10.21203/rs.3.rs-3142678/v1

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To reduce system complexity and bridge the interface between electronic and photonic circuits, there is a high demand for a non-volatile memory that can be accessed both electrically and optically. However, practical solutions are still lacking when considering the potential for large-scale CMOS compatible integration. Here, we present an experimental demonstration of a non-volatile photonic-electronic memory based on a ferroelectric-silicon ring resonator. We successfully demonstrate programming and erasing the memory using both electrical and optical methods. The memory cell exhibits a high optical extinction ratio of 6.6 dB at a low working voltage of 5 V and an endurance of 4×10⁴ cycles. Furthermore, the multi-level storage capability is analysed in detail, revealing stable performance with a raw bit-error-rate smaller than 8.8×10^-3. This ground-breaking work could be a key technology enabler for future hybrid electronic-photonic systems, targeting a wide range of applications such as photonic interconnect, high-speed data communication, and neuromorphic computing.

Physical sciences/Optics and photonics/Optical materials and structures/Silicon photonics

Physical sciences/Optics and photonics/Applied optics/Optical data storage

Physical sciences/Nanoscience and technology/Nanoscale devices/Nanophotonics and plasmonics

To reduce system complexity and bridge the interface between electronic and photonic circuits, there is a high demand for a non-volatile memory that can be accessed both electrically and optically. However, practical solutions are still lacking when considering the potential for large-scale CMOS compatible integration. Here, we present an experimental demonstration of a non-volatile photonic-electronic memory based on a ferroelectric-silicon ring resonator. We successfully demonstrate programming and erasing the memory using both electrical and optical methods. The memory cell exhibits a high optical extinction ratio of 6.6 dB at a low working voltage of 5 V and an endurance of 4×10⁴ cycles. Furthermore, the multi-level storage capability is analysed in detail, revealing stable performance with a raw bit-error-rate smaller than 8.8×10^− 3. This ground-breaking work could be a key technology enabler for future hybrid electronic-photonic systems, targeting a wide range of applications such as photonic interconnect, high-speed data communication, and neuromorphic computing.

In the era of big data and artificial intelligence, conventional electronic computers based on Von-Neumann architecture struggle to meet the stringent demands of data-intensive and massive parallel tasks^1–3. To address this challenge, photonic integrated circuits (PICs) hold tremendous promise to offer a potential solution to the increasing need for computing power in the coming decades. Exploring transmission, manipulation, processing, and storage of information using optics and photonics could provide powerful solutions^4–7, leveraging the inherent properties such as high bandwidth, high power efficiency, low latency, and high parallelism^8–10. Notable successes have already been achieved in demonstrating PICs for accelerating tasks, such as non-linear programming¹¹, signal processing^12–14, photonic neural networks^15–17, and quantum computing^18,19. However, the lack of optically accessible memory poses a significant hurdle in system design, as it necessitates additional electro-optical and opto-electrical conversion processes. This has led to a growing interest in non-volatile photonic-electronic memory as a means to bridge the gap between the electronic and photonic circuits. Currently, control and data processing predominately occur off-chip due to the absence of optical memory. This results in additional loss through optoelectronic conversion and hinders the realization of optical in-memory computing. Therefore, an ideal memory for hybrid electronic-photonic systems should possess the following features: (a) non-volatile nature with high endurance, long retention, and multi-level storage capabilities, (b) the ability to be programmed and erased both electrically and optically, (c) the non-destructive electrical and optical read processes that can occur simultaneously without conflict, (d) fully compatible with the fabrication process of both electronic and photonic components.

There have been a few existing reports to realize the non-volatile photonic memory, with chalcogenide phase change materials (PCM), such as Ge₂Sb₂Te₅ (GST) receiving the most attention in recent years^20–26. They take advantage of the different absorption coefficients of GST in its amorphous and crystallization states to modify the intensity of the guided light in the waveguide. However, the reported low extinction ratio (ER) could be one of the drawbacks that limit its applications. In addition, the program/erase processes require pulse engineering, increasing the complexity of peripheral circuit design²⁰. Moreover, challenges such as resistance drifting^27,28 arising from structural relaxation, as well as the thermal crosstalk^29,30 in high-density integration of the PCM memories, are yet to be solved. Another method involves the use of the floating-gate structure, where carrier injection into the floating gate changes the refractive index (RI) of the waveguide in a non-volatile way^31,32. However, they generally require a high working voltage of a few tens of volts and operate at a low speed of a few Hz. Low program/erase endurance is another issue arising from the accumulation of interface traps in the carrier injection process^33,34. Another method employs the memristor structure where a conductive bridge is created inside the a-Si cladding layer above the Si waveguide using electrical force, resulting in non-volatile modulation of the waveguide³⁵. However, this approach faces the challenges of poor retention, low endurance, highly stochastic switching, etc³⁶. Importantly, most reported non-volatile photonic memory implementations are not electrically readable and electrically controllable, which further narrows their scope of applications in optoelectronic circuits. Furthermore, all the non-volatile photonic memory demonstrations lack a systematic investigation of the endurance and retention properties of the memory cell, which are the key figures of merit (FOMs) in all memory applications.

Ferroelectricity discovered in the doped-HfO₂ thin film has garnered significant attention as a technology enabler for emerging ferroelectric (FE) memory^37–40. Compared with FE materials in complex perovskite systems^41,42, doped-HfO₂ shows great promise and better performances for non-volatile device applications due to its full CMOS compatibility, high scalability, and advantage of retention characteristics^43,44. In this work, we demonstrate a non-volatile multi-level photonic-electronic memory by introducing an Al-doped HfO₂ (HAO) FE thin film onto a silicon photonic platform. The memory is programmable and erasable both electrically and optically at 1550 nm telecom wavelength. The electrical read and optical read processes do not conflict and can happen at the same time. Using a ring resonator structure, the memory cell achieves one of the highest ERs of 6.6 dB with a low working voltage of 5 V. The performance of the memory is analysed in detail, demonstrating multi-level storage capability with minimal errors. The device exhibits a decent endurance of 4×10⁴ cycles and a retention time of more than 10 years, proving its good stability and non-volatility. Based on our current results, our non-volatile memory could pave the way for hybrid electronic-photonic systems, with applications including photonic interconnect, high-speed data communication, and neuromorphic computing.

Design of non-volatile photonic-electronic memory cell

The non-volatile photonic-electronic memory cell is based on a ring resonator structure, as illustrated in Fig. 1a, while Fig. 1b provides the zoom-in cross-section of the ring region. The microscope image of the fabricated memory cell is shown in Fig. 1c. Light is coupled in and out of the chip by using two partially etched grating couplers. In the ring resonator region shown in Fig. 1b, an FE capacitor is directly fabricated on the Si waveguide using 10 nm-thick HAO as the dielectric layer, offering an effective modulation of the silicon waveguide by the FE polarization. In the capacitor, a 13 nm indium tin oxide (ITO) serves as the top transparent electrode, while the p-type lightly doped Si waveguide with a hole concentration (N_h) around 1×10¹⁷ cm^− 3 serves as the bottom electrode. A larger area of nickel is deposited on the Si bottom electrode to lower the parasitic resistance in the measurement. It should be noted that the fabrication of the FE capacitor is independent of the fabrication of waveguide components.

Upon applying different voltages on top and bottom electrodes, the dipoles inside the HAO film can be switched, after which a remnant polarization (P_r) corresponding to the applied electric field maintains. This P_r modifies the N_h in the p-type Si waveguide underneath the HAO, and thereby changes the RI of the waveguide. As shown by the cross-sectional view in Fig. 1b and N_h simulation results in Fig. 1d, when negative (positive) voltage is applied on the top electrode, the dipoles will be switched to a direction that can attract (repel) the holes, then the N_h in the Si will be higher (lower). Due to the permanent dipole moment after switching, the change in N_h is non-volatile and directly related to the P_r. The accumulated (depleted) holes decrease (increase) the RIs and the propagation constant, leading to the blue (red) shift of the resonance peaks. Considering the waveguide dispersion in the submicron silicon waveguide and the resonant phenomenon in the micro-ring, this effect can be quantified by⁴⁵

$$\varDelta {\lambda }_{\text{r}\text{e}\text{s}}=\frac{\varDelta {n}_{\text{e}\text{f}\text{f}}\bullet {\lambda }_{\text{r}\text{e}\text{s}}}{{n}_{\text{g}}}$$

where ∆n_eff is the effective index change induced by the difference in carrier concentration; n_g is the group index; λ_res is the center wavelength of one resonance peak; ∆λ_res denotes the wavelength shift. This shifted resonance peak position can then be optically read out by either measuring the optical spectrum when the input is a broadband light or the output power when the input is a tuneable laser aligned to a resonance peak. Non-destructive electrical reading is achieved by sensing the capacitance change using a small electric signal before and after the FE switching⁴⁶. Noted that the readings are based on different mechanisms, thus the optical reading and electrical reading can operate independently without any conflict in future electronic-photonic systems as shown in Fig. 1a.

We aim to design a photonic-electronic memory that is capable of mixed-mode operations, where optical/electrical programming/erasing are all feasible. As shown in Fig. 1a, electrical programming/erasing biases can be directly applied from the E_{program/erase} port to control the FE switching. Optical programming/erasing will rely on two photodiodes (PDs) to convert the optical power to electrical bias. These two PDs are constantly reverse-biased. When optical power is presented on the PDs, PDs serve as current sources, which can deliver the applied reverse-bias voltages to the FE capacitor assisted by a pull-up resistor. In this way, optical power can be used for programming/erasing. Upon programming/erasing, the results will be read out from the grating coupler optically, or from the E_read port electrically.

Based on the device design, the simulations have been conducted on the ring region accordingly to confirm the working principle, as shown in Fig. 1d, 1e, and 1f for N_h distribution, optical mode profile, and n_eff simulation, respectively. The FE capacitor on the Si waveguide is erased/programmed using voltages with different polarities and read at 1 V. Pronounced differences in N_h (> 8 orders difference at + 1 V reading voltage) are found in the Sentaurus TCAD simulation in Fig. 1d, which is expected due to the large and opposite P_r after programming and erasing. The waveguide is designed to have an etching depth of 120 nm and a width of 500 nm. Single-mode operation is confirmed by the Lumerical MODE simulation, shown in Fig. 1e. Due to the large N_h difference, the simulated optical effective index response in Fig. 1f shows a counter-clockwise hysteresis loop representing the effect of ferroelectric-induced modulation of N_h on optical phase, which can be further converted to resonant peak shift.

Non-volatile photonic-electronic memory cell performance

The devices were fabricated after the device design and the simulation confirmation. Detailed fabrication processes, SEM/TEM characterizations, and the electrical characterizations of the FE film can be found in the Method section as well as the supplementary material Fig. S1 and S2. When measuring the devices, the operational speed is limited by the carrier generation/recombination time of Si for the FE switching process⁴⁰. Therefore, all the measurements were carried out with a visible laser irradiating on the ring region to boost the electron generation/recombination speed. The power spectra (Fig. 2a) of the optical ring resonator were measured under a reading voltage of 1 V after programming and erasing using − 5 V and 5 V, respectively. An excellent ER of 6.6 dB is shown, which is one of the highest ER among the reported works^{20–26, 31,32,35} considering the low voltage used. For practical applications, photodetectors will be used to read the stored state. In this case, a high ER is preferred as it can lower the bit-error-rate (BER) of the stored information. A maximum peak difference of 0.14 nm is also featured in this test. Quality factors of the resonance peaks are different in these two states, indicating that the carrier concentrations are varying in different states. Detailed studies of the quality factor are shown in supplementary material Fig. S3. In addition to the spectra, we extracted the resonance peak positions and plotted them in Fig. 2b, in which clear counter-clockwise hysteresis loops can be observed for both 4 V and 5 V sweeping voltages. The hysteresis direction is critical here because it can validate the working principle. When the biasing voltage is sweeping from − 5 V to 5 V, the FE layer HAO is first programmed by -5 V, resulting in hole accumulation in the waveguide. The effect of hole accumulation is retained by the P_r of the HAO layer, so the resonance peaks in the forward (-5 V to 5 V) sweeping is blue shifted compared with the resonance peaks in the backward (5 V to -5 V) sweeping. The experimentally measured counter-clockwise hysteresis loop is direct evidence for the proper functioning of our non-volatile photonic-electronic memory.

As an integral part of all memory applications, the speed performance of programming, reading, and erasing operations is important. Here, to determine the high-speed performance of the memory cell, we examined the operation speed by using electrical pulses with the same amplitude (4 V or 5 V) but varying pulse width (ranging from 2 ns to 2 ms). The amount of resonance peak shift is used to assess the switching performance under each applied electrical pulse, as depicted in Fig. 2c. The result shows that 90% of the maximum resonance peak shift can be achieved by a -5 V, 100 µs electrical pulse. Higher voltage generally offers a higher operating speed due to a larger electric field across the FE layer. Taking the p-type substrate into account, the switching of the HAO FE layer is easier when applying negative voltages than positive voltages because more holes in the Si waveguide are available to respond to the FE switching (see electrical characterizations of FE switching speed in the supplementary material Fig. S2). For our memory cell, negative voltages are used for the programming process since the speed for information storage is more important.

Demonstration of multi-mode and multi-level storage functions

Taking advantage of the FE material, where the external voltage bias can control the induced P_r with partial switching capability, our non-volatile photonic-electronic memory is able to realize multi-level storage in a simple manner. By applying different programming voltages, the maximum achievable peak wavelength differences and ERs can be controlled by the induced P_r. Multi-level storage, as well as the mixed-mode operation, are proved to be feasible here, with details shown in Fig. 3. The measurement circuit design is shown in Fig. 3a, where optical/electrical programming/erasing/reading functions are equipped. To induce the FE switching and programming/erasing the memory cell, it is crucial to create enough DC bias on the FE capacitor. Here in the circuit, a bias tee is used to deliver the DC voltage from the voltage input (DC port of bias tee) to the device (RF + DC port of bias tee). The DC voltage for programming/erasing can be generated either optically or electrically: (a) Optical programming/erasing is realized by two constant reverse-biased PDs, while two electrically controlled EVOAs are used to tune the optical power intensity on these two PDs. Noted that fiber-coupled PDs on separated chips are used in the proof of principle experiment. The output photocurrents from the PDs flow through a pull-up resistor, which can create DC voltages at the DC port of the bias tee. The constant positive/negative DC bias being delivered to the input of the bias tee is therefore related to the optical power on the PDs. (b) Electrical programming/erasing is realized by a voltage source that directly produces the DC voltage into the bias tee, while in the meantime, both PDs are kept in the off state by turning off the optical power using EVOA. After optical/electrical erasing/programming, our memory can be read out both optically and electrically at the same time: (a) Optical readout is conducted by having a tunable laser input aligned with a resonant peak and measuring the output power using an optical power meter, where different storage states result in different optical power outputs. (b) Electrical readout relies on sensing the capacitance using a small signal input at the RF port of the bias tee. The small signal is generated by a signal generator with a frequency of 100 kHz and a magnitude of 50 mV. The impedance of the ITO/FE/Si capacitor is changed along with the FE switching and can then be read out by the magnitude of the small signal. These working principles of optical/electrical programming/erasing/reading guide the following testing. Note that a small AC signal introduces a negligible difference in the optical reading considering an averaged power reading time of more than 10 µs. Thus, the optical reading and electrical reading can be simultaneously realized.

Multi-level storage was first demonstrated by optical reading after electrically/optically programming/erasing, as shown in Fig. 3b. The memory cell was erased by a + 4.5 V pulse before being programmed by negative voltages ranging from − 0.1 V to -4.5 V, and read under a reading voltage of 1 V. The length of the pulse is long enough to ensure the switching of the FE layer between each state. These voltage pulses for programming/erasing are generated either electrically or optically. Considering the noise and drift of the system, three states are available for this device using different programming voltages of -0.1 V, -2.1 V, and − 3.1 V, which correspond to non-switched, partially switched, and fully switched FE states, respectively. Raw data points repeating 10 times for these three states are shown in Fig. 3c, and the distribution is shown in Fig. 3d, from which we can calculate the raw bit-error-rate (RBER)⁴⁷ between each consecutive state, which is not larger than 8.8×10^− 3.

It should be noted that in the prototype of the device, we are unable to perform electrical readings directly on our memory cell. As shown in the microscopic image of the fabricated device of Fig. 1c, the ITO/HAO/Si stack covers not only the waveguide region but also a large portion of the Si slab. The electrical signal of FE switching is therefore buried by the noise owing to the responses of interface traps between the ITO/HAO gate stack and the Si slab^48,49. Interface traps are mainly aroused from the plasma etching step of the waveguide, while the waveguide itself is unetched because it is covered by the photoresist in the plasma etching step. So, optical readings are conducted successfully because the surface of the waveguide is etch-free and guarantees a low interface trap density, which preserves all the non-volatile modulation effects resulting from the FE switching on the waveguide.

As a result, electrical reading was performed on an FE capacitor with the same ITO/HAO stack and fabrication process to examine the electrical reading function of the designed circuit. The FE capacitor was erased by + 4.5 V and then programmed by negative voltages ranging from − 0.1 V to -4.5 V. The readout is measured from frequency domain output at 100 kHz in Fig. 3e, showing two states corresponding to non-switched and fully switched FE states. An RBER of 1.17×10^− 8 between the two states was calculated, as illustrated in Fig. 3f and 3g. Apart from this simple circuit for electrical reading, other methods have been reported on the FE capacitor reading in either a destructive way⁵⁰ or a non-destructive way⁴⁶ with better accuracy.

These RBERs all meet the requirements for utilizing low-density parity check (LDPC) error correction coding and can be smoothly lowered to less than 10^− 12 by LDPC coding^51,52. Besides the multi-level storage and mixed-mode operation, the simplicity of our multi-level storage realization, in which no pulse engineering is required, is another significant improvement over other implementations of non-volatile photonic-electronic memory. The memory driving system design can therefore benefit from the simplicity of the driving strategy of our memory cell.

To verify the non-volatile property as well as the reliability of our memory cell, retention, and endurance tests are conducted, as depicted in Fig. 4. In the inset of Fig. 4a, the memory cell was erased and programmed by ± 5 V pulses and read under a biasing voltage of 1 V after a time duration ranging from 1 s to 1000 s at room temperature. No obvious degradation was observed. The retention tests here show the non-volatility of our memory cells. The endurance tests were conducted on a dummy FE capacitor which excludes all the parasitic capacitance in our device. As shown in Fig. 4b, a square pulse train with a cycling frequency of 5 kHz was used to ensure effective electrical stressing and switching of the FE capacitor. The electrical field amplitudes were set to be 4 and 5 MV/cm, corresponding to the operating voltages of our memory cell. The endurance of our HAO thin film increases with a decreasing E-field. A minimum endurance of 4×10⁴ cycles at 5 V operation voltage and 1×10⁶ cycles at 4 V is obtained. This can be improved by interface engineering between Si and HAO layers^53–55.

In our memory cell, the ERs are largely dependent on the Q-factors of the optical ring resonator, while the Q-factors are related to the loss of the waveguide. Waveguide loss is strongly related to the lithography and plasma etching step, which have not been fully optimized in this work. Much better results can be expected if the process in commercialized foundries is utilized with waveguide loss of less than 1 dB/cm. Understanding the additional loss caused by the ITO/HAO gate stack is more important here. Measurements were conducted on the Si rib waveguide with ITO/HAO stack on it, as depicted in the inset of Fig. 5. The additional loss of ITO/HAO stack per transmission length was tested and calculated by subtracting the loss of the bare Si rib waveguide. In Fig. 5, additional loss for ITO/HAO is measured to be 0.018 dB µm^− 1, which shows the transparency of our ITO thin film at telecommunication wavelength. In our device, the ITO/HAO covers about 70 µm length on the ring region, corresponding to an acceptable optical loss of around 1.26 dB for this application. A trade-off has to be made here between the conductivity and the transparency of the ITO thin film. A better conductivity results in a more severe photon absorption in the ITO film, degrading the Q-factors of the optical ring resonator and ERs of the memory cell. By lowering the carrier concentration of the ITO thin film in the deposition process, the transparency enhances, but higher parasitic resistance of the ITO/HAO/Si MIS capacitor would degrade its high-speed performance. A possible solution is to reduce the thickness of ITO thin film while keeping its conductivity using the post-annealing process after ITO deposition⁵⁶. Other transparent electrodes can also be used, such as ZnO⁵⁷ and CdO⁵⁸.

In principle, our memory cell can operate in the mixed-mode, including optical/electrical programming/erasing/reading, while electrical reading has not been realized. The realization of electrical reading depends strongly on the post-surface conditioning after plasma etching and reducing the parasitic capacitance, where both steps aim at reducing the trap density and increasing the signal-to-noise ratio of the readout signal. The stored state of the FE capacitor can be read out by both the circuit in Fig. 3a and other techniques^46,50, which shows the feasibility of electrical reading from the FE capacitor.

In the current proof of principle stage, the full single-chip integration of resistors, PDs, and bias tee, is not achieved, which might bring in noise and loss in the measurement process. On-chip components are necessary to improve overall performance. Actually, on-chip waveguide-coupled PDs^59–61, on-chip resistors, and on-chip bias tee⁶², have already been reported, which can show the possible complete integration between the devices and peripheral circuits in future hybrid electronic-photonic systems⁶³.

In conclusion, we have reported here a non-volatile programmable photonic-electronic memory cell with multi-level storage and mixed-mode operation functionalities, enabled by the employment of an Al-doped HfO₂ ferroelectric layer with low operating voltage and a transparent ITO electrode with low optical absorption on top of the silicon waveguide. In our demonstration, the information is stored optically/electrically induced by the remnant polarization of HAO and can be read out optically by the optical power meter. We achieve one of the highest ERs of 6.6 dB at a 5 V operation voltage, with an endurance of 4×10⁴ cycles and a retention of more than 10 years. Furthermore, the comprehensive retention and endurance testing results guarantee the reliability of the memory cell. This work shows the considerable potential of ferroelectric photonic devices for future hybrid electronic-photonic platforms, such as photonic interconnect, optical neuromorphic computing, data center, and optical communication applications, where non-volatile photonics are indispensable.

Device fabrication process flow

The ring resonator and the grating coupler were patterned using the Raith EBPG-5200 electron beam lithography system and etched by Oxford PlasmaPro 100 Cobra ICP RIE etching system using CHF₃/O₂/Ar on an SOI wafer. 250 nm SiO₂ was then deposited by Oxford PlasmaPro 100 PECVD as the cladding layer, followed by the opening of an operational window directly on the ring resonator region using dry etching. After that, 10 nm HAO was deposited using Picosun ALD at 300 ℃. The doping concentration of aluminum is 1:30 controlled by the cycle ratio of Al and Hf. Tungsten was deposited by Sputtering System - AJA UHV as the top electrode. Rapid thermal annealing was performed by the RTP system from Annealsys. After that, Tungsten top electrode was replaced by ITO top electrode deposited using RF-sputtering by Sputtering System - AJA UHV. Finally, the bottom electrode Ni was deposited by the ebeam evaporation system E-Beam Evaporator - AJA UHV. Detail flow charts and TEM figures can be found in supplementary materials Fig. S1.

Measurement setup for the mixed mode operations

For the optical programming/erasing function, the output from a C-band EDFA (Fiberprime) is split into two paths and followed by 2 EVOAs (Thorlabs) to control the optical power. InGaAs fiber pigtailed PDs (Beijing Lightsensing) are used to convert the optical power to DC voltages and then applied to the FE memory cell through a bias tee (Marki Microwave). For electrical programming/erasing function, the DC voltages are generated by a source measurement unit (Keysight U2722A). For the optical reading function, the input is a tunable laser (Agilent 81949A), while the output power is measured by an optical power meter (Thorlabs PM100D). For electrical reading, the small signal is generated by an arbitrary waveform generator (Keysight 33500B) and read by using an oscilloscope (LeCroy WavePro). A visible laser (Thorlabs) with 520 nm wavelength and about 5 mW power is used to help the FE switching. All the optical spectra and peak shifts are measured by an optical spectrum analyser (Yokogawa AQ6370B).

Acknowledgements

This research is supported by the National Research Foundation (NRF) Singapore, under its Quantum Engineering Programme 1.0 projects (QEP-P3) and MOE Tier 1 (A-8001168-00-00).

Author contributions

G.Z., Y.C., and X.G. jointly conceived the idea. G.Z. and Y.C. designed and fabricated the device and performed the measurements. Y.C, G.Z, J.S.Z., and H.B.W. conducted the experiments. Z.J.Z., Z.P.Z., L.M.J., C.S., Q.W.K., R.S., K.N., J.X.W, J.Z.C. and J.R.Z. assisted with the theory. All authors contributed to the discussion of experimental results. X.G. supervised and coordinated all the work. Y.C., G.Z., and X.G. wrote the manuscript with contributions from all co-authors.

Wetzstein, G. et al. Inference in artificial intelligence with deep optics and photonics. Nature 588, 39–47 (2020).
Zangeneh-Nejad, F., Sounas, D. L., Alù, A. & Fleury, R. Analogue computing with metamaterials. Nat. Rev. Mater. 6, 207–225 (2021).
Marković, D., Mizrahi, A., Querlioz, D. & Grollier, J. Physics for neuromorphic computing. Nat. Rev. Phys. 2, 499–510 (2020).
Chen, Z. & Segev, M. Highlighting photonics: looking into the next decade. eLight 1, 2 (2021).
Zhao, W. et al. High-Performance Mode-Multiplexing Device with Anisotropic Lithium-Niobate-on-Insulator Waveguides. Laser Photonics Rev. 17, 2200774 (2023).
Goi, E., Zhang, Q., Chen, X., Luan, H. & Gu, M. Perspective on photonic memristive neuromorphic computing. PhotoniX 1, 1-26 (2020).
Gao, J. et al. Quantum advantage with membosonsampling. Chip 1, 100007 (2022).
Atabaki, A. H. et al. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature 556, 349–354 (2018).
Sun, C. et al. Single-chip microprocessor that communicates directly using light. Nature 528, 534–538 (2015).
Shastri, B. J. et al. Photonics for artificial intelligence and neuromorphic computing. Nat. Photonics 15, 102–114 (2021).
De Lima, T. F. et al. Machine learning with neuromorphic photonics. J. Light. Technol. 37, 1515–1534 (2019).
Tait, A. N. et al. Demonstration of Multivariate Photonics: Blind Dimensionality Reduction With Integrated Photonics. J. Light. Technol. 37, 5996–6006 (2019).
Huang, C. et al. A silicon photonic–electronic neural network for fibre nonlinearity compensation. Nat. Electron. 4, 837–844 (2021).
Zhang, S. et al. Field and lab experimental demonstration of nonlinear impairment compensation using neural networks. Nat. Commun. 10, 3033 (2019).
Xu, X. et al. 11 TOPS photonic convolutional accelerator for optical neural networks. Nature 589, 44–51 (2021).
Zhang, H. et al. An optical neural chip for implementing complex-valued neural network. Nat. Commun. 12, 457 (2021).
Shao, R., Zhang, G. & Gong, X. Generalized robust training scheme using genetic algorithm for optical neural networks with imprecise components. Photonics Res. 10, 1868–1876 (2022).
O’brien, J. L. Optical quantum computing. Science 318, 1567–1570 (2007).
Takeda, S. & Furusawa, A. Toward large-scale fault-tolerant universal photonic quantum computing. APL Photonics 4, 060902 (2019).
Li, X. et al. Fast and reliable storage using a 5 bit, nonvolatile photonic memory cell. Optica 6, 1-6 (2019).
Ríos, C. et al. Integrated all-photonic non-volatile multi-level memory. Nat. Photonics 9, 725–732 (2015).
Zheng, J. et al. GST-on-silicon hybrid nanophotonic integrated circuits: a non-volatile quasi-continuously reprogrammable platform. Opt. Mater. Express 8, 1551-1561 (2018).
Wuttig, M., Bhaskaran, H. & Taubner, T. Phase-change materials for non-volatile photonic applications. Nat. Photonics 11, 465–476 (2017).
Delaney, M. et al. Nonvolatile programmable silicon photonics using an ultralow-loss Sb₂Se₃ phase change material. Sci. Adv. 7, eabg3500 (2021).
Lu, Y. et al. Mixed-Mode Operation of Hybrid Phase-Change Nanophotonic Circuits. Nano Lett. 17, 150–155 (2017).
Farmakidis, N. et al. Plasmonic nanogap enhanced phase-change devices with dual electrical-optical functionality. Sci. Adv. 5, eaaw2687 (2019).
Ielmini, D., Lavizzari, S., Sharma, D. & Lacaita, A. L. Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation. in 2007 IEEE International Electron Devices Meeting (IEDM) 939–942 (IEEE, 2007).
Zhang, W. & Ma, E. Unveiling the structural origin to control resistance drift in phase-change memory materials. Mater. Today 41, 156–176 (2020).
Pirovano, A. et al. Scaling analysis of phase-change memory technology. in 2003 IEEE International Electron Devices Meeting (IEDM) 29–6 (IEEE, 2003).
Cai, K. Vertical constrained coding for phase-change memory with thermal crosstalk. in 2014 International Conference on Computing, Networking and Communications (ICNC) 312–316 (IEEE, 2014).
Song, J.-F. et al. Integrated photonics with programmable non-volatile memory. Sci. Rep. 6, 22616 (2016).
Grajower, M., Mazurski, N., Shappir, J. & Levy, U. Non-Volatile Silicon Photonics Using Nanoscale Flash Memory Technology. Laser Photonics Rev. 12, 1700190 (2018).
Aritome, S., Shirota, R., Hemink, G., Endoh, T. & Masuoka, F. Reliability issues of flash memory cells. Proc. IEEE 81, 776–788 (1993).
Lee, J.-D., Choi, J.-H., Park, D. & Kim, K. Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells. IEEE Trans. Device Mater. Reliab. 4, 110–117 (2004).
Emboras, A. et al. Nanoscale Plasmonic Memristor with Optical Readout Functionality. Nano Lett. 13, 6151–6155 (2013).
Abbas, H., Li, J. & Ang, D. S. Conductive Bridge Random Access Memory (CBRAM): Challenges and Opportunities for Memory and Neuromorphic Computing Applications. Micromachines 13, 725 (2022).
Tan, A. J. et al. Experimental demonstration of a ferroelectric HfO₂-based content addressable memory cell. IEEE Electron Device Lett. 41, 240–243 (2019).
Si, M. et al. Ferroelectric polarization switching of hafnium zirconium oxide in a ferroelectric/dielectric stack. ACS Appl. Electron. Mater. 1, 745-751 (2019).
Müller, J. et al. Ferroelectric Zr_0.5Hf_0.5O₂ thin films for nonvolatile memory applications. Appl. Phys. Lett. 99, 112901 (2011).
Zhou, Z. et al. A Metal-Insulator-Semiconductor Non-Volatile Programmable Capacitor Based on a HfAlOₓ Ferroelectric Film. IEEE Electron Device Lett. 41, 1837–1840 (2020).
Kim, K. & Lee, S. Memory technology in the future. Microelectron. Eng. 84, 1976–1981 (2007).
Udayakumar, K. et al. Manufacturable high-density 8 mbit one transistor–one capacitor embedded ferroelectric random access memory. Jpn. J. Appl. Phys. 47, 2710 (2008).
Okuno, J. et al. SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf_0.5Zr_0.5O₂. in 2020 IEEE Symposium on VLSI Technology (VLSI Technology and Circuits) 1–2 (IEEE, 2020).
Francois, T. et al. Demonstration of BEOL-compatible ferroelectric Hf_0.5Zr_0.5O₂ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications. in 2019 IEEE International Electron Devices Meeting (IEDM) 15.7.1-15.7.4 (IEEE, 2019).
Bogaerts, W. et al. Silicon microring resonators. Laser Photonics Rev. 6, 47–73 (2012).
Zhou, Z. et al. Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High C_HCS/C_LCS, Fast Speed, and Long Retention. in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 357–358 (IEEE, 2022).
Freude, W. et al. Quality metrics for optical signals: Eye diagram, Q-factor, OSNR, EVM and BER. in 2012 14th International Conference on Transparent Optical Networks (ICTON) 1–4 (IEEE, 2012).
Ni, K. et al. Critical role of interlayer in Hf_0.5Zr_0.5O₂ ferroelectric FET nonvolatile memory performance. IEEE Trans. Electron Devices 65, 2461–2469 (2018).
Zhao, G. et al. Suppressing Interfacial Layer Degradation in Hf_0.5Zr_0.5O₂-based FeFETs Using a Pre-erase Strategy during Program/Erase Cycling. in 2022 IEEE Silicon Nanoelectronics Workshop (SNW) 1-2 (IEEE, 2022).
Wu, J. et al. Monolithic integration of oxide semiconductor FET and ferroelectric capacitor enabled by Sn-doped InGaZnO for 3-D embedded RAM application. IEEE Trans. Electron Devices 68, 6617–6622 (2021).
Richardson, T. J., Shokrollahi, M. A. & Urbanke, R. L. Design of capacity-approaching irregular low-density parity-check codes. IEEE Trans. Inf. Theory 47, 619–637 (2001).
Djordjevic, I. B., Cvijetic, M., Xu, L. & Wang, T. Using LDPC-coded modulation and coherent detection for ultra highspeed optical transmission. J. Light. Technol. 25, 3619–3625 (2007).
Zhou, J. et al. Demonstration of ferroelectricity in Al-doped HfO₂ with a low thermal budget of 500° C. IEEE Electron Device Lett. 41, 1130–1133 (2020).
Cao, R. et al. Improvement of endurance in HZO-based ferroelectric capacitor using Ru electrode. IEEE Electron Device Lett. 40, 1744–1747 (2019).
Chernikova, A. G. et al. Improved ferroelectric switching endurance of La-doped Hf_0.5Zr_0.5O₂ thin films. ACS Appl. Mater. Interfaces 10, 2701–2708 (2018).
Li, E., Nia, B. A., Zhou, B. & Wang, A. X. Transparent conductive oxide-gated silicon microring with extreme resonance wavelength tunability. Photonics Res. 7, 473 (2019).
Li, X. et al. A study on the evolution of dielectric function of ZnO thin films with decreasing film thickness. J. Appl. Phys. 115, 103512 (2014).
Campione, S. et al. Submicrometer epsilon-near-zero electroabsorption modulators enabled by high-mobility cadmium oxide. IEEE Photonics J. 9, 1–7 (2017).
Wang, H. et al. High-speed and high-responsivity pin waveguide photodetector at a 2 μm wavelength with a Ge_0.92Sn_0.08/Ge multiple-quantum-well active layer. Opt. Lett. 46, 2099–2102 (2021).
Liu. J, et al. Design of monolithically integrated GeSi electro-absorption modulators and photodetectors on an SOI platform. Opt.Express 15, 623–628 (2007).
Hou. X, et al. Waveguide-coupled superconducting nanowire single-photon detectors based on femtosecond laser direct writing. Opt.Express 29, 7746–7756 (2021).
Hettrich, H. & Möller, M. Linear low-power 13GHz SiGe-Bipolar modulator driver with 7 Vpp differential output voltage swing and on-chip bias tee. in 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) 80–83 (IEEE, 2014).
Corbett, B., Loi, R., Zhou, W., Liu, D., & Ma, Z. Transfer print techniques for heterogeneous integration of photonic components. Prog. Quantum Electron. 52, 1-17 (2017).

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Thin film ferroelectric photonic-electronic memory

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Abstract

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Introduction

Results

Design of non-volatile photonic-electronic memory cell

Non-volatile photonic-electronic memory cell performance

Demonstration of multi-mode and multi-level storage functions

Discussion

Methods

Device fabrication process flow

Measurement setup for the mixed mode operations

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References

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