Ag nanoparticles capped TiO2 nanowires array based capacitive memory

Glancing angle deposition technique was used to fabricate Ag nanoparticles (NPs) capped TiO2 Nanowire (NW) array structure for capacitive memory application. Electron microscopes confirmed the sandwiched structure of Ag NPs between TiO2 thin-film (TF) and NW. The average length of the vertical TiO2 NW and diameter of Ag NPs (with density ~ 1012 cm2) were found to be ~ 350 ± 5 nm and ~ 3.2 ± 0.4 nm, respectively. An enhanced photoluminescence was observed in case of Ag NPs capped TiO2 NWs due to the presence of high carriers as compared to bare TiO2 NW. The capacitance (C)–voltage (V) hysteresis was measured for both Ag NPs capped TiO2 NW and bare TiO2 NW at different sweeping voltage (± 3– ± 10 V) at 1 MHz frequency. A high capacitive memory window of 7.12 V was obtained for Ag NP capped TiO2 NW at ± 10 V with an excellent endurance upto 1000 cycle. Significantly lesser charge loss of 23% was obtained after a span of 104 s with a hole and electron loss of 10.6% and 17.8% respectively. The program and erase process in the device was explained with the help of a band diagram.


Introduction
Recently metal nanoparticle (NP) (Ag, Au etc.) based non-volatile memory (NVM) have drawn much attention because of their ability of showing high non-volatile characteristics in terms of higher retention [1], endurance and scalability [2]. Among the novel metal, Ag is suitable material for NP decoration due to its control growth, high thermal stability and cost-effectiveness [3]. Interestingly, Ag with metal oxide can enhance the charge storage capability by creating Schottky contact with metal oxide i.e. TiO 2 , ZnO etc., [2]. L. Tang et al., reported that Ag NP with carbon nano tube (CNT) enhanced the capacitance with better cycle stability [4]. However Ag nanoparticles easily form oxide as compared to Au which may further lead to enhancement in Schottky barrier potential (0.3 eV) between Ag and metal oxide as reported by T. Tachikawa et al., [5]. Among the metal oxide semiconductors, TiO 2 is known as a High-K dielectric (* 80) material, which allows higher scaling down of the effective oxide thickness (EOT) while increasing the performance of the device [6]. Also, high-k dielectric materials are used as a blocking oxide layer which improve capacitance with lower EOT and lower programming/erase voltage [6].
However, the leakage current has to be controlled as demonstrated by Dhar et al., [7] on using glancing angle deposition (GLAD) technique to synthesize TiO 2 nanowire (NW) based superior MOS capacitor with a very low leakage current by increasing the offset values [6]. Moreover, TiO 2 also shows great stability [8,9] and high performance as NVM application in comparison to other reported metal oxide NVM devices. I. Salaoru et al., have demonstrated capacitive memory using TiO 2 , but significant improvement is required in terms of good retention and better memory window [10]. It is also reported that Ag NP based capacitive memory with the NPs density ranges between * 10 11 and 10 12 cm -2 can efficiently increase the charge storage capability [11], but to control its deposition is not an easy task. A. Ganguly et al., have already demonstrated the controlled growth of Ag NP decoration over TiO 2 using GLAD technique [12]. Mondal et al., also reported that Ag decorated TiO 2 thin-film (TF) enhanced the capacitive memory as compare to bare TiO 2 TF [13]. Similarly, enhanced memory window using metal NPs decorated high-k dielectric based capacitive memory was also reported [14,15] but all of the above memory needs a significant improvement.
In this paper, the authors have demonstrated how a simple modification at the tip of TiO 2 NW by depositing Ag NPs can significantly improve its charge retention capability. The Ag NPs were deposited over the TiO 2 NWs using a simple, wellcontrolled and cost effective technique called GLAD. The Ag NPs capped TiO 2 NW showed a very high memory window with good retention of over 10 4 s and excellent endurance characteristics. However, no reports are so far available on the demonstration of charge trapping structure for capacitive memory applications using TiO 2 /Ag NPs decorated over the tip of TiO 2 NW which can further enhance the NVM performance. This novel structure with Ag NP sandwiched in between TiO 2 NW and TF can significantly introduce intermediate states in between TiO 2 creating charge trapping centers and inject higher charges which can improve the NVM characteristics.
2 Experimental details 2.1 Synthesis GLAD technique was incorporated inside the e-beam chamber (BC-300, HHV INDIA) to fabricate Ag NPs capped TiO 2 NWs over p-type Si substrate. A pictorial representation of the different fabrication process steps along with the GLAD technique are depicted in Fig. 1 The Si substrates were RCA cleaned, dried, and placed inside the e-beam chamber prior to the start of the deposition process. At first, TiO 2 TF of thickness 80 nm was deposited over Si substrate. The deposition was carried out by evaporating high purity TiO 2 source materials (99.999% pure, MTI, USA). The substrates were placed at a distance of 24 cm away from the source material. Then, TiO 2 NW of length 350 nm and diameter of 70 nm was fabricated over TiO 2 TF for which the substrate was kept at an oblique angle of 85°with respect to the source. TiO 2 NW diameter of 70 nm was chosen in order to grow Ag NPs with size (3 nm) over its tip with case having density in the range 10 11 -10 12 cm -2 . The substrate was also azimuthally rotated at a constant speed of 20 rpm (The GLAD technique is shown in Fig. 1c).
Thereafter, Ag NPs (* 3 nm) were deposited over the tip of TiO 2 NWs using the same GLAD configuration i.e., the same substrate rotation and orientation as used for TiO 2 NWs. Afterwards, at the top of Ag NPs, TiO 2 TF of thickness * 120 nm was also deposited to form TiO 2 TF/Ag-NP/TiO 2 NW sandwiched structure. All the above depositions were carried out at a base pressure of 5 9 10 -6 mbar with a constant growth rate of 0.12 nm/sec which was monitored by a quartz crystal installed inside the chamber. Later, Ag electrode of thickness 30 nm (area 1.13 9 10 -6 m 2 ) was evaporated over the TiO 2 TF to fabricate memory device. The device schematic is shown in Fig. 1. Another memory device without Ag NPs was also prepared in order to compare the impact of Ag NPs over the TiO 2 NWs.

Characterization
The morphology and structure of the Ag NPs capped TiO 2 NW was studied using the field emission scanning electron microscope (FE-SEM) (Zeiss/Ultra 55) and transmission electron microscopy (TEM) (JEM 2100, JEOL) analysis. The optical characteristics were recorded using ultraviolet-visible spectroscope (UV-Vis) (HITACHI UH4150) and photoluminescence spectroscopy (PL) (HITACHI, F-7000FL) by measuring the C-V characteristics (Keithley 4200-SCS). Figure 2a shows the cross-sectional FESEM image of the TiO 2 TF/Ag NPs capped TiO 2 NWs/Si structure where each layers are marked accordingly. It can be seen that the TiO 2 TF of thickness * 80 nm is grown over the Si substrate on top of which the TiO 2 NWs are deposited. These TiO 2 NWs are perpendicularly oriented with average length of * 350 ± 5 nm. Ag NPs were then fabricated above the TiO 2 NWs, which are not visible in the FE-SEM image. As these Ag NPs decorated over the tip of TiO 2 NWs were very small in dimensions (* 3 nm), they were completely enveloped by the TiO 2 TF (thickness * 120 nm) fabricated over the top of Ag NPs. Some under grown TiO 2 NWs are also visible in the FE-SEM image, which can be attributed to the competitive growth mode process that prevails in the fabrication (GLAD) technique [16]. The EDS spectrum (Fig. 2b) shows the emission form silicon (Si) K shell, titanium (Ti) K shell, oxygen (O 2 ) K shell and silver (Ag) K shell which designates the presence of Ti, O, Si and Ag elements in the fabricated sample. Figure 2b inset also shows the chemical mapping of the fabricated sample. Figure 3a shows the TEM image that was examined on the Ag NPs capped TiO 2 single NW in order to determine the dimension of the NPs and the morphology of the grown NWs. The direction of the arrow shows the growth direction of the NW and also the length of the NW is calculated to be * 490 nm. The diameter of the NW is found to be 70 nm at the top and 40 nm at the bottom. The selected area electron diffraction (SAED) pattern of the NW shows that the grown NW is amorphous in nature (Fig. 3a). The maximized image (Fig. 3a) of the tip of the TiO 2 NWs depicts that the size of the sprinkled Ag NPs were non-uniform in nature, which may be due to the shadowing effect by GLAD technique. The average diameter of the Ag NP was measured to be * 3.2 ± 0.4 nm. The TEM also verifies that the NPs didn't cover the entire portion of the NWs except the tip, which was due to the shadowing effect of the GLAD technique. The pictorial representation of the shadowing mechanism is shown in Fig. 3b. The incoming vapor fluxes create a shadow (dark zone in Fig. 3b) where the fluxes cannot arrive due to the placement of oblique angle of the substrate (85°) with respect to the source. Therefore, the incoming Ag fluxes from the source could not get deposited around entire surface of the TiO 2 NW. The NP density in each NW is calculated to be 10 12 cm -2 . Figure 4a show the PL spectrum of both the Ag NPs capped TiO 2 NWs and bare TiO 2 NWs sample. The data were recorded at room temperature using a xenon lamp with an excitation wavelength of 250 nm. A higher intense PL peak was observed in the case of Ag NPs capped TiO 2 NW as compared to bare TiO 2 NW. Ag NPs capped TiO 2 NWs sample exhibit PL peak at 360 nm (3.44 eV) and 466 nm (2.67 eV). Whereas, PL emission peak for bare TiO 2 NW were found at 344 nm (3.6 eV) and 466 nm (2.67 eV). The primary PL emission peak was found at 3.6 eV for bare TiO 2 NW. This may be attributed to the direct bandgap of TiO 2 [16]. In case of Ag NPs capped TiO 2 NW the high energy PL emission peak was found at 3.44 eV, which was slightly lower than the main band emission of TiO 2 . This may be due to the presence of localized states in TiO 2 after the incorporation of Ag NPs. Moreover, PL emission peak at 466 nm was found for both the samples due to the radiative recombination on TiO 2 localized state [17] with higher intensity for Ag capped sample due to the additional electron-hole pair generation after incorporation of Ag NP. In order to understand this shifting of primary PL peak, tauc plot was done from the absorption measurement analysis. Figure 4b  band gap of the sample. The bandgap of the Ag NPs capped TiO 2 NWs and bare TiO 2 NWs samples were found to be 3.4 eV and 3.6 eV respectively. The obtained band gap of TiO 2 is in good agreement to the previously reported literature [16]. Interestingly, Ag NPs capped TiO 2 NW sample showed a small red shift of 0.2 eV compared with the bare TiO 2 NW sample. Ag NPs can introduce some localized energy states [18] in the band gap of TiO 2 which may give rise to absorption at lower energy and as such may reduce the band gap. Therefore, the excited photocarriers recombine radiatively to these mid energy states and as a result a shift in PL was observed. Moreover, the higher carriers supplied from the Ag level to the TiO 2 conduction level significantly increased the PL intensity. Figure 5a show the C-V characteristics of Ag capped TiO 2 NW and bare TiO 2 NW device. The experimental study was carried out at room temperature at varying frequency of 10 K, 50 K, 100 K, 500 K, and 1 M with applied sweeping voltage range from -10 to ? 10 V. In Fig. 5a, the capacitance for both the devices increases significantly with decrease in frequency under ± 10 V applied bias. Similar characteristics of increase in capacitance with decreasing frequency were also observed by the authors [19]. Several parameters together including the series resistance, the inhomogeneous layer of semiconductor-dielectric (p-Si/TiO 2 ) interface defect states [20] etc. play a significant role in such observed characteristics. The accumulation capacitance was found to be 18 pF and 13 pF for Ag NPs capped TiO 2 NWs and bare TiO 2 NWs respectively at 1 MHz frequency. Ag NPs capped TiO 2 NW (Fig. 5a) shows high accumulation capacitance as compared to bare TiO 2 NW (Fig. 5a inset) device due to multi-layer charge trapping structure. The interface between TiO 2 -Ag-TiO 2 acts as charge trapping layers due to incorporation of intermediate states and also the higher carriers injected after the incorporation of Ag contributes to the higher capacitance. Figure 5b shows the conductance versus voltage characteristics of Ag NPs capped TiO 2 NW and bare TiO 2 NW device (inset) at different voltage frequency. Ag NPs capped TiO 2 NW device shows lesser conductance value of 1.39 9 10 -4 f compare with the 2.34 9 10 -4 f for bare TiO 2 NW device under 1 MHz voltage (± 10 V) frequency. This may be attributed due to the high resistive carrier movement as a consequence of the charge trapping at the TiO 2 -Ag-TiO 2 interface [13]. Figure 6a, b show the high frequency (1 MHz) C-V characteristics of the Ag NPs capped TiO 2 NW and bare TiO 2 NW based memory device respectively. The C-V hysteresis characteristics was measured by double sweeping the voltage from negative to positive and then from positive to negative. The C-V curve for Ag NPs capped TiO 2 NWs Fig. 6a display a significant counter clock-wise hysteresis with increase in the sweep voltage (from ± 3 to ± 10 V), indicating the strong charge storage capability of the device. The nature of the graph as obtained in our case is similar to other memory devices reported for TiO 2 [20]. Uncapped TiO 2 NW (Fig. 6b) shows almost a constant counter clock-wise hysteresis with increase in sweep voltage, which signifies that the charge storage/trapping capability is lacking in this case. Moreover, double hysteresis was observed for both the devices which may be due to the higher interface traps between TiO 2 and Si [21]. The flat band voltage shift (DV) was measured for both the positive and negative sweep for both the devices. The positive flat band voltage shift [(DV) electron] and negative flat band voltage shift [(DV) hole] for the Ag NPs capped TiO 2 NW device were calculated to be 0.81 V and 5.06 V respectively between the sweeping voltage of ± 10 V and ± 6 V. Whereas, for the same sweeping voltage, the (DV) electron and the (DV) hole for the bare TiO 2 NW device are calculated to be 0.12 V and -0.05 V respectively. This indicates that higher numbers of holes are trapped with ease in case of Ag NPs capped TiO 2 NWs device. The higher valance band offset between TiO 2 and Si (2.7 eV) as compared to the conduction band offset (0.65 eV) might be a possible reason that electrons can tunnel efficiently. The electron/hole trapping density was calculated for Ag NPs capped TiO 2 NW for the sweeping voltage shift from ± 6 to ± 10 V using the Eq. (1) [6] given below.

Electrical analysis
where, q = electron charge, DV = difference of flatband voltages, C OX = oxide capacitance, and A = device area (1.13 9 10 -6 m 2 ). The electron and hole trapping density was found to be 0.82 9 10 14 m -2 and 5 9 10 14 m -2 respectively. The memory window versus the sweeping voltage is plotted in Fig. 7a which clearly shows that the Ag NPs capped TiO 2 NWs had better window as compared to the bared TiO 2 NW. On increasing the sweeping voltage from ± 3 to ± 10 V the memory window increases from 1.5 to 2 V for TiO 2 NW and 2.5-7.12 V for Ag NPs capped TiO 2 NWs. A maximum window of 7.12 V was observed for Ag NPs capped TiO 2 NW for ± 10 V sweep voltage which was higher than other high-k dielectric memory devices [15] and also better than In doped TiO 2 [20] based memory devices. Moreover, TiO 2 NW is able to obtain a memory window of 2 V at ± 8 V, whereas the same memory window of 2 V is achieved in case of Ag NPs capped TiO 2 NW at a very low sweeping voltage of ± 3.64 V. The higher window in case of Ag NPs capped TiO 2 NWs may be ascribed to the presence of higher number of charges mainly in the Ag NPs and TiO 2 /Ag/TiO 2 interface, which can act as a charge trapping multilayer interface. The band diagram for the Ag NPs NPs capped TiO 2 NW memory device is given in Fig. 7b (inset) showing the charge trapping phenomenon inside the device. For positive voltage sweeping (indicated by the arrow in Fig. 6a), the electrons were injected easily from the substrate and trapped between the Ag and TiO 2 interface which acted as a trapping layer. Moreover, the TiO 2 grown using the GLAD method has already been reported to have higher oxygen vacancies [6] that can act as shallow trap levels introducing higher energy levels within the band gap of TiO 2 . Therefore, with the increase in positive voltage, there was a rise in electron trapping in Ag NPs, which were leaked through these trap levels (trap-assisted tunnelling) and collected at the electrode during the programming process. For negative sweeping, the holes stored in the Ag NPs cannot be flushed out with ease due to the higher valence band offset between the TiO 2 and Si (Fig. 7b). Therefore, with the increase in voltage, higher numbers of holes were trapped and as such higher voltage was required to perform the erasing process. This increases the negative voltage shift and as such the memory increases. Moreover, the higher Ag NPs density can increase the local electric field and also the Coulomb blockade effect for small size NPs [6] which results in such enormous enhancement in memory window. The total charge storage density of both the Ag NPs capped TiO 2 NW and TiO 2 NW device were calculated as 7 9 10 14 m -2 and 1.4 9 10 14 m -2 respectively using Eq. (1) which indicates an obvious higher charge storage in case of Ag NPs capped TiO 2 NW device. Table 1 gives a comparison of the memory window of some recently reported metal oxide memory with our reported result.
Further, the Ag NPs capped TiO 2 NW device was also tested for endurance and retention performance at room temperature. Figure 8a shows the retention characteristics of the Ag NPs capped TiO 2 NW device. After almost 10 4 s (* 2.8 h.) a small loss of 23% in memory window is observed which was calculated by using the equation reported in [25]. The hole loss of 10.6% is lower than the electron loss of 17.8% which can be attributed to the defects which allows for electron tunnelling. Moreover, a 40.8% loss is predicted after a span of 10 years, which is much lesser than other report literature [11]. Figure 8b shows the endurance characteristics of the Ag NPs  capped TiO 2 NW upto 1000 program/erase cycles with respect to the flat band voltage shift. The program and erase voltages were ? 10 V and -10 V respectively. The Ag NPs capped TiO 2 NW device showed an excellent stable endurance characteristic upto 1000 cycles. Therefore, our device showed characteristics which can pave way for designing superior Ag/TiO 2 TF/Ag NP/TiO 2 NW/Si charge trapping structure for NVM application. Further analysis on the impact of size of Ag metal NPs is necessary to understand the exact impact of the size of metal NPs.

Conclusions
Ag NPs was successfully deposited over the tip of the TiO 2 NWs using a controlled and cost-effective GLAD technique. The shadowing effect that prevails in GLAD prevented the Ag NPs to decorate the TiO 2 NWs entirely which was verified using TEM analysis. The Ag NPs introduced some localized energy states in the band gap of TiO 2 , which might have increased both its absorption and PL intensity at lower energy level and also indicating injection of higher number of carriers. A lesser conductance value for Ag NPs capped TiO 2 NW device indicated that charge trapping was occurring at the interface between the Ag and TiO 2 (TiO 2 -Ag-TiO 2 sandwiched structure). As a result of the trapping of charge carriers, a significant enhancement in C-V hysteresis was observed for Ag NPs capped TiO 2 NWs as compared to the bare TiO 2 NW NVM device. The excellent endurance and retention characteristic makes the device structure a suitable candidate for capacitive memory applications.