Design, Analysis, and Simulation of All-optical Optimized and Gate Using Y-shaped Plasmonic Waveguide for High-speed Computing Devices

All - optical logic gates have proven their significance in the digital world using which all high-speed computations are calculated. In this paper, we have proposed a novel structure for all-optical AND using the concept of power combiner using Y-shaped metal-insulator-metal waveguide under the footprints of 4 µ𝑚 × 7 µ𝑚 . This design works under the principle of linear interference. The insertion loss and extinction ratio of the design are given by 0.165 dB and 14.11 dB, respectively. The analysis of the design is carried out by finite-difference-time-domain (FDTD) method and verified using MATLAB. This minimized structure can be used to design any complex logic circuits to achieve better performance in future.


Introduction
The role of communication in the day-to-day life of humans can never be replaced by any other alternative.As technology is advancing, the need for faster communication is also advancing at the same pace.Along with the speed of communication, there are several other factors to be considered while designing a device, like the cost of the individual circuit, size of the device, power handling capacity, heat dissipation issues, and interconnect delays [1].The first generation of electronics is based on semiconductor technology which makes use of vacuum tube-based transistors for logical operations but is less preferred due to its high heat dissipation and interconnects delay [2].These limitations are somewhat mitigated by the next technology called photonics [3][4].In this field, instead of electrons, photons are used to exchange information [5].But the optical devices suffer diffraction limit when the size of the device is closer to the operation wavelength [6].Also, the size of optical components is nearly 1000 times greater than the electronic devices which adds another drawback to it [7].The next generation of technology came with a new proposal called surface plasmons, where the optical signal interacts with the metallic structures at a nano-scale giving a new branch called plasmonic [8][9].It is the combined effect of a miniaturized version of electronics and the capacity of photonics [10].
Section 4 includes a result analysis where the present work is compared with previously reported works and Section 5 gives the conclusion of the proposed design.

Design of AND gate using Y-Combiner
In this paper, the proposed design of AND gate using Y-combiner works on the principle of linear interference [43].The inputs applied to the arms of the power combiner are controlled by an external phase shifter to obtain the desired output of the logical AND gate.The Y-combiner is designed using the S-bend sine waveguide whose equation is defined as where D is the input separation gap between two arms of a combiner, W is the width of the waveguide and L is the length of the S-Bend-shaped waveguide.The waveguide is structured using Eq. 1, as shown in Fig. 1.

Fig. 1: Structure of S-bend sine waveguide
Another waveguide of S-bend shape is arranged symmetrically along the X-axis to obtain the actual Y-combiner.
In this paper, the all-optical AND gate has been designed using the concept of power combiner with the help of a Yshaped waveguide.The design of the Y-combiner is achieved by combining the two symmetrical S-bend structures joined at one end to form a Y-shape structure as shown in Fig. 2.

Fig. 2: Schematic of symmetric Y-combiner
The above structure is designed using the plasmonic waveguide by keeping refractive index as 2.1.The final minimized structure is obtained as a result of altering the parameters of the Y-combiner like S-bend length, Input separation gap, and the length of the linear waveguide.By keeping the input separation gap at 3µm, various parameters like peak output power at ON state, peak output power at OFF state, Y-angle, and the ER are calculated by varying the S-bend length and are tabulated.From Table .1, it is found that the ER is the maximum at S-bend length of 3.9 µm and its value is 13.47 dB.A plot of S-bend length versus ER is shown in Fig. 3.

Fig. 3: Plot of S-bend length versus extinction ratio at D = 3 µm
Similarly, the mentioned parameters are calculated by varying the input separation gap by keeping the S-bend length constant at L = 3.9 µm and the values are mentioned in Table 2.The ER is found to be larger at the linear waveguide length of 2.9 µm which is 14.11 dB, significantly greater than already obtained values.A plot of linear waveguide length versus ER is shown in Fig. 5.

Case 4: when A = 1 and B = 1
In this case, both the input ports of the power combiner are supplied with a high-intensity signal (3 9 W/m).Here the phase difference between the signals is made to 0 0 .According to the principle of Constructive interference, when two signals are having the same amplitude and same phase difference, then the intensity of output signal will be twice the input signal intensity (Y = 1).The optical field propagation for logic '1 and 1' is shown in Fig. 7(c).
All the input combinations along with phase values are shown in Table .6. ), where Pout is the peak output power,Pin is the peak input power.
The Extinction Ratio is defined as Extinction Ratio (ER) = 10 10 where   | is output optical power in ON state,   | is output optical power in OFF state.
The IL and ER of our work are found to be 0.165 dB and 14.11 dB respectively.For better performance of logic gates, the insertion loss should be low and the Extinction ratio should be high as possible [44].This paper work is compared with the previously published works in following parameters as shown in the Table .7.

Conclusion
In this work, an all-optical AND logic gate is designed with the help of a Y-shaped plasmonic MIM waveguide.The design is in the area of 4x7µm 2 which is smaller when compared to the previous works.The key parameters like insertion loss and extinction ratio are calculated.The IL and ER of our work are found to be 0.165 dB and 14.11 dB respectively.
The design parameters like S-bend length, input separation gap, and linear waveguide are optimized to obtain the maximum extinction ratio and to minimize the losses inside the waveguide.Due to simple structure and controllability, the Y-combiner based AND gate can provide a new method to implement logic functions in digital electronics.This design has a minimized structure and is also used in future works to design ultra-compact devices for fast optical computing.
Figures Plot of input separation gap versus extinction ratio at L = 3.9 µm Plot of linear waveguide length versus extinction ratio at L = 3.9 µm and D = 2.6 µm The timing diagram of AND gate using MATLAB Light propagation through proposed AND gate for all combinations of input signals using FDTD method

Fig. 5 :
Fig. 5: Plot of linear waveguide length versus extinction ratio at L = 3.9 µm and D = 2.6 µm The final dimensions of the Y-combiner at which the maximum ER is obtained are depicted in Table.4. 4.

Fig. 6 :Case 2 : when A = 0 and B = 1
Fig. 6: The timing diagram of AND gate using MATLAB

Fig. 7 :
Fig. 7: Light propagation through proposed AND gate for all combinations of input signals using FDTD method Case 3: when A = 1 and B = 0 Unlike the previous case, here the upper arm of the combiner is provided with the high-intensity signal (3 9 W/m) and the lower arm is supplied with the low-intensity signal (1 9 W/m).Thereby due to the similar amplitudes of the input signals and out of phase (180 0 ), again the destructive interference will make the output of AND gate to low (Y = 0).The optical field propagation for logic '1 & 0' is shown in Fig. 7(b).

Table .
1: Extinction ratio values for various S-bend lengths of Y-combiner Sl.No.

Table . 2
: Extinction ratio values for various Input separation gaps at L = 3.9 µm From Table.2, at the value of D = 2.6 µm, the ER is found to be greater than the previously noted value and it is 13.62 dB.A graphical representation of input separation gap versus ER is shown in Fig.4.

Table . 3
: Extinction ratio values for various lengths of linear waveguide

Table . 4
As shown in the truth table of AND gate in Table.6, the output of the AND gate is high when both of the inputs are high, : Design parameters of AND gate using Y-combiner Table.5: Simulation parameters of the AND gate using Y-combiner otherwise, it is low.The timing diagram of AND gate is shown in Fig. 6, is verified using MATLAB; where the two input signals A and B are represented by first and second row and the last row represents the output of logical AND gate.

Table . 6
: Truth table for AND gate along with phase and transmission efficiencyIn this paper, the suggested device is in the footprints of 7 µ × 4µ.The performance parameters like insertion loss and extinction ratio are calculated using the output results.The Insertion Loss is given by

Table . 7
: Comparison of a proposed device with existing one