The design, analysis, and simulation of an optimized all-optical AND gate using a Y-shaped plasmonic waveguide for high-speed computing devices

All-optical logic gates have proven their significance in the digital world for the implementation of high-speed computations. We propose herein a novel structure for an all-optical AND gate using the concept of a power combiner based on a Y-shaped metal–insulator–metal waveguide with a 4 µm × 7 µm footprint. This design works based on the principle of linear interference. The insertion loss and extinction ratio of the design are given as 0.165 and 14.11 dB, respectively. The design is analyzed by using the finite-difference time-domain (FDTD) method and verified using MATLAB. The minimized structure can be used to design any complex logic circuit to achieve better performance in the future.


Introduction
Communication now plays a unique role in everyday human life. As technology advances, the need for faster communication also advances at the same pace. Along with the speed of communication, several other factors must be considered when designing a device, including the cost of the individual circuit, the size of the device, its power handling capacity, heat dissipation issues, and interconnect delays [1]. The first generation of electronics was based on semiconductor technology, making use of vacuum tube-based transistors for logical operations, but suffering from effects such as strong heat dissipation and interconnect delays [2]. These limitations were somewhat mitigated by the next technology, called photonics [3,4]. In this field, instead of electrons, photons are used to exchange information [5]. However, optical devices suffer from the diffraction limit when their size approaches the operating wavelength [6]. Also, the size of optical components is nearly 1000 times larger than electronic devices, which represents another drawback [7]. The next generation of technology came with a new proposal called surface plasmons, where optical signals interact with metallic structures at the nanoscale, resulting in the new field called plasmonic [8,9] that combines the effects of a miniaturized version of electronics with the capacity of photonics [10]. When light of a certain wavelength is incident on a metal surface, free electrons are excited by absorbing the energy from the light but are bound at the interface between the metal and dielectric [11]. These surface plasmon polaritons (SPPs) can avoid the diffraction limit found in photonics [7,[11][12][13][14]. SPPs can confine and control light beyond the diffraction limit, while the losses inside SPPs can be overcome by using different waveguides such as metal-insulator-metal (MIM) [15,16], insulator-metal-insulator (IMI), and dielectric-loaded surface plasmon polariton waveguide (DLSPPW) [14,[17][18][19][20][21][22][23][24]. Among these, the MIM waveguide is best suited because of its capacity to confine light to deep subwavelength [2,16]. Logic gates are the basic building blocks of all digital circuits. Several optical devices such as the directional coupler (DC), Mach-Zehnder interferometer (MZI), power combiners, and power splitters are used to realize different logic gates such as AND, OR, NOT, XOR, and XNOR, as well as universal gates such as NAND and NOR [25][26][27][28][29][30][31][32][45][46][47][48]. These all-optical logic gates can thus be used to design all combinational circuits such as multiplexers, demultiplexers, code converters, adders and subtractors, and parity generators [33][34][35][36][37][38][39][40][41]. In this paper, a minimized design for an all-optical AND gate is proposed based on a power combiner using a Y-shaped waveguide [42] and verified using the FDTD method [43]. Section 2 describes the design of the Y-combiner, followed by the design of the AND gate. Simulation results are presented in Sect. 3. Section 4 includes an analysis of the results, where the present work is also compared with previously reported works, while Sect. 5 provides the conclusions on the proposed design.

The design of the AND gate using a Y-combiner
The proposed design for the AND gate using a Y-combiner operates on the principle of linear interference [42]. The inputs applied to the arms of the power combiner are controlled by an external phase shifter to obtain the desired output of the logical AND gate. The Y-combiner is designed using the S-bend sine waveguide, whose equation is defined as where D is the input separation gap between the two arms of the combiner, W is the width of the waveguide, and L is the length of the S-bend-shaped waveguide. The waveguide is structured using Eq. (1), as shown in Fig. 1.
Another waveguide of the S-bend shape is arranged symmetrically along the X-axis to obtain the Y-combiner.
In this paper, an all-optical AND gate is designed using the concept of a power combiner with the help of a Y-shaped waveguide. The design of the Y-combiner is achieved by combining two symmetrical S-bend structures, joined at one end to form a Y-shaped structure as shown in Fig. 2.
The above structure is designed using a plasmonic waveguide by keeping the refractive index as 2.1. The final minimized structure is obtained as a result of altering the parameters of the Y-combiner such as the S-bend length, the input separation gap, and the length of the linear waveguide.
By keeping the input separation gap at 3 µm, various parameters such as the peak output power in the ON state, the peak output power in the OFF state, the Y-angle, and the extinction ratio (ER) can be calculated when varying the S-bend length, as presented in Table 1. revealing that Fig. 1 The structure of the S-bend sine waveguide  the ER is maximum for an S-bend length of 3.9 µm with a value of 13.47 dB. A plot of the S-bend length versus ER is shown in Fig. 3. Similarly, the mentioned parameters are calculated by varying the input separation gap while keeping the S-bend length constant at L = 3.9 µm, yielding the values presented in Table 2.
From Table 2, at the value of D = 2.6 µm, the ER is found to be greater than the previously noted value, reaching 13.62 dB. A plot of the input separation gap versus the ER is shown in Fig. 4.
The S-bend length and the input separation gap are now kept constant at 3.9 and 2.6 µm, respectively, while the length of the linear waveguide is modified to obtain the maximum extinction ratio. The ER for various lengths of the linear waveguide is presented in Table 3.
The ER is found to be larger for a linear waveguide length of 2.9 µm, reaching 14.11 dB, which is significantly greater      Table 4.

The simulation results for the AND gate using FDTD
The minimized design of the logical AND gate is verified using MATLAB and FDTD simulations. The analysis of the structure is carried out with the help of the FDTD method. A continuous wave of 1550 nm is applied at both input terminals of the Y-combiner. The input optical signals with power of 1 × 10 9 and 3 × 10 9 W/m are considered as the low and high optical intensity signals. The entire simulation is carried out in the transverse electric (TE) mode of the plasmonic waveguide, excited by a source with a Gaussian wave for both inputs. The simulation parameters of the proposed design are presented in Table 5.
As shown in the truth table for the AND gate in Table 6, the output of the AND gate is high when both of the inputs are high; otherwise, it is low. The timing diagram of the AND gate is shown in Fig. 6, as verified using MATLAB, where the two input signals A and B are represented by first and second row while the last row represents the output of the logical AND gate.
Case 1: A = 0 and B = 0 In this case, the two inputs of the Y-combiner are given a low-intensity signal with power 1 × 10 9 W/m. According to the truth table of the AND gate, the output power is low. A phase difference of 180° is created between the two input signals. Since the two input signals have the same amplitude   Fig. 6 The timing diagram of the AND gate obtained using MATLAB and are out of phase, destructive interference will occur and the output of the AND gate is low (Y = 0). Case 2: A = 0 and B = 1 In this case, the upper arm of the combiner is provided with the low-intensity signal ( 1 × 10 9 W/m) while the lower arm of the combiner is given the high-intensity signal ( 3 × 10 9 W/m). A phase shift of 180° is introduced between the two input signals. Similarly, in case of A = 0 and B = 0, destructive interference will occur, which in turn reduces the intensity of the output signal. Hence, the output of the AND gate is low (Y = 0). The optical field propagation for logic "0 & 1" is shown in Fig. 7a.
Case 3: A = 1 and B = 0 Unlike the previous case, here the upper arm of the combiner is provided with the high-intensity signal ( 3 × 10 9 W/m) while the lower arm is supplied with the low-intensity signal ( 1 × 10 9 W/m). Thereby, due to the similar amplitudes of the input signals and out of phase (180°) relation, again destructive interference will occur, making the output of the AND gate be low (Y = 0). The optical field propagation for logic "1 & 0" is shown in Fig. 7b.
Case 4: A = 1 and B = 1 In this case, both input ports of the power combiner are supplied with a high-intensity signal ( 3 × 10 9 W/m). Here, the phase difference between the signals is made to 0°. According to the principle of constructive interference, when two signals have the same amplitude and same phase difference, then the intensity of the output signal will be twice the input signal intensity (Y = 1). The optical field propagation for logic "1 & 1" is shown in Fig. 7c.
All the input combinations along with the phase values are presented in Table 6.

An analysis of the results
The proposed device has a footprint of 7 µm × 4 µm. Performance parameters such as the insertion loss and extinction ratio are calculated from the output results. The insertion loss is given by where P out is the peak output power and P in is the peak input power.
The extinction ratio is defined as where P out |ON is the output optical power in the ON state and P out |OFF is the output optical power in the OFF state. The IL and ER in this work are found to be 0.165 and 14.11 dB, respectively. For better performance of logic gates, the insertion loss should be low while the extinction ratio should be as high as possible [44]. The current work is Insertion Loss (IL) = 10 log 10 P out P in , Extinction ratio (ER) = 10 log 10 P out |ON (P out |OFF) , Fig. 7 The light propagation through the proposed AND gate for all combinations of the input signals as obtained using the FDTD method compared with previously published works in terms of the mentioned parameters in Table 7.

Conclusions
An all-optical AND logic gate is designed with the help of a Y-shaped plasmonic MIM waveguide. The design has an area of 4 × 7 µm 2 , which is smaller when compared with previous works. Key parameters such as the insertion loss and extinction ratio are calculated. The IL and ER in this work are found to be 0.165 and 14.11 dB, respectively. Design parameters such as the S-bend length, input separation gap, and linear waveguide are optimized to obtain the maximum extinction ratio and minimize the losses inside the waveguide. Due to its simple structure and controllability, the Y-combiner-based AND gate can provide a new method to implement logic functions in digital electronics. This design has a minimized structure and can also be used in future work to design ultracompact devices for fast optical computing.