Single DC-Link based 5-Level MLI topology for Renewable and grid Applications with fewer Switches

This article describes a 5-level single DC source multilevel inverter (SDS-MLI) with fewer components and optimum eﬃciency. Multiple DC source MLI topologies are presently deemed unsuitable for a range of applications, such as renewable energy (RE) conversion systems and grid applications, while single DC source MLI topologies are more suitable. Existing MLI circuits have more active/passive components, but the SDS-MLI design employs a level-doubling network, requires fewer components, and reduces the DC-link voltage for grid applications. The SDS-MLI uses one capacitor, six switches, and a DC supply. A primary control method enforces a well-known phase disposition carrier arrangement to actualize the presented conﬁgura-tion. Existing systems are evaluated based on the number of active and passive components, their eﬃciency, capacitor voltage, and voltage stress. In comparison to existing topologies, SDS-MLI has fewer components, a lower capacitor voltage, and less TSVs to achieve an eﬃciency of 98.66%. MATLAB/Simulink and experimental setups are used to verify the SDS-MLI architecture. On the basis of experimental setup and simulation, the number of load voltage & load current waveforms under various situations such as variable load, varied input supply, diﬀerent frequencies, and diﬀerent modulation indexes are shown.

Single DC-Link based 5-Level MLI topology for Renewable & Grid Applications with fewer Switches.

Introduction
According to the most recent energy statistics, more power must be generated via the use of renewable energies (REs) in order to reduce the environmental harm caused by conventional energy production.Before it can be transmitted to the grid as high-quality AC power, the energy produced by REs must undergo buck/boost conversion phases.Therefore, efficient power converters are required.In single-stage grid-connected systems inverters play a major role, due to the high harmonic content present in the 2-level inverter's output, large filters are required to filter out harmonic in several applications like PV, grid-linked applications, and electric vehicles [1].These applications utilise MLI technology because it generates higher power quality and has less harmonics.Due to the wide range of medium-voltage applications, efficient power electronic devices are employed [1].Under certain conditions, MLI has the capability of raising the output voltage from low-voltage DC sources.
Because of these MLI capabilities, it is possible to attain higher power levels without having to make a commensurate increase in the switch rating.In the late 1960s, the concept of a multilevel step wave provided the impetus for the creation of MLI technology that uses both Cascaded H-Bridge (CHB) and Flying Capacitors (FC) [2][3][4][5].Despite the fact that these topologies were proposed for low-power applications, in 1970 the Diode Clamped Converter (DCC) was introduced.For medium-voltage applications, the Neutral Point Clamped (NPC) and the CHB were proposed in the 1980s [6].The FC Inverter (FCI) was modified in 1990 to enable its use in industries demanding medium-voltage and high power [7].CHB is the only documented conventional MLI topology with excellent modularity and does not need auxiliary components like clamping capacitors and diodes [8].Due to these advantages, CHB is widely used in a variety of applications, including grid integration, active filters, front-end converters, and energy storage [9][10][11][12].But when the number of devices needs to go up, more driver circuits, heat sinks, and protection circuits are required.This makes the inverter layout more complicated.As an outcome, MLIs developed, with the first research focusing on decreasing switches and their voltage ratings for high-power, medium-voltage applications, while the technology was still relatively novel.MLIs with many levels are being developed to reduce harmonic and filtering efforts [13].Using a combination of switches and DC sources/capacitors, an MLI provides many voltage levels, with each switch carrying less voltage than a 2-level inverter.Even at the lower switching frequency (f sw ), the used switches are turned on and off in compliance with a selected switching pattern to give different voltage levels at the output (low voltage block necessary because the switches cannot carry the whole DC voltage.)This MLI waveform generates higher voltage/current quality, necessitating a smaller output filter.Switching stress, a filter design issue and inconsistent performance are a few shortcomings of existing Multilevel DC-AC converters.To handle the conditions in high-power applications, a more number of inverter levels are required.
MLI produces stair-shaped output voltage, which has a higher conversion efficiency and better power quality.Asymmetric and lowered switch count arrangements have emerged due to the simplification of system counting and circuit design of typical MLIs at higher levels.In asymmetrical designs, DC sources are used to produce new output voltage levels by additive and subtractive combination, which results in different DC voltage ratios [14,15].However, this causes irregular device-blocking voltages and sharply increases the device ratings in several applications such as energy storage, active filters, and front-end converters for grid renewable integration [15,16].
There are a large number of reduced switch count (RSC) MLI configurations being developed in the past two decades as a consequence of efforts to simplify the topological structure of standard MLI setup.The necessary switching logic for multi-level design is not included in conventional multi-level or phaseshifted PWMs.PWM methods used in RSC-MLIs, such as switching function schemes and multi-reference, reduced carrier, are difficult to scale to LDNs [17,18].Changing from cascaded to LDN topologies affects the implementation of PWM.CHB is an MLI because it uses 2 H-bridge [19].Considering the many advantages of MLI control strategies and suggesting a more thorough analysis of different topologies.However, MLIs have a major drawback: in order to achieve substantially greater output levels, MLIs need much more semiconductor switches, which increases the overall cost, size, and complexity of management.An MLI can use low-voltage evaluated switches, but each switch needs a protection unit, a gate driver unit, and a heat sink.The structure can end up being bigger, bulkier, and more complicated as a result.Over the last several years, efforts have been undertaken to reduce the number of power switches, and voltage stress and increase efficiency in MLIs, these efforts have been evaluated in the literature [11,19,20].The proposed research is primarily concerned with providing an analysis of MLI topologies created with the specific purpose of minimizing the number of power switches.The study of these topologies has reached a definite result in terms of the following criteria: voltage blocking capabilities, power distribution across all switches, and the number of power switches [21].
In numerous modified MLI architectures, the eight IGBT switches in 5-Level CHB MLI have been increased or decreased.In addition, this paper discusses the updated proposed design that uses fewer switches overall (6 IGBT switches instead of 8).Several MLI topologies are presented with 2 or more than 2 capacitors, multiple DC inputs, and 6 or more than 6 IGBT switches (S 1 to S 6 ).[19,22].Sinusoidal pulse width modulation is applied in the presented model, and it is responsible for giving switching pulse to the six IGBT switches [23][24][25].Six IGBTs are utilized in the simulation model for MATLAB-SIMULINK, and each one has a switching pulse width specified for it.As a consequence, the THD content in load voltage and current are at acceptable limits.

Design
A novel topology of 5-level MLI is presented shown in Figure 1.It consists of only 6 controlled switches, a DC source, and a capacitor to generate 5-level.The benefits of the proposed topology are listed below: • A 5-level inverter needs a DC supply in addition to a capacitor in order to function effectively.It also has a less number of switches, which is 6, than other inverters.• The switching control logic for these types of switches is relatively easy since SDS-MLI uses three complementing switches.In order to produce the main switch, switching logic, a complementary switching plus is already provided by using a complemented operation.The main switch is represented by S 1 , S 3 , and S 5 , and the complementary switch is represented by S 2 , S 4 , and S 6 .• The maximum voltage stress across all controlled switches is V dc , thus when the switch is linked to the grid or under heavily loaded situations, the voltage stress across the switch is lower.• The SDS-MLI only requires one capacitor, and a capacitor's rating is equal to half of the input voltage.

Mode of operation
The operation of the SDS-MLI is shown in Figure 2. A combination of switches is turned on in such a way that the proposed topology generates a 5-level output voltage waveform.The unipolar bidirectional switch is used to flow the current in both directions.The capacitor charges with a maximum voltage rating of 0.5V dc .6 switches are used in the SDS-MLI, 3 are the main switch, and the remaining are its complement.To avoid a short circuit, the same leg switches do not turn on together.To generate each level, some group of switches is turned on which is given in Table 1.In Table 1, 'C' and 'D' denote the charging and discharging of a capacitor respectively.All levels are described in the following paragraph.

Comparison
On switches Levels 3 Modulation Technique & Parameter Calculation

Modulation techniques
There is various modulation technique used in MLI topologies to generate switching signal.Among the entire modulation technique phase-disposition PWM (PD-PWM) is better in terms of minimization of THD of load current [8].PD-PWM is used to generate a switching pulse for all switches because it reduces THD and uncomplicated operation.The amplitude and time period of all carrier signal is the same in this modulation technique.A 2-carrier signal is required to generate a 5-level.The diagram of this modulation technique is shown in Figure 3.In Figure 3 Both carrier signal magnitude is the same but the range of reference signal magnitude is zero to M CR2 .So, the modulation index is calculated by using Eq.( 1).
MI is related to the output level.If MI is between 0 to 0.5 then level will be generated.If MI is between 0.5 to 1 then V dc , V dc 2 , 0, −V dc 2 , -V dc will be generated, which is shown in Table 2.

Capacitance calculation.
One capacitor is used in the SDS-MLI to generate 5-level.However, it is important to find its capacitance value accurately to prevent charging from taking place.Consequently, two basic concerns must be addressed: The first one is focused on the current magnitude passing through the load and the phase relationship between the voltage & load.Another consideration is how long it takes to drain the capacitor while maintaining acceptable voltage ripples.The maximum time a capacitor can be drained is called its maximum discharge period is shown in Figure 4. Eq.( 2) is used to calculate the maximum charge store (QC) based on t 3 , t 2 & f o which is the time during maximum discharge period & output frequency.
The maximum charge stored for R-L load in Eq. ( 3).
So, after that required optimum capacitor value for a given load is calculated by using Eq.( 5).
4 Efficiency and Loss Calculation.
In this section, power loss of the SDS-MLI is presented.Power loss occurs due to several factors, which are given in Eq. (6).
P L = total power loss P sw = switching loss P conduction = conduction loss P cap,loss = capacitor voltage ripple loss

Switching loss
These type of losses occurs when switches are changed their state from off to on or vice versa.During off and on conditions, fluctuation in switch current and voltage happens.Due to fluctuation, switching loss occurs and is calculated by Eq.( 7) Where, V on & V of f : on and off-state voltage, I on & I of f : on and off state current, T on & T of f : on and off period of switch, The resistance of the active switches had an effect on the switching loss.The f sw affects loss that occurs during switching.When f sw is decreased or increased, switching loss also is decreased or increased.

Conduction loss
when the output voltage is & 0. I, I L & I C are the total currents, load current & charging current.In Figure 5 equivalent circuit of the positive half cycle is shown.For the negative half cycle equivalent circuit is analogous to +ve half cycle and conduction loss is also the same.In Table 3, the values of I C & I L , given that is used to calculate the average power (P avg ).time ratio factor is calculated by using Figure 4, like 4(t2−t1) T the time ratio factor for V dc 2 .So, total conduction loss is the sum of the total P avg of each mode.This type of loss occurs in energy-storing elements.So, in this article ripple loss occurs during to charging and discharging phenomena in a capacitor.In both operations, some energy loss happens which is considered a ripple loss.These types of losses depend on the time period and power factor.The voltage ripple loss is calculated by using Eq.(11).
By using Eq.( 6), total power loss is calculated.

Thermal analysis
The life span and efficiency of a semiconductor switch depend on temperature, that is depends on the heat produced on it.Due to heat, junction temperature (T j ) increases which create several risks on the circuit.Therefore, T j is always kept in the limit, under manufacture consideration.So a thermal analysis of the switch is needed for the proper operation of the circuit.In Figure 6 thermal equivalent model is shown.By using PLECS software, junction temperature (T j ) is determined for the IGBT module by Fuji Electric.The ambient temperature (T amb ) is maintained constant during the operation of a switch, where the initial temperature (T i ) is 0 0 C & final temperature (T f ) is 25 0 C. Average T j is calculated by using Eq.( 12).Average Power loss of switch & diode is calculated using Eq.( 15) & (18).
(P loss ) switch = switch (P cond + P sw ) (15) Where Where, I pk , M & V dc are fundamental currents, modulation index, & DC-link voltage.K v : voltage dependence factor.All used parameter values are taken from the data sheet [26]

Parasitic capacitance's loss
Losses due to parasitic capacitance are also included in the intrinsic features of the switch [26].During high-power applications very high heat loss happens so the heat sink is required back of the switch, due to this parasitic capacitance 'C p ' comes into the picture.C p is used to find switching loss in ON time, which is shown Eq.( 19): Where, (C p ) total loss = 6 n=1 [(C p , S n )] C p , S n is associated with power loss due to parasitic capacitance across each switch.To measure loss during the dead time another storing capacitor (C a ) is used across the device.The minimum value of load current is calculated using Eq.(20).
Dead time current 'I d ' is always lower than load current, and Eq.( 21) provides the voltage across the switch.
The total loss is calculated by using Eq.( 22): The total loss/output is dependent on voltage, which is 'C a V c ', and it contains both the ON and synchronization state.Table 5 shows the comparison of different topology efficiency with the SDS-MLI.For the calculation of power loss of the SDS-MLI, a parameter is given in Table 4. Eq.( 23) and ( 24) are used to calculate total conduction loss and total switching loss respectively.

Comparative Analysis
The proposed topology is compared with several recent 5-level topologies.Table 5 shows the comparative analysis of different 5-level topologies.In Comparative analysis, several factors are considered like as, the no. of switch (S), diode (D), capacitor (C), driver circuit (Dr), Total standing voltage (TSV), cost function (CF), efficiency (η), maximum voltage stress (MVS), Gain, capacitor voltage(V C ), and a maximum number of on switch during level generation & in charging path.The Sum of blocking voltage across all the switches is known as TSV, which is calculated by using Eq.( 26) & per unit value of TSV is calculated by using Eq.(27).
Where V rv : reverse voltage across switches.
The cost function of the SDS-MLI is 35.06,calculated by using Eq.(28).
Where Z=No. of level /Gain, N switch : No. of switch, N diode : No. of diode, N c : No. of capacitor, and α: weighting function.In [23] has approximately equal efficiency to the proposed topology, which is 98.5%, and contains 6 switches, 3 capacitors, and 2 diodes but the SDS-MLI has the best efficiency among compared topology, which is 98.66% along with it has lower components requiring 6 switches and 1 capacitor.
In [25] MVS is 0.5Vdc, but it has a high TSV and also requires 4 capacitors.In topology, [24,25] & [29][30][31][32] have a high gain but also contain 6 or more than 6 switches associated with 2 or more than 2 capacitors, so capacitor balancing is also required.Less number of driver circuits is Required in SDS-MLI topology among compared topologies because SDS-MLI has 3 complementary switches.In the proposed topology, the capacitor is charged with half of the input voltage, so a low-valued capacitor is required.
After comparing with existing topologies, SDS-MLI has a lesser component with less TSV & MVS and optimum efficiency.The application of SDS-MLI for the grid and renewable application is more suitable to other topologies because it has less capacitor voltage 0.5V dc and fewer components with less voltage stress across switches for high-power applications.

Simulation Results
The SDS-MLI is simulated on the MATLAB/Simulink platform to check the proper operation.Simulation is done for an input voltage of 100V for load resistance 40Ω & inductance are 20mH.The capacitor value is calculated by using Eq.( 5).The simulation parameter is given in Table 6.
The proposed topology SDS-MLI is being tested under various conditions Figure 8 shows the load current (I o ) and load voltage (V o ) under different load conditions.0.3 to 0.5 'R load' is connected, but after 0.5 loads changed, and 'RL load' is connected.

HARDWARE VALIDATION
A medium-power prototype hardware circuit is developed to validate the simulation results.DSP is used to provide a switching pulse to the switches, and the DSO (RTH1004) is used to see the waveform.Table 8 shows the parameter that is used during hardware validation.The complete hardware setup is shown in Figure 16.The proposed SDS-MLI works properly at different MI and also generates 5-level under different MI.While 50Hz is a typical frequency for AC power systems, testing at 200Hz allows for evaluating the MLI performance at higher frequencies that may be required in some applications such as aerospace or automotive systems.Proposed topology tested at the change in frequency condition i.e. 200Hz, shown in Figure 24.In this topology, the capacitor required less rating because the capacitor is charged with half of the input voltage (0.5V dc ).So, for high-power applications (grid and renewable) DC-link voltage and DC-link capacitors are required lesser voltage stress and low capacitor rating.

CONCLUSION
This paper presents a novel SDS-MLI 5-level structure using SC technology.MATLAB simulates the design accurately under various loading scenarios, MI, and frequencies.THD for the proposed topology's load current and load voltage at a given loading state is 3.60% and 30.06%, respectively.PD-PWM is used to drive switches, and the switching pattern is primarily focused on capacitor charging/discharging.The capacitor's operation and specifications are thoroughly explained.Half of the input voltage is used to charge the capacitor.By virtue of this property, low-value capacitors could be used in medium to highpower applications.The efficiency of SDS-MLI is 98.66%, which is higher than the efficiency of other compared topologies.A DSP-based medium-power prototype was developed and tested to ensure that it functions properly in each mode, demonstrating that the proposed topology can be used for different loads and MI.When working at different MI, the architecture can also produce the

S 2 ,
S 3 & S 6 switches are in a conduction state to generate '-V dc ', and the capacitor stays in the floating state, as illustrated in Figure2(a).To generate ' −V dc 2 ', the S 2 , S 4 & S 6 switches are turned on, and the capacitor is also charged with 'V dc 2 ', as illustrated in Figure2(b).S 2 , S 4 & S 6 switches are on in this mode, and 0 V occurs across the load, as illustrated in Figure2 (c).In this mode, 0 V also occurs across the load, by turning on S 1 , S 3 & S 6 switches as illustrated in Figure2(d).To create 'V dc 2 ' the switches S 1 , S 3 & S 5 are activated, and the capacitor is discharged with ' V dc 2 ' and fed to the load and DC source is isolated from the load, as illustrated in Figure2(e).To create 'V dc ' Figure2(f) shows that the S 1 , S 4 & S 6 switches are active.In each mode, the current path is shown with a dotted line.
, CR1 & CR2 are carrier signals and reference signals.The magnitude of carrier signal & reference signal is M CR1 , M CR2 & M ref respectively.
Figure 10 demonstrates changes in I o and V o when the

Fig. 8 :
Fig. 8: I o and V o under different load.

Fig. 10 :
Fig. 10: I o and V o under 50V supply voltage.

Fig. 11 :
Fig. 11: I o and V o under different frequencies.

Figure 17 showsFig. 18 :Fig. 19 :
Figure 17 shows the switching pulses of switches.The proposed topology is tested with two different supplies (30V & 15V), different frequencies (50Hz & 200Hz), and different loads (R & RL Load).The input voltage is 30V and the capacitor is charged with half of the input voltage, which is 15V.

Figure 18
Figure 18 and 19 depicts I o and V o at 0.9 modulation index and 30V input for R-Load & RL-Load respectively and Figures 20 and 21 depict load voltage and load current, when the input voltage is changed i.e. 15V for R-Load & RL-Load respectively.SDS-MLI is also tested at 0.6 MI, Figures 22 and 23 show the I o and V o for R-Load & RL-Load respectively.The proposed SDS-MLI works properly at different MI and also generates 5-level under different MI.While 50Hz is a typical frequency for AC power systems, testing at 200Hz allows for evaluating the MLI performance at higher frequencies that may be required in some applications such as aerospace or automotive systems.Proposed topology tested at the change in frequency condition i.e. 200Hz, shown in Figure24.In this topology, the capacitor required less rating because the capacitor is charged with half of the input voltage (0.5V dc ).So, for high-power applications (grid and renewable) DC-link voltage and DC-link capacitors are required lesser voltage stress and low capacitor rating.

Table 3 :
Calculation of I C , I L , P inst & P avg .Modes I c I L
S , No. of On Switch in charging path: N Sc , No. of On Switch in mode: N Sm , No. of Component: N c , Gain = B (P cond ) total = out + P cond + P sw + P cap,loss

Table 7 :
Voltage & Current stress across all switches.
will continue to function effectively even if the MI and frequency are changed.SDS-MLI can produce a 5-level at 0.6 MI, as demonstrated in Figure9.As a result, in the situation of 0.6 MI, SDS-MLI should effectively provide the same

Table 8 :
Experimental parameter.Figures 12 & 13, THD analysis of current and voltage is given.Current THD is 3.60%, which is within the limit as per IEEE standards and Voltage THD is 30.6%.Figure14& 15 blocking voltage and blocking current across all six switches and the value of blocking voltage and blocking current given in Table7.V dc or 100V is maximum voltage stress across 4 switches S 1 -S 4 and 0.5V dc or 50V is voltage stress across S 5 & S 6 .In all above mentioned different conditions, SDS-MLI works appropriately.Hardware validation of the proposed system to verify the simulation is discussed in the next section.