Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

In this paper, a dopingless nanotube field-effect transistor (DL-NT-FET) has been proposed and its performance analysis is carried out by eliminating doping, which is brought in by the application of the charge-plasma technique. A comparative examination of transfer characteristics, transconductance (gm), gate capacitances (Cgs, Cgd), output characteristics, output conductance gds, and various performance parameters are investigated by varying the channel length, radius, gate work function, and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater ION/IOFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The IOFF value increases significantly on increasing the temperature while the small degradation in the ION has been noticed as a result of mobility degradation and velocity saturation. The output conductance gds also degrades on increasing the temperature. A proliferation of 39 % is observed in the Cgs at the VGS of 0.45 V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the Cgd for the same increment in the channel length.


Introduction
The complementary metal-oxide-semiconductor (CMOS) technology has advanced through the decades to dominate the semiconductor industry with excellent features of low power and cost, dense packaging, and high-speed devices that are continuously scaled down in size [1][2][3]. When it comes to designing RF/analog circuits in the nanometer regime, several challenges have been encountered due to strict process requirements to maintain sharp source/drain region and short channel effects (SCEs) [4][5][6][7]. The electrostatic technique to add doping include additional fabrication steps and hence fabrication cost and complexity [8,9]. The junctionless field-effect transistor (JLFET) solves many of the issues related to SCEs but still, it suffers from poor carrier mobility due to high channel doping, which leads to transconductance/gain degradation and hence low ON current [10,11]. Dopingless nanotube FET (DL-NT-FET) can provide a solution by making use of the charge-plasma (CP) technique in which abrupt doped source and drain regions are formed in the intrinsic substrate with the help of suitable work function metal electrode or poly-Si electrode at the high temperature [12][13][14]. The gate-all-around (GAA) and shell-gated nanotube provide strong gate control over the channel carrier which results in enhanced surface inversion and hence superior drain current [15,16]. Hence, the proposed device exploits both the advantages of GAA structure (i.e. allowing better electrostatics and reduced SCEs) and dopingless configuration (like reduced random dopant fluctuations(RDFs), less mobility degradation, better gm) [17,18]. Besides the collective merit of GAA and dopingless nanotube, the impact of temperature on the performance parameters of the proposed DL-NT-FET is the first time investigated along with other design parameters.
In this article, a dopingless nanotube field-effect transistor (DL-NT-FET) is designed and its various performance parameters; transfer characteristics (I D -V GS ), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (I D -V DS ), output conductance (gds), average subthreshold slope (AVSS), the threshold voltage (Vt), the ratio of oncurrent to off-current (I ON /I OFF ) are investigated. The impact of nanotube radius (R), channel length (Lg), and gate work function variations on the performance parameters are examined to achieve high performance. The various performance parameters are also evaluated at a different temperature to study the temperature-dependent variability.

Device Structure
The 2-D structure of the proposed device is shown in Fig. 1(a) whereas the 3-D structure of the same is depicted in Fig. 1(b). The source, channel, and drain regions have been formed on an intrinsic Si body with the radius being 10nm and the silicon thickness being 7nm leaving the inner oxide thickness. CP technique is used to establish the source and drain regions of this dopingless device [19]. The gate oxide is made of SiO 2 and is 2nm in thickness. Both drain and source lengths are 30nm while the channel length is 20nm. P-type polysilicon (workfunction = 3.9 eV) is used in forming the source and   Aluminum is generally preferred for gate material of MOSFET but here the polysilicon is mainly utilized because polysilicon composition matches with the channel bulksilicon and therefore offers low threshold voltage as compared to that of metal gate material [20]. The proposed device is simulated utilizing Silvaco TCAD to analyze the various results. To account for accurate mobility evaluation in the channel, the Lombardi mobility model along with concentration and field-dependent mobility models are considered.  The variation of the electron-hole concentration and the energy band diagram of the proposed DL-NT-FET is illustrated in Fig. 2 for OFF-state conditions (V GS =0 V and V DS =1 V) and ON-state conditions (V GS =1 V and V DS =1 V) respectively. As it can be noticed from Fig. 2(a) that the concentration of the electrons in the channel region goes high from the low and the holes concentration goes low from high when the device comes into the ON-state condition from OFF-state condition due to the formation of the inversion layer of the electrons and depletion of the holes from the channel [21]. The energy levels of the conduction band and valance band are high in the OFFstate condition as compared to the energy levels of the conduction band and valance band in the ON-state condition Fig. 2(b). The bands bend downwards in ON-state because when a positive gate voltage is applied in the polysilicon gate, the Fermi potential (potential between Fermi level and intrinsic Fermi level) decreases due to an increase in the surface potential, and this result in large electron carriers in the intrinsic (initially) channel region [22]. The introduction of these high electrons shifts the conduction band down towards the Fermi level. Simultaneously the holes are also de-voided from the channel due to positive potential on the gate therefore the valance band also shifts downwards away from the Fermi level. Figure 3 depicts the variation of electric field and potential in the OFF-state and ON-state conditions. It can be seen from Fig. 3(a) that the electric field uplifts in the interface of sourcechannel and suppressed at the interface of channel-drain when the device comes in the ON-state condition from the OFFstate, this is due to the application of the positive gate voltage along with the drain voltage [23]. The low electric field at the channel-drain interface indicates less control of the drain to the channel and hence the DL-NT-FET implies low short  On the other hand, the surface potential goes high in the ON-state as intended due to more bending in the energy bands, at this stage the surface becomes doubled that of Fermi potential. Figure 4 shows the variation of the electron mobility and electron-hole pair recombination rate of the DL-NT-FET in OFF-state and On-state conditions. The electron mobility goes lower at the source-channel interface and becomes higher at the channel-drain interface Fig. 4(a). It is because the electric field is higher at the source-channel interface and lower at the channel-drain interface as is seen in Fig. 3(a). It can be observed from Fig. 4(b) that the recombination rate of the electron-hole pairs is zero in the channel region ON-state condition of the device channel region The impact of doped and doping-less I-V characteristics of nanotube-FET are plotted in Fig. 5. The source and drain region of the device are initially induced with the help of charge plasma technique to form the doping-less device while for the doped case both the region are defined and doped with the same doping level. It has been seen from the Fig. 5 that there is no changes in the drain current for both the cases so charge plasma technique can be beneficially exploited instead of doped technique so that fabrication steps will be reduced.
The drain current variation with channel length is plotted in Fig. 6(a) and its extracted performance parameters are listed in Table 1, it is noted that on increasing the channel length the ION/IOFF ratio enhances while the threshold voltage and Average sub-threshold slope (AVSS) of the DL-NT-FET reduce. An augmentation of 2 orders in the I ON /I OFF ratio and a reduction of 22 and 13 % in the threshold voltage and AVSS respectively have been recorded on increasing the channel length from 15 nm to 35 nm. The impact of the gate work function variation on the transfer characteristics of the DL-NT-FET is shown in Fig. 6(b) and various device properties that are extracted from its transfer characteristics are mentioned in Table 2. It can be observed that the OFF-current (I OFF ) reduces significantly as compare to the ON-current (ION) and therefore the I ON /I OFF ratio enhances on increasing  the gate work function. The threshold voltage also decreases on augmenting the gate work function whereas the AVSS initially decreases up to a work function of 4.5 eV but then starts increasing. Six orders increment in the I ON /I OFF ratio and an 81 % reduction in the threshold voltage has been observed when the gate work function is augmented from 4.3 eV to 4.7 eV. Figure 6(c) exhibits the variation of I D -V GS characteristics with temperature and the various performance parameters at different temperatures are summarized in Table 3. The I OFF value increases significantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. And therefore 6 orders diminution in the I ON /I OFF ratio is noticed when the temperature is increased from 200 to 450 K. threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92 % while the AVSS rises 114 % on increasing the temperature from 200 to 450 K. The effect of nanotube radius on the transfer characteristics and hence on various performance parameters are depicted in Fig. 6(d) and Table 4 respectively. On enhancing the radius of the nanotube of the DL-NT-FET, the I ON and I OFF both are increasing but the I OFF increases more rapidly as compare to the I ON and therefore the I ON /I OFF ratio reduces. The I ON /I OFF ratio is degraded by 3 orders on augmenting the radius from 8 nm to 16 nm. The threshold voltage and AVSS are increased by increasing the radius of the nanotube; there is an increment of 47 % in threshold voltage whereas an increment of 19 % in the AVSS has been observed while increasing the radius of the nanotube from 8 nm to 16 nm. Figure 7(a) shows the variation of transconductance with V GS at different channel lengths which is a specific figure of merit of a FET and it measures the precision in the conversance of gate voltage into the current. It is noticed from Fig. 7(a) that the transconductance increases with the increasing channel length (up to 25 nm) then it remains constant. The transconductance increases with the channel length because of higher change in drain current is obtained at the large channel length with a small change in gate voltage. At the 25 nm channel length, the obtained value of the gm is 5.2 × 10 − 5 S/ µm at the gate voltage of 0.45 V. Figure 7(b) depicts the changes in the gate to source capacitance (Cgs) and drain to source capacitance (Cgd) with the gate voltage. A proliferation of 39 % is observed in the Cgs at the VGS of 0.45 V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the Cgd for the same increment in the channel length.  Gate voltage V GS (V) g m for L g = 15nm g m for L g = 20nm g m for L g = 25nm g m for L g = 30nm g m for L g = 35nm (a) Capacitance (fF) Gate voltage V GS (V) C gs for L g 20nm C gd for L g 20nm C gs for L g 35nm C gd for L g 35nm (b) Fig. 7 Variation of (a) transconductance (gm) and (b) gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) with gate voltage at various channel length and VDS = 1 V The behavior of drain current concerning V DS for different values of V GS at the channel length of 20 nm and 35nm has been shown in Fig. 8(a), where it is again found that I D is more for channel length 20nm than that of for channel length 35nm. Moreover, it is also noticed that at smaller V GS , the saturation in the drain current occurs earlier as compare to the large V GS ; this is because of limited space-charge inversion in the channel which implies greater gate control over the channel. Figure 8(b) shows how the output conductance (gds) varies with V DS where V GS is fixed at 1 V and readings for 20nm and 35nm channels are taken. It is well known that gds is a crucial parameter in determining the intrinsic gain of a device and for better gain, it should be low. It can be seen from Fig. 8(b) that its value does not change with the channel length and the obtained value of the gds for the designed DL-NT-FET is 3.4 × 10-5 (S/µm).
The output characteristics (I D -V DS ) at the various temperatures are plotted in Fig. 9(a) and it is observed that the drain current decreases with an increase in the temperature. The I D decreases with the temperature because scattering phenomena increase with the temperature and these results in low carrier mobility in the channel and hence low drain current at the higher temperature [24]. The I D degrades 15 % on increasing the temperature from 200 to 400 K. Figure 9(b) shows the variation of the output conductance (gds) with the V DS at different temperature and it is found that gds also degrades on increasing the temperature and it is due to the reduction of I D at the higher temperature.
The impact of the nanotube radius in the output characteristics and output transconductance is plotted in Fig. 10(a) and (b) respectively and it is found that both the parameters are increasing with augmenting the radius. The I D enhances the increasing radius because a large radius renders large space charges in the inversion condition and the large drain current implies the higher output transconductance. An increment of 100 % in the drain current and 137 % in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm. This manuscript covers a proposed dopingless nanotube FET structure. Different characteristics of the device have been examined by TCAD simulated results. The obtained AVSS for 20nm channel length, the radius of 10nm simulated at 300 K is 68.80mV/decade which has much scope of improvement by optimization of the device. A comparative analysis of transfer characteristics (I D -V GS ), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (I D -V DS ), and output conductance (gds), has been made by varying the channel length (Lg), radius (R), gate work function (Φ) and temperature. An increment of 100 % in the drain current and 137 % in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm. The gate capacitances Cgs and Cgd are higher for the longer channel. On increasing the temperature from 300k to 400 K, the output conductance is found to decrease as well as the drain current gets saturated to a lower value whereas, by decreasing temperature to 200 K, the opposite happens. An augmentation of six orders in the I ON /I OFF ratio and 81 % reduction in the threshold voltage has been observed when the gate work function is enhanced from 4.3 eV to 4.7 eV. The ION/IOFF decreases with a temperature rise, there are 6 orders diminution in the I ON /I OFF ratio is noticed when the temperature is increased from 200 to 450 K. The threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92 % while the AVSS rises 114 % on increasing the temperature from 200 to 450 K. The transconductance curve has the highest peak value for the longest channel. It can thus be concluded that, after a thorough investigation of the behavior of the proposed dopingless nanotube FET parameters under several variations, it can be well understood that there are a good number of challenges to get the optimized results.
Author Contributions All authors have equally participated in the preparing of the manuscript during implementation of ideas, findings results, and writing of the manuscript.
Data Availability Current submission does not contain the pool data of the manuscript but the data used in the manuscript will be provided on request.

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Conflict of Interest The authors declare that they have no conflict of interest.
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