Impactful Study of F-shaped Tunnel FET

In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric field crowding effect at the corners of the source region which reflect in terms of high ON-current (Ion). The Ion of the proposed device is increased up to 10− 4A/μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.


Introduction
The steeper subthreshold slope devices are necessary to alter next generation low power device application in the field of electronics. The TFET is one of the most extensively investigated novel devices with their methodologies that can potentially surpass the 60 mV/decade limit of SS in MOSFET at room temperature [1][2][3]. The TFET working operation is based on BTBT mechanisms, and it is capable of attaining a smaller SS value. However, the ambipolar behavior (high ambipolar current (I amb ≈ 10 −7 A/μm)) and low I on (≈ 10 −6 A/μm) for which TFET can be realized by a small tunneling junction with limiting SCi region. To overcome these leading limitations of TFET, many researchers investigated different structures and materials by using antithetic concepts and techniques [4][5][6][7][8][9]. In this simulation-based work, a novel SG-FC-TFET has been studied and optimized to obtain high I on , suppressed I amb , and minimum V on with the steeper sub threshold slope Prabhat Singh prabhat@nith.ac.in Dharmendra Singh Yadav dsyadav@nith.ac.in 1 Electronics and Communication Engineering Department, National Institute of Technology, Hamirpur, Himachal Pradesh, 177005, India of I ds − V gs curve. Along with this, the analog and radio frequency performance parameters were analyzed through the 2D-TCAD tool, to optimize the device performance for high frequency applications with low power consumption.

Designed Device Specifications
The 2D cross-sectional view of conventional double gate TFET (DG-TFET) and the proposed device structure under study is illustrated in Fig. 1a and b. The proposed device resembles a finger-like ultra-thin N-type source region (dark green color) which is completely enclosed by a lightly doped P-type channel region. Due to complete insertion of source in channel region, the tunneling area is increased. Along with this, electric field crowding effect came into existence at the corner of source region. A metal gate (gate work function (W F gate )= 4.6 eV) with a SiO 2 as gate oxide is used to improve the controllability over channel region. Along with different colors displayed in Fig. 1b defining various regions of simulated device like oxide, source, gate, channel, drain electrodes and their region, etc. The simulated device and DG-TFET are with drain doping N DN = 1 × 10 18 cm −3 (N+ type), source doping N SP = 1 × 10 20 cm −3 (P+ type), channel doping N CP = 1 × 10 15 cm −3 (P-type) and SiO 2 (k= 3.9) as gate oxide material.
, t c−u = 16nm, T total = 41nm and L total = 103nm with SiO 2 as gate oxide layers can be grow (active regions) with the help of insitu doping process. After this, CVD (chemical vapor deposition) method is use to deposit SiO 2 hard-mask and this will cooperative to passivate active sidewall. SiO 2 sacrificial buffer layer deposited after performing mesa pattering process. Along with this, a dummy gate is formed and etch back process performed to remove the SiO 2 buffer layer. With the help of RTA (Rapid thermal annealing) and ion implantation process, arsenic impurity (VA group) is added to define the drain region and a thick layer of SiO 2 is deposited. To evince the dummy gate, CMP (chemical mechanical polishing) is used. For ultra-thin lateral tunnel region, selective epitaxial layer of silicon is grown after the selective removal of dummy gate and SiO 2 sacrificial buffer layer. After this, the stacking of gate and gate-oxide is performed by using atomic layer deposition processes.

Results and Observations
The DG-TFET and SG-FC-TFET are simulated in a 2D-TCAD simulator using nonlocal BTBT, SRH, FLDMOB, auger, FERMI, and CONMOB models. Along with, quantum tunneling region (qt region) for accurate lateral tunneling of electrons and holes at both interfaces (SCi and DCi). The comparative analysis between both devices is perform to ensure the performance advantages of proposed device over the conventional DG-TFET. From Fig. 3, the I amb is suppressed by seven decade because the the BTBT rate is reduced as DCi decreases. However, I on increased by 3 decade because of electric field crowding effect and increased tunneling area at SCi. The turn-ON voltage is reduced by 0.25V for the proposed device when compare to DG-TFET because very high charge accumulation takes place at the SCi junction and high ELF crowding effect helps to enable the BTBT phenomena earlier. Along with, the steepness of I ds − V gs is improved and the SS value for proposed device is reduced (7.3 mV/decade).
The electric field (ELF) variation of proposed device along with different cut lines is illustrated in Fig. 4. The ELF plays an important role in the proposed device operations [15,16], hence it can be analyzed in different regions by imposing cut lines. AA' (Black square) and BB' (Red circle) horizontal cut lines are used to compare ELF at the corners of source region where ELF crowding takes place. The ELF along cut lines AA' and BB', which run parallel to the upper and lower source junctions exhibit peak each at X ≈ 66 nm, which falls within the channel. Besides, the field is nearly uniform and rather small at the lateral source junction, shown in Fig. 4a. Next, The ELF at the CC' cut line, intersecting the drain junction, exhibits a first peak (≈ 4.5 × 10 5 V/cm) within the channel and second peak occurs at X ≈ 90 nm (≈ 1.5 × 10 5 V/cm) because the DCi junction at X = 91 nm, as depicted in Fig. 4b. For analysis of ELF crowding effect at corner and flat region of source, vertical VV' cut line used, it exhibits double peak at Y ≈ 15 nm and 20 nm, as portrayed in Fig. 4c. Therefore, we can conclude that at the corner of source region ELF is very high (E corner =4×10 5 V/cm) compare to flat region (E f lat =2.3 × 10 5 V/cm). The high ELF at source corners (Fig. 4), causes higher drain current due to improved tunneling probability at SCi. From Fig. 5a, we can observe that the drain current (I ds ) increased rapidly w.r.t., V gs at fixed V ds = 0.7 V.
The slope of I ds − V gs curve defines the amplification ability of the device, which is also known as g m . The g m of a device also depends on the I ds [17,18]. Hence, higher  (Fig. 5b). On the other hand, g ds of the device is required low for better device performance because output resistance (R out ) of device inversely proportional to g ds . For better amplification property, we need a device with high R out [19]. For the proposed device, the g ds is obtained 23 μS, as displayed in Fig. 5c. The ratio of g m to g ds is known as intrinsic gain, it should be high for better amplification property of a device [20]. From Fig. 5d, the intrinsic gain of the proposed device is increasing with V gs (up to 0.9 V) and Fig. 3 Comparative Transfer characteristics of DG-TFET and SG-FC-TFET attain the peak value 68 obtained as an ratio. Furthermore, it starts decreasing due to mobility saturation of charge carriers a significant reduction been observed in g m .
The radio frequency (RF) parameters play a very crucial role in the circuit level analysis of the device. Regarding this, the parasitic capacitances (C gd and C gs ) are analyzed and depicted by Fig. 6a and b. The C gd is a critical parameter that affects many other RF parameters (f t , GBP, etc.) [19]. The lower value of capacitances are observed in this proposed device because of less accumulation of charge carriers at SCi and collected by drain region. The reduced value of C gd helps to improve the gate controllability over the channel region with enhanced f t and GBP values of proposed device [20], as illustrated in Fig. 6c and d. The f t and GBP increased to achieve their apex, then with higher C gd it starts decreasing.
To explain the trade-off between intrinsic gain and cutoff frequency, another parameter is introduced named GFP. It is increasing with V gs due to an increment in intrinsic gain and f t (Fig. 7a). Its curves start decreasing due to mobility saturation of the charge carriers which are responsible for existence of parasitic capacitances. Along with, TFP and TGF are also examining to check the device efficiency and consumption of power. TFP defines the relation between power and bandwidth [20]. Therefore, a higher value of TFP = 0.31 GHz (Fig. 7b) indicates that the proposed device is suitable for low-power applications. On the other hand, TGF defines the device efficiency in terms of circuit operation. The higher value of TGF reflect in terms of high  [20]. From Fig. 7c, we can observe that TGF of 8 × 10 4 V −1 is achieved for the proposed device (SG-FC-TFET). The transit time (τ ) is inversely propositional to f t . For higher f t , transit time is less [10]. In other words, τ represents the delay of a device, so the speed of SG-FC-TFET is improved with a reduced value of τ . From Fig. 7d, we can analyze that τ is in the range of 210.5 μs, which indicates that the proposed device can be used in digital circuits with the advancement of high speed as well as low power consumption [21]. According to the above impactful studies carried out, the proposed device (SG-FC-TFET) is best suited for low power high speed with enhanced RF performance.

Conclusion
In this study, we have inspected the solitary characteristics of SG-FC-TFET with fabrication process flow. It is worth pointing of the effect of a finger-like shape of the source region on analog/RF parameters is investigated using a 2D-TCAD simulator in this analysis. The proposed device achieved I on = 4.35 × 10 −4 A/μm, I ambi = 6.35 × 10 −18 A/μm, I on /I off = 6.85 × 10 13 , V on = 0.28 V and SS of 7.3 mV/decade. Along with these results, some important parameters were also examined to study the RF performance of the SG-FC-TFET device like g m (830 μS), g ds of (23 μS), C gd of 0.23 fF, C gs of 0.28 fF, f t = 370 GHz, GBP = 176 GHz, and GFP of 24 THz. To achieve high performance, some additional parameters related to the speed and power of the device are also investigated that as TFP (0.31 GHz), TGF (8 × 10 4 V −1 ), and transit time (210.5 μs). The promising results obtained for the proposed design demonstrate its applicability in both analog and digital technologies.