Analytical Breakdown Voltage Model for Partial SOI-LDMOS Transistor with Buried Oxide Step Structure

- We have developed a simple physics-based two-dimensional analytical Off-state breakdown voltage model of a Partial Buried Oxide Step Structure (PBOSS) Silicon-On-Insulator Lateral Diffused Metal Oxide Semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson’s equation. The electric field at the Si-SiO 2 surface is modified by creating additional electric field peaks due to the presence of the PBOSS structure. The uniformly distributed electric field results in improving the breakdown voltage. Further, the breakdown voltage is analytically obtained via critical electric field concept to quantify the breakdown characteristic. The model exploits the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by the results obtained from ATLAS two dimensional simulations. The analytical model is of the high potential from a physical and mathematical point of view to design high voltage SOI-LDMOS transistors for power switching applications.


INTRODUCTION
With the advancement in solid-state technologies, power electronics application is an ever-expanding topic of research and development, proving its potential to solve several market challenges [1], [2]. The silicon power devices have been providing the solution midrange voltage applications ranging from 100s of watt to serval megawatts [3]. Nowadays, the integration of LDMOS like power devices into the CMOS platform is of interest to High-Voltage Integrated Circuit (HVIC) technology, space power systems, data conversion, and electrostatic discharge protection applications [4][5][6]. The SOI-LDMOS transistor has attracted much attention due to its near-ideal isolation, reduced parasitic active components, low leakage currents, etc. among the HVIC designing community [7][8][9][10]. Also, a total vertical and lateral dielectric isolation prevents the overstress events arising in high-voltage transistors fabricated on SOI substrates [11]. On the other hand, an increase in self-heating, reduction in the breakdown voltage, hence reduced Safe Operating Area (SOA), are the challenging issues [12]. Recently, a Partial-SOI LDMOS technology [13][14][15], has been reported to overcome the problems observed in the conventional SOI-LDMOS transistors. Orouji et al. [16] reported a new PBOSS SOI-LDMOS transistor with a modified step buried oxide structure. It improves the Off-state breakdown voltage (VBR) by producing two additional electric field peaks in the drift region. An analytical model would be very useful for formulating the design guidelines of the advanced semiconductor devices. Moreover, the analytical models can provide an insight into its physical mechanism and shorten the design time [17,18]. In a sense, the analytical model is indispensable. Several analytical models are proposed for the surface field distribution of conventional and buried oxide step SOI-LDMOS transistors [19][20][21].
However, the analytical model for the PBOSS SOI-LDMOS transistor is still lacking to the best of our knowledge.
In this paper, a two-dimensional analytical model for the PBOSS SOI-LDMOS transistor is presented. The variation of electric field and potential is modelled by solving the two-dimensional differential equation for power switching applications.
The paper is organized as follows. In Section 2, we present the investigated transistor with dimensions used for detailed explanations. Also, the simulation methodologies are described in this section. Section 3 presents the analytical model formulation. The results are discussed in detail in Section 4. The summary of the results has been outlined in the Section 5.   [16]. A uniformly doped region P-Well creates the channel part of the device with a doping concentration represented by NA. The drift region is low doped, represented by NDr. A Player is used, as shown in Fig. 1 to elevate the thermal effects which are inherent to SOI-LDMOS transistor. NP-layer represents the doping concentration of the P-layer. A step in the buried oxide layer (BOX) is created to enhance the VBR by modifying the surface electric field. The thicknesses of the silicon epitaxial layer, the buried oxide, and step layer are represented by tSi, tBOX, and tBOSS, respectively. The drift region is divided into three regions-1, region-2, and region-3. L1, L2, and L3 are the boundary in the x-direction for region-1, region-2, and region-3, respectively. The substrate is of P-type and lightly doped. The device parameters of the PBOSS are equivalent to those of the BOSS and Conventional SOI-LDMOS transistors. The critical design parameters are given in Table I.  Selberherr's model is considered for impact ionization according to (1),

INVESTIGATED DEVICE STRUCTURE AND SIMULATION METHODOLOGY
Here, E is the electric field in the direction of current flow at a particular position in the structure, and the parameters AN, BN, and βn are defined as 7.03×10 5 cm -1 , 1.231×10 6 V/cm, and 1.0, respectively [23]. As the peak electric field is quite sensitive to mesh design, the structure is designed with optimum mesh in the deck.

Potential and Electric Field Expression
Assuming that, the drift region is under complete depletion for breakdown condition, the potential function (ϕ) in region-1, 2, and 3 are described by the 2D Poisson's equation as follows.
where 'q' is the charge of the electron. Here N1 = N2 = N3 = NDr. εSi is the dielectric constant of silicon.
The boundary conditions for the potential and electric field are given as follows, At the Si-SiO2 surface, the vertical electric field may be ignored, which results in (3). The electric flux density is continuous across the n-drift region and P-layer. This results in (4).
The continuity of the electric flux density at Si-BOX interface results in (5). Similarly, other boundary conditions (6) to (10) are shown to satisfy Gauss's law. The solution of twodimensional equation (2) is achieved by the polynomial approach is as follows Substituting the boundary conditions (3) -(5) into (11) leads to a general differential expression for the potential distribution as (12).
While deriving (12) from (2), also it can be shown that, The surface electric field is expressed as, The expressions of (16) and (18) can be simplified for the BOSS and the Conventional SOI-LDMOS transistors using suitable boundary conditions.
The lateral and vertical electric fields at any point can be expressed as (19) and (20) respectively.

Breakdown Voltage Expression
  In this paper, the critical electric field (Ecrit) is determined by (

RESULTS AND DISCUSSION
In this section, the numerical simulation results are compared with the proposed analytical model. The simulation data at the top silicon surface implies the data obtained across cross-section FF` as shown in Fig. 1. Similarly, the simulation results at the bottom silicon interface are considered across cross-section HH` as shown in Fig. 1. The potential and the electric field distributions are shown only for the drift region. Hence the starting point of the lateral position is the pn-junction, which separates the MOS and drift junction. The device parameters in Table-I    From the simulation studies, it is found that the VBR of the PBOSS SOI-LDMOS transistor is ~ 170 V, whereas the BOSS and Conventional SOI-LDMOS transistors break down at ~ 126 V and ~ 80 V respectively as shown in Fig. 2. The VBR is measured using the industry-standard constant current (1E-10 A/µm in this paper) measurement method. Fig. 3(a) shows the numerical and analytical profiles of surface potential at cross-section FF` for the investigated transistors at breakdown condition. It changes at the boundary of region-1 and region-2 and the boundary of region-2 and region-3 for the PBOSS SOI-LDMOS transistor.

i. PBOSS, BOSS and Conventional SOI-LDMOS transistors: Variation of Potential, Electric Field and Equipotential Contours
To know the reason behind this improved VBR, it is important to study the variation of the electric field both at cross-section FF` and HH` as shown in Fig. 3

(b) and 3(c) respectively.
Both the fields are correlated through (19) and (20). For the Conventional SOI-LDMOS transistor, the electric field is almost flat at cross-section FF`, as shown in Fig. 3(b) with two usual peaks at pn-junction (which separates the MOS and drift region) and nn+ junction. The step-like structure in BOX creates an additional electric field peak near the step, as shown in Fig. 3(b) for BOSS structure [21]. It is observed that the PBOSS SOI-LDMOS transistor introduces additional electric field peaks apart from the peak at pn-junction and nn+ junction, as shown in Fig. 3(b). The first additional electric field peak is due to the P-layer charges at the region-1 and region-2 boundary. The second additional electric field peak is created due to the sudden change in buried oxide step thickness at the region-2 and region-3 boundary  The equipotential contours for the Conventional, BOSS and PBOSS SOI-LDMOS transistors in breakdown condition are shown in Fig. 4(a) -4(c) respectively. For the Conventional SOI-LDMOS transistor, the equipotential contours are more unevenly spaced, as shown in Fig. 4(a). The potential contours are not able to spread into the substrate for the Conventional SOI-LDMOS transistor. The equipotential contours are uniformly distributed for the BOSS SOI-LDMOS transistor than the Conventional SOI-LDMOS transistor, as shown in Fig. 4(b). It is observed that the equipotential contours are distributed uniformly for the PBOSS SOI-LDMOS transistor, as shown in Fig. 4(c). The potential contours spread to the substrate for the PBOSS SOI-LDMOS transistor. For the PBOSS structure, the P-layer supports a higher electric field, which is originated from the interface between the P-type layer and buried oxide. This leads to a more uniform distribution in the electric field; therefore, the VBR is enhanced significantly.
where VSi and VBOX are the potential across SOI film and buried oxide. EI and tBOX,eff are the vertical electric field in the BOX and effective buried oxide thickness. As the tBOSS increases, the voltage drop VBOX also increases; hence, the VBR also increases. The surface electric field is increasing with the increase in tBOSS at point-C, as shown in Fig. 5(a). This results in a more uniform distribution in the surface electric field. However, a further increase in tBOSS results in a reduction in VBR as the peak electric field is comparable with the critical electric field and breakdown occurs. The variation of the VBR with tBOSS is as shown in Fig. 5(b). The VBR is increased up 170 V at tBOSS = 1.5 µm. So, there exists an optimum value of tBOSS, where an improved performance in the VBR is achieved. As observed in Fig.   5(b), the VBR is decided by the minimum VBR at point-D and point-E up to as tBOSS = 1.5 µm.
Beyond the optimum tBOSS the drift region will partially deplete when the breakdown occurs and the VBR is decided by VBR,A. Hence the VBR follows a bell shape curve, as shown in Fig.   5(b). The variation of the surface electric field along the lateral direction is shown in Fig. 6(a) for different L2. It is to highlight that the LBOSS is measured as L3 -L2. As L2 is increased, the length of the BOSS layer LBOSS reduces. Here, L3 is fixed at 15 µm. At LBOSS = 0 µm, the peak of the surface electric field due to BOSS superimposes on the drain end electric field peak. As L2 reduces (i.e., LBOSS increases), the electric field peak at point-C is noticeable. For L2 = 11 µm (i.e. LBOSS = 4 µm) the surface electric field distribution is more uniform. There is an optimal value of LBOSS where the VBR is maximum. As the LBOSS increases beyond this optimal value, the peak due to the BOSS layer superimposes with the electric field at the pnjunction, as shown in Fig. 6(a). The variation of VBR with L2 is shown in Fig. 6(b). The VBR initially increases with the L2, and the maximum VBR is found to be 170 V at L2 = 10 µm i.e.
(LBOSS = 5 µm). As L2 is increased above 12 µm, the VBR falls sharply. It is observed that the VBR follows almost the value at VBR,D for the entire range of L2. It is to highlight that choosing an optimum value of L2 (which subsequently determines LBOSS) is important for device designers to achieve higher VBR. The effect of silicon film thickness tSi for the PBOSS SOI-LDMOS transistor is shown in Fig. 7. As the tSi increases, the electric field peak is increased at point-D to fulfill the RESURF criterion for a given doping concentration of the drift region. It is observed that as the tSi increases, the surface electric field becomes more uniform (as shown in Fig. 7(a));

B. Effect of Silicon Thickness (tSi) and Doping (NDr)
hence the area under the electric field is maximum. The VBR initially increases with tSi, and it follows the VBR,D up to tSi = 0.5 µm (full-depletion occurs), as shown in Fig. 7(b). A maximum VBR of 170 V is achieved for tSi = 0.5 µm and limited by the vertical breakdown VBR,E. As the tSi increases more, the VBR is decided by VBR,A (i.e., the breakdown occurs due to partial depletion). Fig. 8(a) shows the surface electric field distribution for different NDr. As the NDr increased from a low doping concentration of 2.0×10 16 /cm 3 to 3.3×10 16 /cm 3 , the peak of the surface electric field at point-D is increased, and full depletion occurs. The maximum VBR is found to be 170 V for NDr = 3.3×10 16 /cm 3 . As NDr increases further, the drift region is partially depleted, and the electric field peak at point-A is comparable with the critical electric field. A highly doped drift region acts as an extended drain contact, missing its original role of extended body. The VBR after the optimum NDr is decided by the VBR,A as shown in Fig. 8(b). The model provides a reasonable justification for the bell-shape nature of the VBR.

CONCLUSION
We have developed an analytical model of breakdown field by calculating the variation of surface potential and electric field for PBOSS SOI-LDMOS transistor for the first time. can, therefore, serve as a good analytical tool for the design of high voltage SOI-LDMOS transistors.