Design a Hybrid Memory Array for Radiation-Hardened SRAM in Satellite Image Compression Systems

doi:10.21203/rs.3.rs-3423461/v1

In the satellite technology landscape, the satellite industry is crucial across military, meteorology, safety, climate monitoring, and landscape mapping sectors. The demand for high-quality satellite imagery has led to innovations in image processing and compression techniques to overcome challenges such as data storage limitations and slow upload speeds. This paper focuses on optimizing on-board SRAM memory cells for satellite image compression, addressing issues like radiation-induced errors, memory size, and power efficiency. A hybrid memory array is proposed, allocating reliable cells for Most Significant Bits (MSB) and less reliable cells for Least Significant Bits (LSB), optimizing area, power, and data integrity. The research evaluates SRAM cell sensitivity to radiation-induced Single Event Upsets (SEUs), with simulation results indicating smaller cell sizes and lower operating voltages increase susceptibility. Simulate a comparative analysis involving radiation-hardened SRAM cells, including CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, and PCELL10T, and proposed 12T. Proposed 12T cell is significantly 1.22x/3.77x/3.9x/4.1x/1.86x less write delay then CC18T/RHC14T/RHMC12T/SRRD12T/PCELL10T, respectively. Additionally, 2.27x/1.98x/71.29x lower read access time than RHMC12T/SARP12T/SRRD12T memory cells. The area occupied by our proposed cell is substantially smaller, with it being 2.03x/1.39x/1.18x/1.6x/1.09x less than CC18T/RHC14T/RHMC12T/ SRRD12T / PCELL10T. Furthermore, observed improvements in read, write and hold Noise Margins, and critical charge. Introduced an Electrical Quality Metric (EQM) to provide a comprehensive assessment of SRAM cell performance, and our proposed cell excels in terms of EQM compared to the others.

Satellite Image

SRAM

Memory array

SEUs

Critical Charge

In today's technological landscape, the satellite industry plays a crucial and multifaceted role, influencing various sectors, including the military, meteorology, safety, climate monitoring, and landscape mapping. Recent trends have driven innovation within this industry [1,2]. Satellites are increasingly utilized for ground imaging purposes, encompassing applications like landscaping, meteorology, and intelligence, fostering competitive research in image processing aimed at extracting invaluable insights. These satellites efficiently capture high-quality images of the Earth's surface [3]. However, achieving top-tier quality in satellite imagery presents its own set of challenges, primarily revolving around extensive data storage and sluggish upload speeds [4]. In response to these challenges, modern image compression techniques like lossless compression, lossy compression MPEG, JPEG, notably 'image compression,' are enlisted to tackle these hurdles head-on. Image compression reduces the storage and transmission requirements of images while preserving their visual quality, making it efficient for data transfer and storage [5]. Figure 1 illustrates the satellite compression process. In this on-board satellite image compression unit, the encoder processes, stores, and transmits images, effectively reducing redundancy and creating smaller files for storage and quicker transmission [6]. This process requires computational processing for compression and a decoder for decompression at the receiving end. The paramount objective is to preserve image quality during compression, thereby ensuring the effectiveness of data recovery and evaluating the efficiency of these tools. As satellite sensors continue to advance, resulting in larger image files, the demand for high-density on-board memory intensifies. The central focus of this research revolves around on-board memory, encompassing the challenges of addressing its vulnerability to radiation-induced errors, optimizing memory size and power

efficiency to meet satellite constraints, and ensuring reliability in space environments [7]. In satellite systems, SRAM memories are commonly used. Their advantages for space. applications include their high-speed operation, enabling rapid data access and processing; low latency, vital for real-time applications in space; and the ability to retain data without the need for frequent refresh cycles, which makes them well-suited for critical tasks in the challenging space environment [8]. In the realm of technological advancements, on-board SRAM memory in space applications faces several challenges. Firstly, the heightened risk of radiation-induced errors due to satellite advancements necessitates robust error mitigation strategies. Secondly, increasing data volumes demand larger memory sizes, prompting the need for high-density SRAM solutions. Lastly, optimizing power efficiency is crucial to align with strict power budgets as satellites incorporate more advanced features. Balancing these challenges is pivotal in ensuring the reliability and success of space missions, where data integrity, memory area, and power efficiency are paramount concerns [9].

Numerous researchers are actively engaged in the design of memory cells tailored for space applications. However, this endeavour comes with its set of formidable challenges, primarily revolving around data integrity, area efficiency, and power efficiency [10,11,12]. Ensuring data remains accurate and reliable in the harsh space environment, characterized by radiation and temperature extremes, is a paramount concern. Simultaneously, memory cells need to be compact to optimize space utilization on satellites and spacecraft while still providing sufficient storage capacity. Balancing these constraints with power efficiency, crucial for adhering to strict power budgets in space missions, adds complexity to the already intricate task of designing a memory cell that excels in all these aspects simultaneously. Achieving all these objectives within a single memory cell is impractical. Therefore, our research focuses on designing a hybrid memory array to offer an optimized solution for on-board SRAM memory used in image compression. As research shows in an 8-bit image pixel, both the MSB and LSB play pivotal roles in influencing image quality [13,14,15]. The MSB, being the most significant, primarily determines a pixel's overall brightness or colour. Modifying the MSB can result in noticeable changes in contrast and dominant colour tones, significantly impacting image quality. Conversely, the LSB, as the least significant bit, represents finer variations within the pixel's value, such as fine textures or noise. Adjusting the LSB typically affects subtler aspects of the image. However, it can potentially lead to a loss of fine image details, reducing image sharpness or introducing unwanted noise. On the other hand, the reliability of space memory is mostly affected by radiation effects, such as the Single Event Upset (SEU) effect, which decreases transistor currents and nodal capacitances. SEU dominates over all other failure mechanisms [16]. If the SRAM area is large, it is capable of resisting a larger critical charge and is less susceptible to SEU. However, at the same time, it consumes a larger amount of power. Conversely, small-sized SRAM cells consume less power, but their SEU failure rate is higher [17].

In our design concept for hybrid memory in on-board SRAM memory for image compression, we allocate high-reliable memory cells for storing MSB bits and less reliable memory cells for storing LSB bits. This approach offers a balance between data integrity and resource efficiency, optimizing both area and power utilization. In the in next section, we explain in detail how this radiation affects SRAM memory stability.

Major contribution of this research:

1. The study quantifies the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) in space, providing insights into memory resilience.

2. A comparative analysis shows that the proposed SRAM cell outperforms existing radiation-hardened cells in terms of key performance metrics such as RAT, RSNM, WD, and WM.

3. The introduction of EQM as an assessment tool highlights that the proposed SRAM cell exhibits superior overall performance and reliability when considering key design metrics

4. The research proposes a hybrid memory array for satellite image compression, combining high-reliable memory cells for MSBs and less reliable cells for LSBs, optimizing memory use while preserving data integrity.

In the vast expanse of deep space, there exists a significant presence of highly energetic particles that pose a challenge to the functionality of memory circuits [18]. When these energetic particles collide with the substrate of a MOS transistor within an SRAM semiconductor memory, they give rise to electron-hole pairs. This collision-induced event creates an electric field due to the reverse bias between the diffusion region and the substrate/n-well, which appears as a forward field to the minority carriers generated.

Consequently, the minority carriers drift towards the drain diffusion regions, leading to an accumulation of charge as shown in Fig. 2. This accumulation results in the generation of a voltage spike, either positive or negative, depending on the type of minority carrier involved. If the magnitude of this voltage spike surpasses the switching threshold of the logic circuit and its duration is sufficiently long, it can cause a disturbance in the stored content, leading to a phenomenon known as a single-event upset (SEU).

It's important to highlight that SEUs pose a significant threat to SRAM cells due to positive feedback mechanisms that can result in a change in stored values. This vulnerability makes SRAM cells particularly sensitive to SEUs, especially in space environments. To evaluate this sensitivity, we quantify the minimum charge needed to disrupt stored data, known as the Qc. To determine the Qc in an SRAM cell, we utilize a double exponential current pulse model (in Eq. 1)[19].

$$I\left(t\right)={I}_{0}\left({e}^{-\frac{t}{t\alpha }}-{e}^{-\frac{t}{t\beta }}\right) \left(1\right)$$

Where, I(t) = injected Current, ${I}_{0}$=Peak current, ${t}_{\alpha }$=Fall time constant, ${t}_{\beta }$ = rise time constant. For the simulation ${t}_{\alpha }$ =200ps, ${t}_{\beta }$=50ps and ${I}_{0}$=50µA. This model simulates the effects of a high-energy particle strike on a sensitive node, helping us gauge potential outcomes [20]. The Q_c in SRAM memory is influenced by various factors, including memory size, device scaling, and operating voltage. Smaller memory sizes and lower operating voltages tend to reduce the Q_c, rendering SRAM more susceptible to SEUs. In this section, we analyze the impact of memory size on Q_c and upset probability of SRAM due to SEU. To analyze how cell area affects the Q_c and upset probability necessary to disrupt an SRAM cell, we conducted a simulation study using a 6T SRAM cell designed for 45nm GPDK CMOS technology. To comparison of the probability of upsets over the cell area value range to the probability of upsets at the corresponding injected charge level. To find out probability of upset we run 1000 Monte Carlo simulation and find the ratio of upset event to total simulation. Figure 3(a) shows the simulation. The upset probabilities corresponding to the PMOS cell area values and injected-charge levels. It is evident that lower cell area and higher injected-charge result in the highest upset probability, while higher cell area and lower injected-charge yield the lowest upset probability. This phenomenon is attributed to the increase in cell area leading to a decrease in the threshold voltage of the cell, resulting in higher charge accumulation. We leverage this phenomenon in the design of a hybrid on-board memory array, where higher-order MSB bits are stored in larger area memory cells, and LSB bits are stored in smaller area cells to optimize power, area efficiency, and Qc. In Section V, we delve into the proposed cell design for the hybrid array. Initially, we design the cell for the hybrid memory array based on research findings that indicate the failure of conventional 6T cells for high Qc values. Therefore, we propose a memory cell capable of accumulating a larger charge. The subsequent section provides a detailed description of the proposed cell design.

Figure 3(b) displays the schematic diagram of the proposed 12T SRAM cell we've introduced. This innovative cell comprises a total of 12 transistors, with 8 being NMOS and 4 being PMOS. Specifically, P1, P2, P3, and P4 function as pull-up transistors, while N1, N2, N3, and N4 serve as pull-down transistors. N5, N6, N7, and N8 act as access transistors, under the control of a single word line (WL), which dictates their switching behaviour. There are 4 internal storage nodes A, B, C, and D. this storage node are interconnected with BL and BLB through the access transistors N5, N6, N7, and N8. When the cell stores a "1," nodes A and C hold the value "1," while nodes B and D retain "0.". This proposed HSRH12T cell boasts support for three distinct operations: hold, read, and write These operations are described below.

Hold Operation: In the hold operation, the WL is maintained in a low state, effectively disconnecting the access transistors N5, N6, N7, and N8 from the bit-lines BL and BLB. These bit-lines are pre-charged to VDD, which reduces the wake-up time. In this state, assuming nodes A and C store logic "1," they maintain this logic level without any change.
Write Operation: In the write operation, the WL is driven to VDD. This action connects transistors N5 and N7 to the BL, while transistors N6 and N8 are connected to the complement BLB. Assuming the desired operation is to write "1," BL is set to VDD, and BLB is set to 0. The high voltage on BL is transmitted to nodes A and C through the access transistors. As a result, the “1” voltage at node "A" activates transistor N4, pulling node D to logic "0." This state on node D, in turn, triggers the P3 transistor, setting node C to "1." With node C at "1," it activates transistor N2, pulling node B to logic "0." This sequence successfully completes the write "1" operation in the proposed cell. To perform a write "0" operation, the switching of the transistors is reversed.
Read Operation: In the read operation, both BL and BLB are connected to the pre-charged VDD supply voltage, while the WL is set to a high level, enabling the access transistors. This activation affects the internal node connected to BL and BLB, causing BLB to discharge through N2 and N4 transistors. As this discharge occurs, a voltage difference between BL and BLB starts to develop, and when it reaches approximately 20% of the supply voltage, it is detected by the sense amplifier. This detection signifies that the memory cell stores the value "1."

The calculated values of t_α = 200 ps, t_β = 50 ps, and I₀= 50 µA indicate the equivalence of a 3fC charge being injected into A,B,C and D sensitive node of the memory cell. Figure 3(c) displays the simulation results for the proposed memory cell when subjected to the applied current pulse model at each sensitive node, which is equivalent to the accumulation of a 3fC charge in space. In this analysis, SEU (Single Event Upset) scenarios for changing the node value from "1" to "0" and "0" to "1" are considered for all sensitive nodes A, B, C, and D within the proposed memory cell.

A Single Event Upset (SEU) event takes place at node A when radiation particles strike the drain region of transistor N1. This event results in the accumulation of negative charge, leading to a change in the voltage signal from "1" to "0" at node A. Consequently, transistor N4 turns off while P1 turns on. With the value of C set to 1, transistor P3 remains OFF, and P4 remains ON. As a result, node D retains its initial value unchanged, and transistor N1 remains OFF. Under these conditions, the voltage change at node A does not propagate to nodes C and D, and they maintain their original voltage states. Eventually, since C is still 1 and D is 0, transistor N2 turns on while N1 remains off. Simultaneously, transistor P2 turns on. Consequently, the voltage at node A undergoes a recovery process and returns to its initial value.

An SEU event occurs at node B when radiation particles strike the drain region of transistor P1. This results in the accumulation of positive charge, causing a node B voltage change from "0" to "1". Consequently, transistor P2 turns OFF while N3 turns ON. Meanwhile, transistor P4 remains ON as the value of D is still 0. The voltage change at node B does not propagate to node D, which remains at 0. In the next steps, transistor N2 turns OFF, and P4 turns ON. Simultaneously, transistor P1 turns OFF, and P2 turns ON. This configuration restores the voltage at node B to its original value. Furthermore, this sequence of events turns OFF P1, turns OFF P2, and turns ON P3.

Because of symmetry in cell structure node C and D recovery same as A and B. so proposed cell recovery successfully when SEU occurs of all the sensitive nodes. In the next section we compared proposed cell with other cells.

In this section, we conduct a comparative analysis of the proposed cell against other radiation-hardened cells CC18T[21], RHC14T[22], RHMC12T[23], SARP12T[24], SRRD12T[25], and PCELL10T[26]. To ensure a fair and meaningful comparison, all SRAM cells are subjected to simulations using the GDPK 45nm CMOS technology. Additionally, for consistency, the size of all transistors in these cells is set to the minimum size of 45nm/120nm. Table 1 provides a feature comparison of each SRAM cell. In the RHMC12T, SARP12T, and SRRD12T employ a two-WL setup to manage memory operations, which results in increased area due to additional circuitry for control. In contrast, the proposed cell maintains the same peripheral circuitry as the standard 6T SRAM cell, its make area efficient. Additionally, it's worth mentioning that SARP12T and SRRD12T utilize active low-control lines, which can consume a significant amount of power in the hold state within the memory array [27]. In this section compare proposed cell with reference well in the aspect of read, write and hold performance.

Table 1

feature Compression of proposed cell with reference cells.
Feature	CC18[21]	RHC14T[22]	RHMC12T[23]	SARP12T[24]	SRRD12T[25]	PCELL[26]	PROPOSED
No.of transistors	18	14	12	12	12	10	12
NMOSs	12	10	6	10	4	4	8
PMOSs	6	4	6	2	8	6	4
Sensitive nodes	6	4	4	4	4	4	4
Control Lines	1	1	2	2	2	1	1

A. Read Performance:

In this section, we evaluated the read performance of all the cells based on two key parameters: read access time (RAT) and read static noise margin (RSNM).

Read Access Time (RAT)

measures the time required for the completion of a read operation. It is defined as the interval between when the WL voltage reaches 50% of the supply voltage (VDD) and when the voltage difference between the bit lines (BL and BLB) reaches VDD/2, as depicted in Fig. 4(d). Minimum RAT is essential for fast memory access. An SRAM cell's RAT primarily relies on the read current and bit line capacitance. Among the cells studied, the proposed, RH12T, CC18T, and RHMC14T exhibit the same and lowest RAT, achieving 773fs at a 1V supply voltage. This remarkable performance is attributed to the bit-lines being connected to two or more internal storage nodes, enhancing the read current and decreasing access time. In comparison, the SRRD12T cell experiences the highest delay, with a read access time of 8.66ps. This delay can be attributed to the presence of PMOS access transistors and a cascading structure of PMOS transistors in the read path, which makes it slower than the other cells. Figure 4(a) illustrates the RAT with different power supplies at a temperature of 27°C, TT corner. Figure 4(b) provides RAT data at a one-volt supply voltage, TT corner, within a temperature range of -25 to 125°C, where the SRRD12T cell exhibits the highest temperature variations compared to the other cells. Figure 4(c) offers a process corner analysis of all the cells, with "slow-slow"(ss) being the worst process corner. Across all these simulations, the proposed demonstrates the lowest RAT. Finally, Fig. 4(d) showcases the results of a Monte Carlo simulation for the proposed cell, based on 1000 samples for RAT at 1 volt and 27°C temperature, TT corner. Mean 0.78ps and standard deviation 0.010ps calculations which shows proposed cell are working in under 3σ condition.

Read static noise margin (RSNM)

The RSNM represents the maximum DC voltage that can be applied to the circuit during reading without causing any alteration or flipping of the data stored at internal nodes [28]. This parameter holds paramount importance in the stable design of SRAM cells, ensuring robust noise immunity. A higher RSNM value is desirable for enhanced noise tolerance. To calculate RSNM, we employ the butterfly curve method [29]. This method involves identifying the largest square that can fit within the curve and measuring its diagonal length, which corresponds to the RSNM, as depicted in Fig. 5(d). For our simulations, we consider the primary storage nodes of all the cells. Figure 5 presents the simulation results of RSNM, considering variations in supply voltage, temperature, and process corner. Figure 5(d) provides insights from a Monte Carlo simulation involving 1000 samples, along with calculated 281.28mV mean and standard deviation values.

Read performance comparison

To compare cells with the proposed cell, we utilize the formula provided in Eq. 2. Table 2 presents a comparison of RAT and RSNM at a 1-volt supply voltage and a temperature of 27°C in the TT corner. Among the compared SRAM cells, the proposed cell shares the same RAT performance as CC18T, RHC14T, and PCELL SRAM cells. However, it distinguishes itself by achieving the highest RSNM among all the considered cells. Specifically, when compared to the proposed cell, CC18T has 66.8% less RSNM, RHC14T has 72.02% less RSNM, RHMC12T showcases 77.03% less RSNM, and PCELL has 6.73% less RSNM. Notably, only two cells, SARP12T and SRRD12T, match the proposed cell's substantial noise margin. However, it's important to highlight that while SARP12T achieves 97.93% more RAT than the proposed cell, SRRD12T significantly outperforms in RSNM, albeit at the cost of slower speed due to the presence of a large number of PMOS transistors in its read path.

$$\varDelta =\frac{Compared cell-Proposed cell}{Proposed cell} \times 100\%$$

2

Table 2

Read performance comparison.
Cells	RAT (ps)	ΔRAT (%)	RSNM (V)	ΔRSNM (%)
CC18T	0.77	0%	0.09	-66.80%
RHC14T	0.77	0%	0.08	-72.02%
RHMC12T	1.75	126.39%	0.06	-77.03%
SARP12T	1.53	97.93%	0.31	10.63%
SRRD12T	54.90	7002.20	0.49	74.20%
PCELL	0.77	0%	0.26	-6.73%
PROPOSED	0.77	-	0.28	-

B. Write Performance:

For the write operation, write delay and write static noise margin are the most important parameters for SRAM cells. A low value of WD is preferable for high speed write operations. During write operations, how much noise is eliminated is shown by the write static margin. For high noise elimination, its value is high.

Write Delay (WD)

Is defined as the time gap between two critical events the moment when the WL voltage reaches 50% of VDD and the point when the storage node voltage experiences a disturbance of 50% of VDD. This definition is illustrated in Fig. 6(d). Figure 6(a) presents the WD under various supply voltage conditions at a temperature of 27°C in the TT corner. Notably, RHC14T, RHMC12T, and SRRD12T exhibit a failure to perform write operations at supply voltages as low as 600 mV. Figure 6(b) illustrates WD at different temperatures while maintaining a 1-volt supply voltage in the TT corner. For diverse process corners, Fig. 6(c) displays simulation results for the proposed cell, with the FF corner representing the most challenging scenario. Lastly, in Fig. 6(d), 1000 Monte Carlo simulation results are provided, with 19.45ps mean and standard 0.18 ps deviation values for WD.

Write margin (WM): The effectiveness of an SRAM cell in writing data is determined by its capacity to switch the states of data storage nodes. Recent research has highlighted the significance of WM as a more precise metric for assessing an SRAM cell's ability to write data [27]. To calculate WM, we measure the difference between VDD and the WL voltage when Storage node A and its complement B intersect, as depicted in Fig. 7(d). Here are the key findings from our simulations: Fig. 7(a) presents simulation results for WM under varying supply voltage conditions at a temperature of 27°C, specifically in the TT corner. Figure 7(b) and Fig. 7(c) display WM results at different temperatures and corners, respectively. In Fig. 7(d), we provide insights from a Monte Carlo simulation involving 1000 samples, along with 717.2 mean and standard 14.71 deviation values for WM.

Write performance compression: Table 3 provides a comprehensive comparison of WD and WM at a 1-volt supply voltage, 27°C temperature, and TT corner. Additionally, we have calculated Δ for both WD and WM, highlighting the differences between the proposed cell and the other SRAM cells: Compared to the proposed cell, CC18T exhibits 22.28% more WD. RHC14T shows a substantial increase in WD at 277.20% more than the proposed cell. RHMC12T exhibits a significant increase in WD, measuring 297.41% more than the proposed cell. SRRD12T demonstrates the highest increase in WD, with a notable 315.54% more delay than the proposed cell. PCELL cell presents 86.01% more WD when compared to the proposed cell. SARP12T, on the other hand, displays a 11.40% reduction in WD compared to the proposed cell, attributed to its internal nodes storing weaker values, which aids in reducing WD. In terms of WM PCELL achieves the highest WM, surpassing the proposed design by 11.63%. SRRD12T shares the same WM as the proposed cell, despite having the largest delay among all cells. These findings illustrate the trade-offs between WD and WM in various SRAM cell designs, showcasing the unique strengths and weaknesses of each.

Table 3

Write performance comparison.
	WD (ps)	ΔRD (%)	WM (mV)	ΔWM (%)
CC18T	23.60	22.28	722.00	0.00
RHC14T	72.80	277.20	745.00	3.19
RHMC12T	76.70	297.41	716.00	-0.83
SARP12T	17.10	-11.40	716.00	-0.83
SRRD12T	80.20	315.54	722.00	0.00
PCELL	35.90	86.01	806.00	11.63
PROPOSED	19.30	-	722.00	-

C. Hold Margin:

Hold Static Noise Margin (HSNM) is a measure of how much noise can be tolerated during hold operations. To calculate this butterfly curve method, simulation results are shown in Fig. 8 for (a) different supply voltage, 8(b) temperature and 8(c) different process corner. SRRD12T has highest hold noise margin and PCELL second highest HSNM and rest of cell approximately has same HSNM. And rest of cell experience approximately same amount of HSNM. Figure 8(d) Proposed cell Monte-Carlo simulation 1000 samples for HSNM at 1v/27^oC/TT.

D. Area:

Figure 9 displays the layout of the proposed cell, which has an area of 3.2µm². In Table 4, the areas of all compared cells are listed, with CC18T having the largest area at 6.58µm². Among all the cells, the proposed cell has the smallest area. This is because RHMC12T, SRRD12T, and PCELL contain a greater number of PMOS cells, which contribute to an increase in the overall cell area as shows in Fig. 10(a).

E. Critical charge:

For critical charge analysis double exponential current pulse is applied at critical nodes In Fig. 10(b) calculate Qc form Eq. 1 and observed proposed cell has 3fc Q_c CC18T has highest Q_c as time its required 18 transistor with produce large area overhead for memory array as shows in Table 4. RHMC12T has second highest Q_c but vary small RSNM (60mV) which make its less reliable for noise environment during read operation RHC12T has approximately same Q_c and rest of all cell are less Qc than proposed cell.

As observed in the above comparison, the proposed 12T cell demonstrates better performance compared to other cells, especially in terms of lower delay, making it the ideal choice for on-board image compression memory. In the next section, we will discuss how the proposed cell is utilized in a hybrid memory array.

Table 4

HSNM, power and Critical Charge comparison.
Cells	Area (µm²)	Qc (fc)
CC18T	6.588	4.01
RHC14T	4.541	3.00
RHMC12T	3.892	3.06
SARP12T	3.245	3.39
SRRD12T	4.875	2.41
PCELL	3.565	2.78
PROPOSED	3.245	1.94

In section II (Fig. 3(a)) observe that the upset probability depends on SRAM cell size if size is large its capable to resist large charge. For this we take two cases in one case take all transistor width size at 120n, and for second case transistor width size is taken 240n. In Table 5 shows critical charge, hold power and upset probability. To calculate upset probability 3fc charge is injected at sensitive storage node and run 1000 Monte-Carlo simulation and find ratio of fail samples to total samples.

Table 5

Critical charge, hold power and upset probability compression for proposed cell with all transistor size 120nm and 240nm.
Cell	Critical charge Q_c(fc)	Hold Power (pW)	Area (µm²)	Upset probability for 3fc critical charge
All transistor width 120n	3	22	3.245	30%
All transistor width 240n	5.1	34	5.568	1%

the relationship between SRAM cell area and Q_c is a crucial consideration in SRAM cell design. there is an inverse relationship between the SRAM cell area and Q_c. As the size of the SRAM cell increases it typically becomes more robust against SEUs caused by radiation or other external factors. Larger cells tend to have a higher Q_c requirement, meaning they require more energy to upset the stored data. Larger SRAM cells can store more charge in their nodes, making them less susceptible to disruptions caused by external events like radiation strikes. This increased charge storage capacity results in a higher Q_c requirement. However, increasing the SRAM cell area comes with trade-offs, such as increased power consumption, reduced density on the chip, and potentially slower access times. a balance between cell size, Q_c, and overall SRAM performance to meet the specific requirements. Table shows 8bit image pixel MSBs bits are store in larger size and LSBs bits are stored in smaller SRAM cell. And observed if how many bits are stored in larger size cell form increasing order like zero to all bits are stored in larger SRAM cell. Additional observed power dissipation and area of total 8bit memory array and up-set probability and find out optimized solution as shows in Fig. 11(a). 4bits MSBs are stored in 240nm transistor size cell and 4 LSBs bits are stored in 120nm transistor size cell.

Table 6

MSB bit position in 8 bit memory array and its effect on Power dissipation, memory aera and upset probability.
Number of MSBs bits are stored in large size SRAM cell	Power dissipation of 8 bit memory array (pw)	Area of 8 bit memory array (µm²)	Upset probability
0	176	26.24	30
1	188	28.528	26.375
2	200	30.816	22.75
3	212	33.104	19.125
4	224	35.392	15.5
5	236	37.68	11.875
6	248	39.968	8.25
7	260	42.256	4.625
8	272	44.544	1

Table 7

all the parameters comparison at 1volt/27^oC/ TT corner
	RAT(ps)	RSNM (mV)	WAT(ps)	WM(mV)	HSNM (mv)	Area (µm²)	Qc(fc)
CC18T	0.77	92.80	23.60	722.00	320.30	6.588	4.00
Proposed	0.77	280.00	19.30	780.00	330.60	4.541	3.00
RHC14T	0.77	78.20	72.80	745.00	322.90	3.892	3.06
RHMC12T	1.75	64.20	76.70	716.00	341.50	3.101	3.39
SARP12T	1.53	309.20	17.10	716.00	334.20	4.875	2.41
SRRD12T	86.60	486.90	80.20	722.00	435.50	3.565	2.78
PCELL	0.77	260.70	35.90	806.00	411.30	3.245	1.94

In table calculate all the parameters how are explain in above section are illustrated at 1volt VDD. For Image space on-board application memory cell its effectiveness is determined by Qc, but this is not only one parameter other also affect its. Factor such as RSNM, WM, HSNM, area, RAT and WD are important design constrain. However, enhancing one design parameter may come at the expense of others. If VDD increasing improving noise margins, delays and Qc, but this also results in higher power consumption. Similarly, enhancing Qc through larger transistors increases area usage. In this regard, introduce an electrical quality metric (EQM) based on Pal et al.'s [24] work, which offers an estimation of an SRAM's overall performance by considering these major design metrics.

$$EQM=\frac{{Q}_{c}\times RSNM\times WM\times HSNM}{RAT\times WD\times Area}$$

3

A higher EQM signifies superior overall performance. In Fig. 11(b), the normalized EQM values for all the compared cells are depicted, and it's evident that the proposed cell boasts the highest EQM. A higher EQM in an SRAM cell is indicative of its superior overall performance. Our simulation results affirm that, when operating at a VDD of 1 volt, the proposed cell consistently outperforms other cells.

In conclusion, our research has focused on the design and evaluation of a hybrid memory array for on-board SRAM memory used in image compression in satellite systems. This hybrid memory array has been developed to address the challenges posed by radiation-induced errors, memory size optimization, power efficiency, and reliability in space environments. Our investigation into SEUs highlighted the vulnerability of conventional SRAM cells to radiation-induced errors in space. We conducted a thorough analysis of Q_c and upset probability, revealing the importance of cell size in mitigating SEUs. This insight guided the design of our hybrid memory array, where larger cells store high-order MSBs, and smaller cells store LSBs, achieving a balance between data integrity, resource efficiency, and Q_c. Comparative analyses of our proposed cell against existing radiation-hardened cells demonstrated its superior performance in terms of RAT, WD. The proposed cell exhibited excellent overall performance and reliability in the face of SEUs, making it a promising solution for on-board SRAM memory in satellite image compression applications. Furthermore, we introduced an EQM to comprehensively assess SRAM cell performance by considering Q_c, noise margins, write margin, hold margin, power efficiency, read and write delays, and area efficiency. Our results showed that the proposed cell 3.66x/5.02x/8.33x/1.73x/65.12x/1.19x achieved the highest EQM compare to CC18T/RHC14T/RHMC12T/SARP12T/SRRD12T/PCELL10T respectively. Affirming its superiority in overall performance. In summary, our research contributes to the advancement of memory cell design for space applications, particularly in the context of image compression in satellite systems. The hybrid memory array we propose offers a practical and efficient solution that balances various design constraints while ensuring robustness and reliability in challenging space environments. This work lays the foundation for improved satellite image compression systems, further enhancing the capabilities of satellite technology across various sectors.

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No competing interests reported.

Design a Hybrid Memory Array for Radiation-Hardened SRAM in Satellite Image Compression Systems

Status:

Version 1

Abstract

Figures

I. Introduction

II. Single event upset and analysis

III. Proposed cell

IV. Performance comparison of proposed cell with other radiation harden cells:

V. Hybrid memory array

VI. Simulation results

VII. Conclusion

References

Additional Declarations

Status:

Version 1