Solution processed low-voltage metal-oxide transistor by using TiO2/Li–Al2O3 stacked gate dielectric

A solution processed top-contact bottom-gated SnO2 thin-film transistor (TFT) has been fabricated using a TiO2/Li–Al2O3 bilayer stacked gate dielectric that show operating voltage of this TFT within 2.0 V. It is observed that the bilayer dielectric has much higher areal capacitance with lower leakage current density that significantly improve the overall device performance of TFT. The TFT with bilayer gate dielectric shows an effective carrier mobility (μsat) of 9.2 cm2 V−1 s−1 with an on/off ratio of 7.1 × 103 which are significantly higher with respect to the TFT with a single layer Li–Al2O3 gate dielectric. The origin of this improvement is due to the Schottky junction between the highly doped silicon (p++-Si) and TiO2 of bilayer stacked dielectric that induced electrons to the channel which reduces the dielectric/semiconductor interface trap-state. This investigation opens a new path to develop TFT device performance using a suitable bilayer stack of gate dielectric.


Introduction
The charge carrier conduction of the channel of a thin-film transistor (TFT) normally occurs within \10 nm thickness of the semiconductor film next to the gate dielectric [1]. Therefore, the field effect charge transport phenomena of a TFT is not only dependent on the microstructures of the semiconductor but is also strongly affected by the surface properties of the gate insulator [2]. Conventional silicon gate dielectric (SiO 2 ) commonly offers smooth surface morphology which is capable of minimizing the defect density of semiconductor-insulator interface. However, the dielectric constant of SiO 2 is very low (3.9). Therefore, to reduce the operating voltage of a TFT below 2 V for portable electronics application, it requires very low thickness of SiO 2 (\10 nm) which sometime becomes very leaky [3,4]. Employment of high-k dielectric materials instead of SiO 2 is the best alternative which allow us to deposit thicker dielectric film by maintaining the advantage of low operating voltage TFT fabrication [5][6][7][8][9]. However, ionic bonds in high-k dielectrics results in high defect concentrations with oxygen vacancies (V O ) being the primary source of traps. These can be source of fixed charges or act as electron traps that decreases the effective carrier mobility of the device. Moreover, this trap-states can change the threshold voltage (V T ) of the device and increases the gate-leakage current [10], decreasing device performance and the stability of devices. To overcome these problems, different approaches like inorganic-organic hybrid dielectric [11,12], multicomponent dielectric [13], bilayer dielectric stack [14][15][16], composite solid polymer electrolyte (CSPE) [17] have been used. Many of these dielectrics are solution processable and can be printed by different printing technique [18]. To reduce the semiconductor/dielectric interface trap-state, recently, a new method has been developed by implying n-type TiO 2 as interface layer between highly doped silicon (p ?? -Si) substrate and high-k ion conducting Li 5 AlO 4 dielectric, which drastically enhance the TFT device performance due to the formation of Schottky junction of p ?? -Si/TiO 2 [19]. However, capacitance of that Li 5 AlO 4/ TiO 2 stacked dielectric reduce rapidly above 10 4 Hz [19]. To enhance the frequency range and overall performance of TFT, more detailed study is required for different combinations of stacked dielectric.
In this work, we have synthesized Li-doped alumina (Li-Al 2 O 3 ) thin film by sol-gel method and have used this ionic dielectric to fabricate TiO 2 /Li-Al 2 O 3 stacked gate dielectric. The variation of areal capacitance of this bilayer stacked gate dielectric reduces only by 20% up to the frequency 10 5 Hz. To realize the overall improvement of TFT performance and the mechanism of this development, two sets of solution processed SnO 2 TFT were fabricated; one with TiO 2 gate interface and another without gate interface. Comparative studies of these two TFT reveals a significant improvement of device performance. A schematic presentation of energy bandgap of multilayer thin films and related charge transfer of p ?? -Si/TiO 2 Schottky junction explain the probable reason for enhancing device performance.

Material synthesis
As mentioned earlier, all TFTs are fabricated by lowcost solution processed technique. In this process, both gate dielectric (TiO 2 and Li-Al 2 O 3 ) and semiconducting layers (SnO 2 ) are deposited from the precursor solution by spin coating method. For TiO 2 deposition, a solution of 100 mM was prepared by dissolving Titanium(IV) Butoxide in 2-methoxy ethanol (2ME) followed at the room temperature stirring process by a magnetic stirrer about 30 min. Similarly, to prepare the Li-Al 2 O 3 dielectric, two different solutions of lithium acetate and aluminium nitrate nonahydrate of concentration 500 mM were prepared using 2-methoxy ethanol as solvent. These two homogeneous solutions are mixed with a ratio of 1:11 to maintain the atomic ratio of the final product of Li-Al 2 O 3 . This mixture of solutions was left for 24 h for proper gelation before deposition [20]. Finally, solution was filtered by 0.45 lm PVDF filter before spin coating. For semiconductor (SnO 2 ) thin-film deposition, a solution of SnCl 2 has been prepared using 2-methoxy ethanol as solvent.

Device fabrication
Metal-oxide TFTs are fabricated in a top-contact bottom-gate configuration using highly p-doped Si wafer (p ?? -Si) as a substrate as well as gate electrode. Initially, all the Si wafers are cleaned with standard cleaning process. After wet cleaning, wafers were treated with an oxygen plasma for 10 min before spin coating. Plasma treatment makes the surface hydrophilic which increases the adhesive property and helps to form pinhole-free smooth film during spin coating. Two types of devices are fabricated without and with TiO 2 interface named as Device 1 and Device 2 shown in Fig. 1a and b, respectively. The TiO 2 thin film is deposited on p ?? -Si wafer spin coating with a spinning speed of 3500 rpm for 40 s followed by a drying process of a preheated hot-plate (set at 90°C) to evaporate the solvent. Afterwards, this film was annealed at 350°C for 30 min to form a polycrystalline thin film of TiO 2 . On top of this, the precursor solution of Li-Al 2 O 3 was spin coated with a speed 5000 rpm for 50 s followed by annealing process at 350°C for 30 min. The dielectric film coating was repeated three times to achieve a desired thickness of the dielectric layer. Finally this film was annealed at 500°C for 1 h to form Li-Al 2 O 3 thin film. For Device 1, the same procedure was followed except the TiO 2 layer deposition. After dielectric deposition, the precursor solution of SnO 2 was spin coated (4000 rpm for 40 s.) and subsequent annealing (500°C for 30 min) process [17]. Finally, aluminium source/drain electrode are deposited by thermal evaporation method with width-to-length ratio of 118 (23.6 mm/0.2 mm). In addition to this TFT fabrication, the metal-insulator-metal (MIM) devices ( Fig. 1c and d) were fabricated in a similar process for the electrical characterization of single and bilayer dielectric thin films.

Material and device characterization
Crystal phase/structural analysis of thin films were carried out by grazing incidence XRD (Rikagu, Smart Lab) with monochromatized Cu Ka radiation (k = 1.5405 Å ). Atomic force microscopy (AFM) study has been performed using ''NTMDTNTEGRA-prima'' to measure the roughness of different thin-film surfaces. Thin films are deposited on p ?? -Si substrate in both cases. Frequency vs. capacitance (C-f) measurement has been done by LCR meter (Keysight LCR meter E4990A). All the electrical characteristics of TFTs and leakage current measurement of MIM devices have been measured by semiconductor parameter analyzer (KEYSIGHT B1500A).

Surface morphology of dielectric thin films
The surface morphologies of single layer Li-Al 2 O 3 and bilayer TiO 2 /Li-Al 2 O 3 dielectrics were studied by atomic force microscopy (AFM). All these dielectric layers were deposited on p ?? -Si substrates with the same condition as for TFT fabrication. The 2D and 3D morphologies of these two dielectric thin films are shown in Fig. 3a-d. Figure 3a and

Dielectric and electrical characterization
The leakage current density and areal capacitance of single layer and bilayer dielectric are measured with metal-insulator-metal (MIM) architecture which is shown in Fig. 4. Figure 4a shows the leakage current density vs. applied voltage graphs of both dielectric thin films. This data indicate that stacked dielectric of p ?? -Si/TiO 2 /Li-Al 2 O 3 /Al device has one order lower leakage current density than p ?? -Si/Li-Al 2 O 3 / Al device at applied voltage 2 V with a current density of 6.2 9 10 -5 A/cm 2 , whereas single layer dielectric MIM device shows a current density of 2.0 9 10 -4 A/cm 2 at 2.0 V. The dielectric-leakage current of bilayer film is reasonably low for TFT fabrication that operates within 2.0 V operating voltage. The reduction of gate-leakage current in case of bilayer dielectric may be resulted from the lattice mismatch of two different materials with different grain shapes at the interfaces, which is well understood from the earlier multilayered dielectric studies [16]. The variation of capacitance per unit area of the same set of MIM devices with frequencies (20 to 10 5 Hz) at room temperature are represented in Fig. 4b. It is well known that the capacitance decreases with frequency due to the different relaxation times originated from different types of polarization contribution [7]. Similar behaviour is observed in both types of MIM devices that reduce significantly [ 10 3 Hz. However, the capacitance of single layer p ?? -Si/Li-Al 2 O 3 /Al device changes more rapidly compared to bilayer p ?? -Si/TiO 2 /Li-Al 2 O 3 /Al MIM device. The measured areal capacitance (C) values of single and bilayer MIM devices are 55 nF/cm 2 and 66 nF/cm 2 at 50 Hz frequency, respectively. This study is the indication of the higher areal capacitance value with wider frequency range of a bilayer stacked dielectric thin film which originated from additional TiO 2 layer. The TiO 2 /Li-Al 2 O 3 bilayer act as series combination of TiO 2 and Li-Al 2 O 3 parallel plate capacitor and the resultant capacitance can be written as The high-k value of TiO 2 layer increases the capacitance of TiO 2 /Li-Al 2 O 3 dielectric with respect to Li-Al 2 O 3 single layer.

Electrical characterization of single and bilayer dielectric thin-film transistor
To realize the performance of these dielectric layers for the application of gate dielectric of TFTs, two sets of devices have been fabricated. Device 1 is the reference TFT without TiO 2 gate interface and Device 2 is TFT with TiO 2 gate interface in between gate electrode and Li-Al 2 O 3 gate dielectric. A higher channel length of 200 lm with W/L (W = 23.6 mm, L = 0.2 mm) ratio of 118 is chosen to avoid the overestimation of carrier mobility value due to grain boundary effect, which is highly dominating below 25 lm channel length and W/L ratio of 10 [21,22]. Additionally, high-performance TFT with larger device area demands good quality of dielectric with pinhole-free uniform thin film with very low defect states. Figure 5 shows transistor characteristics of two types of device, and are measured at ambient conditions. The I D -V D characteristics of Device 1 and Device 2 are shown in Fig. 5a and b, respectively. The applied V D are swept from 0 to 1 V with different constant gate voltages ranging from -0.2 to 2.0 V with step of 0.2 V. The linear and saturation region of the output characteristics are clearly shown by the figure for both sets of devices. The transfer characteristics of SnO 2 TFT without and with TiO 2 interface are shown in Fig. 5c and d. The gate to source voltages is swept from -0.2 to 2 V keeping V D constant at 1 V for both devices. All the measurement conditions and parameters are kept the same for all devices. From comparative data of transfer characteristics (Fig. 5e and f), it is observed that the threshold voltage of Device 2 (0.29 V) is sufficiently lower than Device 1 (0.85 V). Besides, the calculated value of I ON /I OFF ratio for Device 2 is 7.2 9 10 3 which is higher than Device 1 (i.e. 3.6 9 10 3 ). The effective carrier mobility (l), subthreshold swing (SS), and dielectric/semiconductor interface trap-states (N Max SS Þ of TFT have been calculated by using the following equations [23]: where k, T and q are the Boltzmann constant, temperature in absolute scale and charge of electron, respectively. The saturation carrier mobilities of both devices are calculated using Eq. 1 and extracted from the linear fitting of (I D ) 1/2 vs. V G plot. From comparison of both devices, it is observed that Device 2 shows better performance having saturation electron mobility of 9.2 cm 2 V -1 s -1 than Device 1 that shows saturation electron mobility of 7.7 cm 2 V -1 s -1 . Besides, we have calculated carrier mobility by considering the 'reliability factor (r lin )' with this calculation that arises due to the faulty capacitance values, erroneous measurement of V T and irregular shape of the I D vs. V G suggested by earlier works which gives only * 3% variation with earlier calculation (Table 1) [24,25]. The subthreshold swing (SS) value of both devices are extracted from the slope at lower gate voltage regime of the log (I D ) vs. V G graphs (shown in Fig. 5e and f and by using Eq. 2). Device 2 has lower SS value (250 mV/decade) than Device 1 (280 mV/ decade). The dielectric-semiconductor interface trapstate densities have been derived from Eq. 3. Device 1 has 1.5 times higher interface trap-state density than Device 2. The lower N Max SS leads to less trapping of charge carriers in the dielectric-semiconductor interface, resulting in improvement of effective mobility and higher drain current [26]. All the TFT parameters are summarized in Table 1.
To understand the reason behind the higher performance of Device 2 with TiO 2 /Li-Al 2 O 3 stack dielectric, a schematic diagram of energy bands of two types of SnO 2 TFTs have been illustrated in Fig. 6. Since p ?? -Si(111)/TiO 2 interface forms a Schottky junction at zero gate bias, the electron of TiO 2 layer transferred to the p ?? -Si gate electrode creates a depleted layer of positive charge at TiO 2 thin film. However, hole is not allowed to transfer from p ?? -Si to TiO 2 layer due to large potential barrier in p ?? -Si(111)/TiO 2 interface [27,28]. Hence, the layer of positive charge of TiO 2 thin film induces electrons of the channel of TFT (SnO 2 ) to accumulate at the Li-Al 2 O 3 /SnO 2 interface, which initially fills up the electron trap-states ðN Max SS Þ at the dielectric/ semiconductor interface (Fig. 6a).
This phenomenon is happening without gate bias. Therefore, TiO 2 thin film effectively reduces the interface trap-states, resulting in a lower subthreshold swing and threshold voltage. Although, these phenomena are not occurring in Device 1 because of the high barrier height of insulating Li-Al 2 O 3 layer. Therefore, electrons cannot be ejected from Li-Al 2 O 3 to p ?? -Si gate electrode (Fig. 6c). Under accumulation mode operation, a positive gate voltage is b Fig. 3    phenomena effectively enhance the accumulation of mobile charge carriers in the channel of Device 2, which improves the device performance over Device 1.

Conclusion
In conclusion, high-performance solution processed low operating voltage SnO 2 thin-film transistor has been fabricated onto sol-gel derived ion-conduction Li-Al 2 O 3 dielectric using TiO 2 gate interface. A comparative study of two sets of SnO 2 TFTs with and without TiO 2 interface have been demonstrated. The Schottky junction formation between p ?? -Si and n-type TiO 2 help to accumulate extra electrons at the Li-Al 2 O 3 /SnO 2 interface, which essentially fills up the interface trap-states and reduces the subthreshold swing (SS) as well as threshold voltage (V T ) and enhance the saturation carrier mobility of the device with compared to the device without TiO 2 interface. The high-k value of TiO 2 improves the capacitance of the TiO 2 /Li-Al 2 O 3 stack dielectric as well as it's leakage current reduced compared to single layered Li-Al 2 O 3 dielectric. We have achieved an effective carrier mobility (l sat ) of 9.2 cm 2 V -1 s -1 , SS of 250 mV/decade, and V T of 0.29 V in TiO 2 /Li-Al 2 O 3 stack TFT with an I ON /I OFF ratio of 7.2 9 10 3 . This investigation opens a new path to develop highperformance TFT devices using a suitable bilayer stack of gate dielectrics.

Data availability
The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.