3.1 Laboratory set-up
Electronics breadboarding combines the three critical elements. The focal plan cold electronics interface simulator, which implements both passive components and active components to amplify (with a factor ~ 1000) the signals. Amplification is necessary to simulate output (scientific) signal. It also allows to perform the crosstalk measurement. The WFEE electronics simulator, with representative interface including buffers, based on the RHF200 component. The cryo-harness simulator between the focal plane interface and the WFEE interface. This set-up has several purposes. The primary purpose is to assess the crosstalk performance of the cryo-harness solution, by measuring crosstalk between wires. The crosstalk is measured between a signal line (active) and a passive signal line. Measurements have been performed on both sides, on the focal plane simulator board and on the WFEE simulator board. Both loom technical solution and shielded twisted pair have been tested. The results obtained with the loom technology are presented in this paper. Secondary purposes of the electronics set-up is to validate the design choices and definition of the electrical interfaces on the WFEE side. Buffer implementation and associated performances can be assessed. Finally, focal plane passive electronics breadboarding will also allow to establish a definition for a tooling interface with representative load, in the frame of the warm electronics testing. The last objective is to correlate obtained results with simulations.
Electronics breadboarding is displayed on Fig. 1. Specific care has been taken for the design of the electronics boards. The leads geometry obeys to specific topology to limit crosstalk between PCB leads and implementation for small connectors to prevent crosstalk at connectors level, in order to be able to measure intrinsic loom crosstalk. The loom definition is compliant with the current instrument design (Gauge xx, distance between pairs around xx). An isolation signal pair is implemented between each signal pair (twisted pairs). Constantan loom have been selected in order to have a serial resistance close to the final flight harness. Two looms variant have been tested with total length of 2 m or 3 m, with impedance characteristics Z0 = 40 Ω / Zseries = 66 Ω/m. The electrical interface definition is co compliant with specifications (differential architecture, representative interfaces on both side at focal plan level and WFEE level),
Test plan has included tests with practical objectives, from RHF200 buffer characterization, electronics board tuning, impact of the interface on the signals, constantan loom characterization (sensitivity to harness length, loom stacking performance, …).
Criteria to assess the performance rely on signal integrity. Signal integrity parameters translate into rising/falling edge time characterization, characterization of the crosstalk of the signals, damping of over/undershoots transients. Electronics definition includes impedance matching to avoid signal propagation associated signal degradations.
3.2 Main results
Measured signal are displayed on Fig. 2. Waveforms, amplitude and delay are consistent with the simulation. The breadboard provides a very stable and reproducible results, which assess the compliance with respect to the requirements. As a worst case, falling and rising edge have been set to 8 ns at WFEE board input. The bandwidth of the signal is measured at different levels and is consistent with simulations (~ 20 MHz). The set-up show no signal oscillations, which confirms that the resistive harness provides an efficient damping. In the 160 ns time period, the end of the settling transient needs to be stable, as readout requirements lead to sample the signal in the last 40 ns. The signal integrity results validates the interface choices at WFEE output.
Figure 3 shows the signal on an adjacent line to the signal line after amplification. The ratio between the two signals provide an estimate of the crosstalk at FPA input, of the order of 66dB. At WFEE input, the obtained crosstalk figure is ~ 77dB.
Measurments have been performed in the frequency domain, to corroborate the results with the crosstalk figure obtained in the time domain. Calculations have been conducted to verify the consistency of both set of data, e.g data acquired in the time and frequency domain. This was performed through a dedicated campaign, by injecting sine waves at selected frequencies (see Fig. 5). The crosstalk level has been measured both by comparing the peak amplitude of the victim line in time domain (orange line) and by comparing the ratio of the power spectrum densities (PSDs, blue line) of the input and victim signal at the investigated frequency value. A further comparison has been performed using a spectrum analyser on the set-up (green line). All three methods show excellent consistency over the 0.1–100 MHz range, confirming the results obtained through simulation. Finally, a correlation with LTspice simulations have been performed which allows a rescaling of the parasitic capacitance with realistic values