Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement. The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. The proposed design has 100% tolerance to the fault of a single missing cell and 71.43% tolerance to the rotation of one cell. The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell.


Introduction
Today, metal-oxide superconductor technology has extensive application in the production of digital circuits and chips. This technology, like many others, involves making a tradeoff between speed and power consumption (Lent et al. 1993;Wilson et al. 2002).
In the near future, complementary metal-oxide-semiconductor (CMOS) technology is expected to reach the end of its way due to limitations such as switching speed, scaling specifications, high cost of lithography and thermal challenges (Toth and Lent 1999). CMOS technology also suffers from lower tolerability and manufacturing diversity, which Since the two electrons within each cell repel each other until reaching the lowest energy state, as shown in Fig. 2, there could only be two stable states for each cell (Sen et al. 2014;, 2021Bilal et al. 2018;Afrooz and Navimipour 2017;Fam and Navimipour 2019).
In the base state when there is no external force, the Coulomb repulsion of the electrons pushes them into opposite corners of the QCA cell, where they will be as far as possible from each other. Hence, there are only two possible states for a QCA cell. As shown in Fig. 2, these two states are known as P = + 1 or P = − 1 and represent the binary values of "1" and "0" respectively (Lent et al. 1993;Rahmani et al. 2021;Raj et al. 2020;Rahimpour Gadim and Navimipour 2018;Hasani and Navimipour 2021. The basic building blocks of QCA circuits are wires, majority gate (vector) and inverter. There are two types of wire in QCA circuits: 90° and 45°. The 45° wire is a wire of base cells that are rotated at 45° (Fig. 3) (Ahmadpour and Mosleh 2018;Norouzi and Heikalabad 2019;Safoev et al. 2021;Norouzi et al. 2020). In Fig. 4 shown the typical layouts of majority gate and inverter (Sen et al. 2014). All of these structures are based on cellular interaction. The basic structure realized with QCA is the 3-input majority gate, MV(A, B, C) = Maj (A, B,C) = AB + AC + BC. The majority gate can also function as a 2-input AND or a 2-input OR by fixing one of the three input cells to P = − 1 or p = + 1 respectively (Sen et al. 2016b). Inverters are realized in two different orientations as shown in Fig. 4b. In these layouts, the inverse polarity of the input cell is transmitted to the output (Moghimizadeh and Mosleh 2019;Salimzadeh and Heikalabad 2021;Salimzadeh et al. 2021;Salimzadeh and Heikalabad 2019;Rahimpour Gadim and Navimipour 2018).
In QCA circuits, the movement of electrons inside the cells is controlled by the Clock. This component makes sure that the data is flowing in the right direction and also synchronizes the combination of data incoming from different branches. In other words, in conjunctions where multiple inputs should be combined to produce an output, the clock holds the data that arrive earlier in place until all data necessary for the combination arrive at the conjunction. The clock can be applied to groups of cells (clock zones). In each zone, a set of QCA cells based on their placement are doing a certain operation and its output is used as input to the next clock zone. Each clock consists of four phases ( 1. Switch: the cell becomes depolarized and gradually transforms according to the state of the input or preceding cell. 2. Hold: the cell maintains a high energy level and remains active to serve as an input for the subsequent cell. 3. Release: with a gradual decrease in the energy level, the cell loses its effect on its adjacent cells. 4. Relax: the cell loses all of its energy and reaches a stable state.

Related works
In this section, we briefly review the existing solutions for improving the fault tolerance of majority gate circuits. The designs previously proposed for this purpose are displayed in Fig. 7. These designs have used different methods to improve fault tolerance. In most of these solutions, fault tolerance is improved by adding additional cells to strategic positions within the majority gate. Other solutions have repositioned inputs or output or have used cell rotation to improve fault tolerance. Das and De (2010) proposed a fault tolerant three input majority gate with 13 cells and occupied area of 0.0096 μm 2 , which is 55% fault tolerant to the single cell omission (Fig. 7a).  Kumar and Mitra (2016) provided a fault tolerant three input majority gate with 20 cells and occupied area of 0.0139 μm 2 , which has a tolerance of 87.5% and required two clock phases (Fig. 7b).
Other design presented by Dysart et al. (Dysart et al. 2017) in 2017. This is designed with 21 cells and occupied area of 0.0096 μm 2 that has 82.25% fault tolerance (Fig. 7c).
Huakun et al. (2016) introduced a fault tolerant three input majority gate with 19 cells and occupied area of 0.0135 μm 2 which has 60% tolerance to the single cell omission (Fig. 7d).
In 2018 majority gate structure provided by Hosseinzadeh and Rasouli Heikalabad with 16 cells and occupied area of 0.0076 μm 2 . The results show that this structure provides 100% fault tolerance under one missing cell defect. It also provides 54.5% fault tolerance under two missing cells defect (Fig. 7e). Beard (2006) in 2006 proposed a fault tolerant three input majority gate with 32 cells and occupied area of 0.0210 μm 2 , which has 64.29% fault tolerant to the single cell omission defect (Fig. 7f). One of the problems in this gate is low fault tolerant. Sun et al. (2018) provided a fault tolerant three input majority gate with 25 cells and occupied area of 0.0096 μm 2 , with up to 80.95% fault tolerance (Fig. 7g). Sen et al. (2016b) proposed a fault tolerant three input majority gate with 43 cells and occupied area of 0.0388 μm 2 , which is 97.44% fault tolerant to the single cell omission defect (Fig. 7h). One of the problems in this gate is the large number of cells, which increases the complexity of the QCA circuits.
Other design presented by Ahmadpour and Mosleh (Dysart et al. 2017) in 2018. This fault tolerant gate is including 27 cells and occupied area of 0.0096 μm 2 . The proposed structure was 100% fault tolerant under single cell omission and 100% fault tolerant under extra cell deposition defects (Fig. 7i). One of the problems in this gate is the large number of cells, which increases the complexity of the QCA circuits.

Proposed majority gate design
This section introduces the proposed majority gate design developed for improved fault tolerance. After the introduction, the simulation results are presented and the design outputs in different states are examined. The proposed majority gate design is shown in Fig. 8. The proposed gate consists of 11 cells and requires an area of 0.0096 μm 2 . In this gate, three cells called A, B and C are inputs, the cell called OUT is output and the remaining cells are intermediate cells. Blue cells are input cells, green cells are device cells and yellow cell is output cell. The proposed structure was simulated with the parameters listed in Table 1 using the software QCA Designer. Figure 9 presents the simulation results of the proposed three input majority gate. In two cases with different inputs, the operation of the proposed gate is examined. As can be seen, when the inputs are 100, the output is 0 and when the inputs are 111, the output is 1. This operation is exactly according to the operational equation of the majority gate. The AND and OR gates developed based on the proposed structure are shown in Fig. 10a and b. Blue cells  are input cells, green cells are wire, yellow cells are output cells and orange cells represent the binary values of "1" and "0" respectively. The results of the simulation of these gates are presented in Fig. 11. As highlighted on the result of AND gate, the output is only 1 when both inputs have a value of 1. Also, as highlighted on the result of OR gate, the output is only 0 when both inputs have a value of 0. The proposed design has 100% tolerance to the fault of a single missing cell (Table 2a) and 71.43% tolerance to the rotation of one cell (Table 2b). The tolerance of the design to cell displacement is described in Table 3. Also, addition a cell fault to the grid will make no change in the output of the proposed majority gate. Tables 4 and 5 demonstrate the physical fault tolerance of the design for the state shown in Fig. 12.
In cells i and j, the electrostatic energy between two quantum dots can be calculated using the following: The parameters ε 0 , ε r , q n i respectively show the vacuum permittivity, dielectric constant and the amount of charge in the quantum dot n in cell r n i . In addition, parameter i indicates the   location of quantum dot n in cell i and | | | r m i − r n j | | | is the distance between cells. By considering the influence radius of the electrostatic energy equals to 56 nm, the Kink energy is calculated for both states of output cell (Hosseinzadeh 2018). In Fig. 12a the influence radius is considered. The output cell energy in two states is obtained by mentioned equations and the results are presented in Tables 4 and 5. Due to the fact that a cell with the least amount of energy is in a stable state, it can be said that the cell is more stable in states with less numerical values in the calculations. By considering the Table 5, state (c) in Fig. 12 has the least numerical value, which indicates cell deletion has no effect on output. When a cell is lost, the electrostatic energy of each cell and its effect on output is calculated by (5), (6) and (7) to compute kink energy.
(2) U = kq 1 q 2 r  In Table 6, the proposed majority gate is compared with the existing designs in terms of the number of cells, area requirement and fault tolerance. As Table 6 demonstrates, the proposed design enjoys a better performance than the existing designs.

New multiplexer based on the proposed majority gate
This section first reviews the existing multiplexer designs, then presents a 2-1 multiplexer and a 4-1 multiplexer designed based on the proposed majority gate. At the end of the section, the proposed multiplexer compared with the existing designs. The existing designs for 2-1 multiplexers are shown in Fig. 13.    Figure 14 presents the 2-1 multiplexer designed based on the proposed majority gate. The output function of this multiplexer is shown in Eq. 5: The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm 2 . The simulation results obtained for this multiplexer are presented in Fig. 15. As can be seen from the simulation result, when input S is 0, input A is transferred to output and when input S is 1, input B is transferred to output.
This multiplexer has 95.24% tolerance to the fault of a single missing cell. For example, if the pointed cell in Fig. 16 is removed, the multiplexer circuit will not respond well and the output will be as shown in Fig. 17.
The 4-1 multiplexer designed based on the proposed majority gate is shown in Fig. 18. This multiplexer has 85.71% tolerance to the fault of a single missing cell.
In Table 7, the proposed 2-1 multiplexer is compared with the existing designs. As the simulation results presented in Table 7 demonstrate, the proposed 2-1 multiplexer exhibits significant superiorly over the existing designs in term of the number of cells, area requirement and fault tolerance.

Conclusion
In this article, we first provided a brief introduction to QCA technology and challenges in the fabrication of QCA circuits and discussed the existing solutions for resolving these challenges. We then presented a new solution for improving the tolerance of three input majority gate to the faults of single missing cell, single additional cell, single cell rotation and single cell displacement. The proposed idea was then used to design new 2-1 multiplexer and 4-1 multiplexer. The simulation results demonstrated the significantly improved fault tolerance of the proposed solution for three input majority gate compared to the existing designs. The multiplexer designed based the proposed majority gate also showed significant superiority over the existing designs in terms of fault tolerance and area requirement. In future works, the proposed majority gate can be incorporated into the design of flip-flops, decoders, hybrid circuits and sequential circuits. The proposed multiplexer can be used in the design of memory cells for RAMs.