Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.
Research Article
Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata
https://doi.org/10.21203/rs.3.rs-355476/v1
This work is licensed under a CC BY 4.0 License
You are reading this latest preprint version
Quantum dot Cellular Automata
Fault Tolerance
Majority Gate
Multiplexer
Today, metal-oxide superconductor technology has extensive application in the production of digital circuits and chips. This technology, like many others, involves making a tradeoff between speed and power consumption. New technologies such as carbon nanotube field-effect transistor (CNTFET) and quantum dot cellular automata (QCA) have been able to facilitate the fabrication of faster, more compact, and more energy-efficient circuits with parallel processing capabilities[1,2].
QCA is a nanotechnology computing architecture originally developed by Dr. Craig Lent and his colleagues in 1993[1]. In this architecture, some concepts of quantum mechanics such as tunneling are utilized in the fabrication of potential barriers for cellular automata[3,4]. The core idea of QCA originates from the concept of artificial semiconductor atoms, which allows for the implementation of digital components in the nanoscale[13,14].
There are however several challenges in implementing QCA technology, which include fabrication faults appearing as missing cells, additional cells, cell displacements, and cell rotations. Missing cell refers to the absence of one or more cells from the grid. Cell displacement refers to the situation where one or more cells are not exactly in their expected position. Rotation cell refers to when a cell rotates in its place [5-12,16,17,22,29].
This article is mainly focused on the challenge of addressing missing cells. In the remainder of this article, the principles of QCA are introduced in Section 2. The existing solutions for dealing with missing cells are reviewed in Section 3. The proposed design for a fault tolerant three input majority gate is presented in Section 4. In Section 5, two 2-1 and 4-1 multiplexers developed based on the proposed majority gate are introduced. And finally, discussions and conclusions are presented in Section 6.
Principles of QCA were first introduced in 1993[1]. To have a system of information processing based on the position of electrons, there must be a space for holding electrons in place. In the QCA literature, this space is called a cell. Each cell is a Nano-sized square space with four holes called quantum dots in its four corners which hold two electrons. The cells allow free electrons to tunnel between neighboring quantum dots (Figure 1)[15].
Since the two electrons within each cell repel each other until reaching the lowest energy state, as shown in Figure 2, there could only be two stable states for each cell[15].
In the base state when there is no external force, the Coulomb repulsion of the electrons pushes them into opposite corners of the QCA cell, where they will be as far as possible from each other. Hence, there are only two possible states for a QCA cell. As shown in Figure 2, these two states are known as P = +1 or P = -1 and represent the binary values of “1” and “0” respectively [1,16-19].
The basic building blocks of QCA circuits are wires, majority gate (vector), and inverter. There are two types of wire in QCA circuits: 90° and 45°. The 45° wire is a wire of base cells that are rotated at 45° (Figure 3)[16].
In Figure 4 shown the typical layouts of majority gate and inverter[15].
In QCA circuits, the movement of electrons inside the cells is controlled by the Clock. This component makes sure that the data is flowing in the right direction and also synchronizes the combination of data incoming from different branches. In other words, in conjunctions where multiple inputs should be combined to produce an output, the clock holds the data that arrive earlier in place until all data necessary for the combination arrive at the conjunction. Each clock consists of four phases (Figure 5)[15-17,20,21,30]:
- Switch: the cell becomes depolarized and gradually transforms according to the state of the input or preceding cell.
- Hold: the cell maintains a high energy level and remains active to serve as an input for the subsequent cell.
- Release: with a gradual decrease in the energy level, the cell loses its effect on its adjacent cells.
- Relax: the cell loses all of its energy and reaches a stable state.
QCA circuit fabrication faults
The faults that typically occur in the fabrication of QCA circuits include [5-12,16,17,22]:
- Missing cell (Figure 6-a)
- Additional cell (Figure 6-b)
- Cell displacement (Figure 6-c)
- Rotation cell (Figure 6-d).
In this section, we briefly review the existing solutions for improving the fault tolerance of majority gate circuits. The designs previously proposed for this purpose are displayed in Figure 7. These designs have used different methods to improve fault tolerance. In most of these solutions, fault tolerance is improved by adding additional cells to strategic positions within the majority gate. Other solutions have repositioned inputs or output or have used cell rotation to improve fault tolerance.
This section introduces the proposed majority gate design developed for improved fault tolerance. After the introduction, the simulation results are presented and the design outputs in different states are examined. The proposed majority gate design is shown in Figure 8.
The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. In this gate, three cells called A, B and C are inputs, the cell called OUT is output, and the remaining cells are intermediate cells. The proposed structure was simulated with the parameters listed in Table 1 using the software QCA Designer.
Table 1: Simulation parameters used in QCA Designer
|
Parameter |
Value |
|
Cell Size(nm) |
18 * 18 |
|
Cell Separation(nm) |
2 |
|
Number Of Samples |
12800 |
|
Convergence Tolerance |
0.001000 |
|
Radius of effect(nm) |
65.000000 |
|
Relative Permittivity |
12.900000 |
|
Clock High |
9.800000e-022 |
|
Clock Low |
3.800000e-023 |
|
Clock Shift |
0.000000e+000 |
|
Clock Amplitude Factor |
2.000000 |
|
Layer Separation |
11.500000 |
|
Maximum Iterations Per Sample |
100 |
Figure 9 presents the simulation results of the proposed three input majority gate. The AND and OR gates developed based on the proposed structure are shown in Figures 10-a and 10-b. The results of the simulation of these gates are presented in Figure 11.
The proposed design has 100% tolerance to the fault of a single missing cell (Table 2-a) and 71.43% tolerance to the rotation of one cell (Table 2-b). The tolerance of the design to cell displacement is described in Table 3. Also, addition a cell fault to the grid will make no change in the output of the proposed majority gate. Tables 4 and 5 demonstrate the physical fault tolerance of the design for the state shown in Figure 12.
Table 2: Simulation results of the proposed structure for the faults of (a) a single missing cell and (b) a single rotation cell
a
|
Removed Cell |
Output |
|
1 |
MV3 |
|
2 |
MV3 |
|
3 |
MV3 |
|
4 |
MV3 |
|
5 |
MV3 |
|
6 |
MV3 |
|
7 |
MV3 |
b
|
Rotation Cell |
Output |
|
1 |
B |
|
2 |
A |
|
3 |
MV3 |
|
4 |
MV3 |
|
5 |
MV3 |
|
6 |
MV3 |
|
7 |
MV3 |
Table 3: Effect of a cell displacement on the output of the proposed majority gate
|
Rightward |
Leftward |
Upward |
Downward |
Cell |
|
<3 |
<3 |
<18 |
|
A |
|
<3 |
<3 |
|
<18 |
B |
|
|
<7 |
<4 |
<4 |
C |
|
|
|
<8 OR >15 |
|
1 |
|
|
|
|
<8 OR >15 |
2 |
|
|
|
<7 OR >17 |
|
6 |
|
|
|
|
<7 OR >17 |
7 |
|
<2 |
|
<4 OR (>18 AND <31) |
<4 OR (>18 AND <31) |
OUT |
Table 4: Energy calculations for the output cell of Figure 12-b
Table 5: Energy calculations for the output cell of Figure 12-c
In Table 6, the proposed majority gate is compared with the existing designs in terms of the number of cells, area requirement, and fault tolerance. As Table 5 demonstrates, the proposed design enjoys a better performance than the existing designs.
Table 6: Comparison of the proposed majority gate with the existing designs
|
Single-cell fault tolerance |
Area requirement (µm2) |
Number of cells |
Gate |
|
66.70 |
0.0096 |
13 |
Figure 6-a[23] |
|
81.25 |
0.0139 |
20 |
Figure 6-b[11] |
|
82.25 |
0.0096 |
21 |
Figure 6-c[24] |
|
60.00 |
0.0135 |
19 |
Figure 6-d[10] |
|
100 |
0.0076 |
16 |
Figure 6-e[17] |
|
64.29 |
0.0210 |
32 |
Figure 6-f[25] |
|
80.95 |
0.0096 |
25 |
Figure 6-g[21] |
|
97.44 |
0.0388 |
43 |
Figure 6-h[26] |
|
100 |
0.0144 |
27 |
Figure 6-i[16] |
|
100 |
0.0096 |
11 |
Proposed design |
This section first reviews the existing multiplexer designs, then presents a 2-1 multiplexer and a 4-1 multiplexer designed based on the proposed majority gate. At the end of the section, the proposed multiplexer compared with the existing designs. The existing designs for 2-1 multiplexers are shown in Figure 12.
Figure 13 presents the 2-1 multiplexer designed based on the proposed majority gate. The output function of this multiplexer is shown in equation 1:
Eq. (1) : F=S'A + SB
The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell. The simulation results obtained for this multiplexer are presented in Figure 14.
The 4-1 multiplexer designed based on the proposed majority gate is shown in Figure 15. This multiplexer has 85.71% tolerance to the fault of a single missing cell.
In Table 7, the proposed 2-1 multiplexer is compared with the existing designs. As the simulation results presented in Table 7 demonstrate, the proposed 2-1 multiplexer exhibits significant superiorly over the existing designs in term of the number of cells, area requirement, and fault tolerance.
Table 7) Comparison of the proposed 2-1 multiplexer with the existing designs
|
Fault tolerance |
Area requirement (µm2) |
Number of cells |
Multiplexer design |
|
48.14 |
0.039204 |
45 |
Figure 14-a[27] |
|
33.33 |
0.035244 |
45 |
Figure 14-b[27] |
|
64.45 |
0.051084 |
65 |
Figure 14-c[10] |
|
94.02 |
0.158404 |
137 |
Figure 14-d[26] |
|
86.96 |
0.078684 |
98 |
Figure 14-e[16] |
|
95.24 |
0.063516 |
41 |
Proposed design |
In this article, we first provided a brief introduction to QCA technology and challenges in the fabrication of QCA circuits and discussed the existing solutions for resolving these challenges. We then presented a new solution for improving the tolerance of three input majority gate to the faults of single missing cell, single additional cell, single cell rotation, and single cell displacement. The proposed idea was then used to design new 2-1 multiplexer and 4-1 multiplexer. The simulation results demonstrated the significantly improved fault tolerance of the proposed solution for three input majority gate compared to the existing designs. The multiplexer designed based the proposed majority gate also showed significant superiority over the existing designs in terms of fault tolerance and area requirement. In future works, the proposed majority gate can be incorporated into the design of flip-flops, decoders, hybrid circuits, and sequential circuits. The proposed multiplexer can be used in the design of memory cells for RAMs.
1 Lent, C.S., Tougaw, P.D., Porod, W., Bernstein, G.H.: Quantum cellular automata. Nanotechnology 4, 49–57 , 1993.
2 Wilson, M, Kannangara, K, Smith, G, Simmons, M, Raquse, “B: Nanotechnology: basic science and emerging technologies. Chapman and Hall, London”, 2002.
3 Chandra, Jangam Siva, Kandula Suresh, and Bahniman Ghosh. Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design, Journal of Low Power Electronics, vol. 10, no. 2, pp. 272-278, 2014.
4 Karim, Fazal, and Konrad Walus. Efficient simulation of correlated dynamics in quantum-dot cellular automata (QCA), IEEE Transactions on Nanotechnology, Vol. 13, no. 2, pp. 294-307, 2014.
5 Hashemi, S., Tehrani, M., Navi, K., "An efficient quantum-dot cellular automata full-adder,” Sci. Res. Essays 7(2), 177–189, Sci, Res, Essays, vol. 7, no. 2, pp. 177-189, 2012.
6 A. Roohi, S. Sayedsalehi, H. Khademolhosseini, K. Navi., "Design and evaluation of a reconfigurable fault tolerant quantum-dot cellular automata gate," J. Comput. Theor. Nanosci., vol. 10, pp. 380-388, 2013.
7 B. Sen, A. Rajoria, B.K. Sikdar. “Design of Efficient full adder in quantum-dot cellular automata,” Sci. World J. 2013 (2013) 10, Sci. Word, vol. 10, 2013.
8 Roohi, A., DeMara, R.F., Khoshavi, N., "Design and evaluation of an ultra-area-efficient faulttolerant QCA full adder," Microelectron. J., vol. 46, no. 6, pp. 531-542, 2015.
9 Mohammadi, M., Gorigin, S., "An efficient design of full adder in quantum-dot cellular automata technology," Microelectron. J., vol. 50, pp. 38-43, 2016.
10 Huakun Du, Hongjun Lv, Yongqiang Zhang, Fei Peng, Guangjun Xie. "Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata," J Comput Electron, 2016.
11 Dharmendra Kumar, Debasis Mitra. "Design of a practical fault-tolerant adder in quantumdot cellular automata," Microelectronics. Journal, vol. 53, pp. 90-104, 2016.
12 Sen, B., Sahu, Y., Mukherjee, R., Nath, R.K., Sikdar, B.K., "On the reliability of majority logic structure in quantum-dot cellular automata," Microelectron. J., vol. 47, pp. 7-18, 2016.
13 M. A. Reed, J. N. Randall, R. J. Aggarwal, R. J. Matyi, T. M. Moore, and A. E. Wetsel. “Observation of discrete electronic states in a zero-dimensional semiconductor nanostructure”, Phys. Rev. Lett. Vol. 60, pp. 535-539, 1988.
14 U. Meirav, M. A. Kastner, and S. J Wind. “Singleelectron charging and periodic conductance resonances in GaAs nanostructures” Phys. Rev. Lett. ,Vol. 65, No.6, pp. 771-774, 1990.
15 B. Sen, et al., Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability, Microelectron. J, 2014, http://dx.doi.org/10.1016/j.mejo.2014.08.012i
16 Ahmadpour. SS , Mosleh. M, A novel fault-tolerant multiplexer in quantum-dot cellular automata technology, The Journal of Supercomputing, Volume 74, Issue 9, pp 4696–4716, 2018.
17 Hasan Hosseinzadeh, Saeed Rasouli Heikalabad. A novel fault tolerant majority gate in quantum-dot cellular automata to create a revolution in design of fault tolerant nanostructures, with physical verification, Microelectronic Engineering, Volume 192, Pages 52-60, 2018.
18 Lent CS, Tougaw PD. A device architecture for computing with quantum dots. Proc IEEE 85(4):541–557, 1997.
19 Tougaw PD, Lent CS. Logical devices implemented using quantum cellular automata. J Appl Phys 75(3):1818–1825, 1994.
20 Walus K et al. QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol 3(1):26–31, 2004.
21 Mengbo Sun, Hongjun Lv, Yongqiang Zhang, Guangjun Xie. The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata, Journal of Electronic Testing, Volume 34, Issue 2, pp 109–122, 2018.
22 Momenzadeh M, Ottavi M, Lombardi F. Modeling QCA defects at molecular-level in combinational circuits. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005.
23 Das K, De D. QCA defect and fault analysis of diverse nanostructure for implementing logic gate. International journal of recent trends in. Eng Technol 3(1), 2010.
24 Dysart TJ, M Kogge P, S Lent C. An analysis of missing cell defects in quantum-dot cellular automata, 2017.
25 Beard MJ. Design and simulation of fault-tolerant quantum-dot cellular automata (QCA) NOT gates. Dissertation, Wichita State University, 2006.
26 Sen, B., Dutta, M., Mukherjee, R. et al. Towards the design of hybrid QCA tiles targeting high fault tolerance, Journal of Computational Electronics, Volume 15, Issue 2, pp 429–445, 2016.
27 Huang, J., Momenzadeh, M., Lombardi, F. On the tolerance to manufacturing defects in molecular QCA tiles for processing-by-wire. J. Electron. Test.23(2–3), 163–174, 2007. doi:10.1007/ s10836-006-0548-6
28 Du H et al. Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata. J Comput Electron 15(4):1484–1497, 2016.
29 Nuriddin S., Jun-C. j., A novel controllable inverter and adder/subtractor in quantum-dot cellular automata using cell interaction based XOR gate, Microelectronic Engineering, Vol. 222, 2020, 111197.
30 Rahmani Y., Heikalabad S.R., Mosleh M., Efficient structures for fault-tolerant majority gate in quantum-dot cellular automata, Optical and Quantum Electronics, 53, 45, 2021.