In CMOS design, conventional logic design plays a vital role. Even though, irrespective of its many advantages, it lacks efficiency in terms of speed, area, power, and delay leading to much heat dissipation and delay on circuit design. Therefore, in replacement of conventional digital computers, Reversible logic acts as a promising technology that can improve the standard of the circuits in terms of power, speed, area, heat dissipation, lifespan, and input traceability. In this project, we propose a high-speed reversible radix binary-coded decimal multiplier (HS-RBCDM) and a Power Enhanced- High speed reversible binary-coded decimal multiplier (HS-RBCDMPE) each efficient in terms of speed, power and area respectively. In comparison with recent designs, the proposed methodology gives a single gate level architecture for multiple multiplicand generator (MMG) and reversible adder and a Radix-recoder for converting 8221 to 4221 codes for HS-RBCDM that achieves low power dissipation and shifting operation using copying gate instead of MMG for HS-RBCDMPE to achieve high-speed reducing delay in the circuit and area efficiency. The proposed multipliers HS-RBCDM and HS-RBCDMPE is designed with 90- nm ASIC technology using the Cadence EDA tool and is compared with state-of-art reversible BCD algorithm. Performance evaluations of the proposed designs compared with recent proposed methods reveals that the proposed HS-RBCDM multiplier and HS-RBCDMPE achieves 64.9% and 69.6% Area reduction, 51.3% and 71.9% Delay reduction and 52.6% and PDP reduction respectively.