Subthreshold Analytical Model of Asymmetric Gate Stack Triple Metal Gate all Around MOSFET (AGSTMGAAFET) for Improved Analog Applications

In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal gate MOSFET(AGSTMGAAFET) and performed a comparative analysis with the simulation results obtained using the SILVACO 3D simulation software. Existing devices such as gate all around single metal (SMGAAFET), gate all around triple metal (TMGAAFET), gate stack single metal (GSSMGAAFET), gate stack triple metal (GSTMGAAFET) and asymmetric gate stack single metal (AGSTMGAAFET) have been compared with our proposed structure AGSTMGAAFET. Our device provides excellent performance in terms of drain current, transconductance, output conductance, current gain, maximum transducer power gain which shows our device’s suitability for various analog applications moreover the potential and electric field plots obtained have twostep profile and extremely low electric field near the drain region which ordains our device with the ability to suppress various SCE’s like DIBL and hot-carrier effect. The analytical model and simulation results show good convergence in values which validate the correctness of the proposed model.


Introduction
In modern day world where there is need for continuous miniaturization of MOSFET used in variety of integrated circuits, device scaling has been one of the prime tools to achieve this goal. However, device scaling is restricted up to a limit mainly due to short channel effects (SCE) [1]. The continued downscaling of CMOS has led to the need for ultra-thin gate dielectrics as well. However, the thinning of oxide layer is limited by direct tunneling which increases the leakage current. Thus, combination of these effects leads to major reliability issues and causes performance degradation over a period of time.
Thus, a number of device structures like Schottky barrier MOSFET (SBCGAA MOSFET), Schottky barrier graded stack MOSFET (SBGS-CGAA MOSFET) and Dual metal Schottky barrier graded stack MOSFET (DMSBGSCGAA) have been proposed earlier to overcome short channel effects. These gate all around MOSFET have greater control over the channel as they surround the substrate from all sides, provide increased packing efficiency and avoid corner effects [2]. However, they suffer from DIBL effects, threshold voltage fluctuations and difficulties in fabrication.
In this paper we have proposed a triple material gate FET that helps in overcoming existing DIBL, impact ionization and eliminates oxide breakdown effects to large extent by improved transport efficiency. This when used with gate stack provides high transconductance. With the use of triple material gate in the practice of gate engineering the overall characteristics of the device are enhanced because of the spread of inversion charge throughout the silicon body which in turn leads to a high current because of improvements in substrate mobility [3]. For better carrier generation and improved performance, a high-k dielectric material like HfO 2 has been used along with SiO 2 in the proposed structure which reduces leakage current [4]. However, high-k materials result in fringing fields from the source/drain regions which tends to decrease the control of the gate over the channel. Thus, an ultra-thin SiO2 interlayer between the high-K layer and silicon substrate has been introduced which improves the quality of interface by decreasing trap density and provides stability [2]. To overcome shallow source/drain at junction and for easy fabrication metallic material instead of doped material is used. Hence overall proposed structure consists of asymmetric gate stack and triple material gate which collectively improve drain current characteristics and reduce SCE's by providing better gate control.
Using graphical simulation for the proposed Asymmetric Gate Stack Triple Gate (AGSTMGAAFET) the device showed best performance results in terms of drain current, conductance, intrinsic gain, transconductance, maximum transducer power gain (MTPG), current gain and output conductance (g d ) as compared to Asymmetric gate stack single metal FET(AGSSMGAAFET),Gate all around single metal FET (SMGAAFET),Gate all around triple metal F E T ( T M G A A F E T ) , G a t e s t a c k s i n g l e m e t a l FET(GSSMGAAFET) and Gate stack triple metal FET(TMGSGAAFET) which have been proposed earlier to overcome SCE's to a great extent. Section 2 describes the device structure of the proposed and the models used to simulate the various devices for comparison. Section 3 presents the analytical model of the device. Section 4 displays the comparative analysis of our device against those previously proposed and the comparison is made on the basis of various parameters such as electric field, potential, subthreshold current for different lengths and radius, MTPG, current gain, transconductance, output conductance, I DS vs V GS and I DS vs V DS graphs and also the potential contour plots of all the devices has been studied. In section 5 we provide the conclusion, in section 6 we acknowledge the inputs of all those who have guided us throughout the course of our research and section 7 presents the calculated coefficients of the analytical model.

Device Structure
The three-dimensional view of Asymmetric Gate Stack Triple Metal Gate All Around (AGSTMGAAFET) MOSFET is presented in the Fig. 1(a). The gate material is composed of three metals each having different work functions. The highest work function metal (4.8 eV) is present at the source end and between the two the metal with work function 4.62 eV is present while the with the least work function metal (4.4 eV) is present at the drain end. Source and drain are doped with a concentration of 10 19 cm −3 (n-type) and the substrate is doped with concentration of 10 16 cm −3 (p-type). The thickness of the silicon substrate is t Si = 10 nm. Hafnium Oxide (HfO 2 ) is the gate stack material used in the device (t Hfo2 = 2 nm, ε r,Hfo2 = 22ε 0 ). Two methods namely Newton & Gummel are used for solving using ATLAS-3D.
The decreasing gradient of work functions from source towards the drain helps in reducing the value of electric field at the drain end thereby regulating it throughout the channel. Due to this, electron overshooting is prevented which is basically the hot-carrier effect (another type of SCE).
T h e 3 -D a  Tables 1 and 2 respectively. The list and description of models used for the simulation of the device using ATLAS-3D are tabulated in Table 3 [5].

Analytical Model
The Asymmetric gate stack triple metal exhibits a symmetry which is cylindrical in nature therefore to take advantage of this it is a good choice to resort to the use of cylindrical coordinates instead of cartesian coordinates because it greatly simplifies the solution procedure that is the solution is gotten using the 2D Poisson's equation rather than 3D Poisson's equation this luxury is afforded to us as a result of the fact that the potential and electric field distribution in our device do not depend on the variation of the azimuthal angle. The 2D Poisson's equation for AGSTMGAA MOSFET is given by- 0 ≤ r ≤ t si 2 and L i − 1 ≤ z ≤ L i where i = 1,2,3,4. Here 'r' represents the channel radius and 'z' represents the axis along which we measure the length of the channel and Φ i (r,z) represents the potential as a function of r and z.
The form of the solution is as shown below were the use of boundary condition gives us the required coefficients by using the parabolic approximation method.
Where a 0 , a 1 , a 2 represent the coefficients which are a function of 'z'. The calculation of these coefficients is done using the following boundary conditions: -.
1. The electric field vanishes along the axis of symmetry 2. The electric field should be invariant crossing over from the dielectric to the silicon body Where ϕ g s i = V g s − V fb i , ϕ s i ¼ Φ i r; z ð Þ r¼0 and i = 1,2,3,4,j = 1,2,k = 1,2 3. The potential should not vary as we move from a region under one metal to another having different work functions.
4. The electric field should not vary as we move from a region under one metal to another having different work functions.
5. Potential measured at the source should be V bi Where Potential measured at the drain should be V bi + V DS We apply the first two boundary conditions and rearrange the equation to solve for the surface potential. Where, Here ϕ Mi represents the work function of the gate material and ϕ si represents the work function of the silicon substrate.
The solution for this equation is obtained in two parts that is in terms of the forced and natural solutions.
To obtain the necessary coefficients we employ the boundary condition discussed above. The coefficients are presented in the appendix at the end. The electric field which is the negative gradient of the potential is obtained simply by taking the first derivative of the potential.
EF z ð Þ ¼ The subthreshold current can be calculated using the formula [6]: Where k = 1.38 x 10 23 J/K represents the Boltzmann's constant, T represents temperature and μ =1300 cm 2 /V s represents the electron mobility.
And the corresponding sub threshold slope is given by [6]:

Results and Discussion
Potential is an important parameter for understanding device physics as it explains the different FET's behavior under the same biasing condition as potential would instigate the charge distribution across the channel. On this charge distribution across the channel, complete device characteristics are dependent. We can clearly observe from the contour plots in Fig. 2. that the increase in potential in triple metal FET's is much more as compared to the single metal FET's this basically leads to a reduction in short channel effects like hot carrier effect and impact ionization. Also, the use of asymmetric gate stack with high dielectric leads to a large capacitance and greater control over the channel carriers which increases the electric field throughout the channel and reduces any possibility of gate tunneling. Figure 3 gives us an idea of the dependence of potential on position in the channel for all the devices under study. We are analyzing devices with a single and triple gate material; the latter case leads us to observe two steps in the potential moving from source to drain, this ordains our device with the ability to overcome DIBL to a great extent due to an improvement in the efficiency of carrier transport and the carrier speed thus leading to improved drain current [2]. This can be attributed to the change in work function moving from source to drain. Another point of interest is that devices with gate stack exhibit relatively lower potential which can be attributed to the use of triple metal gate with different work function [6]. Figure 4 analyses the dependence of electric field on the position the channel. Electric field is the first order derivative of potential. This graph exemplifies the benefit of using an asymmetric gate stack which as depicted in graph has lower electric field values which in nano-scale device architectures is of paramount importance for reduction of SCEs such as impact ionization and velocity saturation that degrade the performance of the device [2]. Figure 5 gives us the distribution of surface potential as a function of channel length in which we observe that the potential has a minima which progressively decreases as we increase the channel length due to the decrease in charge control linear region which ultimately leads to the entire potential to slide in the direction of source [6,7]. The analytical results are in much accordance with the simulated results in this case. Figure 6 presents the electric field distribution at the surface as a function of position in the channel for three values of channel length (L = 30 nm,45 nm,60 nm). The triple metal asymmetric gate stack MOSFET provides a two-step profile for the electric field where the steps occur at the interface of two gate metals [8]. This is extremely beneficial because it leads to the electric field being averaged out throughout the length of the channel and a major reduction in electric   field seen near the drain directly reduces hot carrier injection and oxide degradation in the drain region [2]. Figure 7 gives the graphical relationship between subthreshold current and the applied gate input voltage. Now we can analyze from graph that if we decrease the length of the channel for the proposed device then the value of subthreshold current increases leading to increased power consumption and other related SCEs due to current leakage in off state [6]. Apart from this it is observed that the analytical model closely resembles the ideal case.
In Fig. 8, we have shown a comparison between source to drain and gate input voltage for different radii of the channel region and for a particular channel length(30 nm). The observation to make here is that smaller the channel radius greater the subthreshold slope leading to lower off current and hence lower power dissipation [9].
In Fig. 9, we show the variation of surface potential with different values of channel radii. The observation made here is that as the length of the channel goes up the position of potential minima also rises because of the fact that controllability of the gate over the channel goes down with increasing channel thickness causing V T to decrease as channel radius increases so a smaller channel radius is desirable to keep off current in bounds [10].
In Fig. 10, the clear decline in electric field near the drain region because of the high -k dielectric (HfO 2 ) and triple metal gate this gives us the benefit of reduced hot-carrier effect and therefore additional reduction in power dissipation [11,12]. Figure 11 shows the variation in the drain current (I DS ) with the gate voltage (V GS ) for SMGAAFET, TMGAAFET, GSSMGAAFET, GSTMGAAFET, AGSSMGAAFET and AGSTMGAAFET MOSFET devices. It can be seen that the AGSTMGAAFET generates the highest drain current. Because of the amorphous nature, HfO 2 provides high kinetic stability to AGSTMGAAFET thus ensuring less leakages in the corresponding MOSFET [13]. Apart from this HfO 2 stack structure helps in increasing the concentration of electrons in the channel by providing higher capacitance thereby resulting in higher I DS [14]. The strength of the fringing electric fields also increases thereby increasing I DS [15]. It is clear from obtained graph that gate stack devices give higher current than non-gate stack devices due to presence of high dielectric (HfO 2 ) graded channel. Triple metal devices give higher current than single metal devices as they reduce the overshooting of the electrons by averaging out electric field in entire region. The general trend followed by drain current characteristics is asymmetric gate stack greater than gate stack greater than non-gate stack FETs. Figure 12 shows the variation in the transconductance (g m ) with the gate voltage (V gs ) for SMGAAFET, TMGAAFET, GSSMGAAFET, GSTMGAAFET, AGSSMGAAFET and AGSTMGAAFET devices. Transconductance is calculated by derivation of drain current relative to the gate voltage at constant V ds [16].
It can be seen that initially the transconductance increases since the device is in linear region and then it tends to decrease when device enters the saturation region. In the presence of triple metal surrounding gates and HfO 2 the carrier mobility increases and the gate control over the channel region becomes more enhanced, thus increasing the drain current and hence the transconductance (since g m is proportional to I DS ). As g m increases, it also implies a higher cut off frequency (f T ) [16]. Figure 13 shows the variation of the current flowing from source to drain with respect to the applied voltage V DS . It can be seen clearly from the figure that our proposed model AGSTMGAAFET gives superior performance in terms of current as compared to all other devices under inspection. Owing to the amorphous nature of HfO 2 the device has high kinetic stability due to which leakage current is greatly reduced. The asymmetric gate stack provides a much higher drain current owing to high relative permittivity and the triple metal gate which by reducing the acceleration of carriers also decreases short channel effects such as hot carrier effect, impact ionization, oxide breakdown etc. Figure 14 gives the variation of output conductance (g d ) with respect to the drain to source voltage (V DS ). The mathematical expression for output conductance is given as [16]: It is observed that increase in drain current obtained by the AGSTMGAAFET is because of the excellent control over the channel offered by the asymmetric gate stack. The high relative permittivity of HfO 2 increases the capacitance of the device which in turn enhances the drain current and subsequently g d as well. Figure 15 clearly gives us the idea that the current gain offered by the proposed device AGSTMGAAFET is superior to the other devices under study, this result can be attributed to the fact that our device simply provides excellent performance in terms of drain current. The use of high-K dielectric (HfO 2 ) increases the gate capacitance which in turn enhances the electric field causing electron velocity surge leading to better current gain which is highly beneficial for certain analog applications such as current amplifiers. Moreover, the decreasing work function of the gate material as we move from the source to the drain reduces unwanted SCEs by regulating the acceleration of charge carriers. [17]. Figure 16 gives the comparison of the Maximum transducer power gain (MTPG) of the various devices under study. This parameter basically gives the average amount of power delivered to the load as a ratio of the maximum average power available from the source and is measure of power efficiency of device under the condition that the load (Z L ) is matched to the devices output impedance (Z O ). [18] MTPG ¼ P load P source The proposed device gives excellent power efficiency as justified by the figure. MTPG is an important performance parameter of amplifiers which are a perfect application of our proposed device.
The combination of asymmetric gate stack with high-K dielectric and triple metal gate leads to the device having a large capacitance resulting in large electric field and high saturation velocity for the charge carriers which cause large current flow from source to drain thereby leading to large MTPG.

Conclusion
In this paper AGSTMGAAFET is studied in terms of various device parameters. Excellent performance in terms of drain current, transconductance, output conductance, current gain, maximum transducer power gain which shows our device's suitability for various analog applications. Our device provides the advantages of triple work function gate and asymmetric gate stack which leads to increased carrier velocity, improvement of efficiency in carrier transport and alleviation of DIBL, hot-carrier effect and other SCE's moreover it leads to reduced power dissipation. Overall, the proposed device is suitable for various analog application requiring high gain and low power dissipation. The proposed analytical model for AGSTMGAAFET has been analyzed for different channel length (L = 30,45,60 nm) and radius of substrate (R = 10,12 nm). It is so found that the analytical results for potential, electric field and subthreshold current are in close accordance with the simulated results. Declarations Not Applicable.
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Conflict of Interest
There are no conflicts of interest amongst the authors.