Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

- The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.


INTRODUCTION
On scaling CMOS technology into nano regime the conventional metal oxide field effect transistor (MOSFET) faces major hindrance due to massive short-channel effects such as drain induced barrier lowering (DIBL) subthreshold leakage, velocity saturation, punchtrough, hot electron effect, gate induced drain leakage (GIDL) [1][2][3][4], and accordingly the expected output characteristics and performance of the device at nanoscale is tarnished [3][4][5]. Multiple methodologies are incorporated in conventional MOSFETs to improve the performance at nanoscale, which are namely reduction in gate oxide thickness, increased doping concentration, indulging high-k dielectrics, incorporation of dual material gate, pocket implantation, lateral channel engineering, silicon-on-insulator (SOI) technology, strained silicon (s-Si) technology [4][5][6][7][8]. But, as source and drain doping concentrations are increased the mobility of charge carriers decreases, while the junction capacitances at gate-source (Cgs) and at gate-drain (Cgd) escalate significantly [3,[5][6][7][8][9]. With reduction in gate oxide thickness the carriers acquire enough energy due to applied gate voltage and become trapped into the gate oxide region at high electric field [10]. So, the overall performance degrades hence, induction of high-k dielectric substituted compensating the reduced oxide thickness by increasing the total gate capacitance for nano-regime device. On the other hand, introduction of high-k creates additional hitches in channel mobility leading to fermi level pinning at the MOS work function near the gate [11] resulting in tunnelling based leakage within the device, which is not desired.
Pocket implantation technique is another dominating choice to enhance device performance but, this generates large drain induced threshold voltage shift and low output resistance, which is not suited for application in high performance analog circuits [12][13][14], thereby discarded at many instances.
Due to shortening of channel length, gate tends to lose its control over the channel and the device, so subthreshold leakage current engenders [3,15,16] prompting abnormality in device performance. Hence, developing vertical FETs in the form of double-gate/tri-gate structures and integrating them with unconventional technologies (SOI, high-k, etc.) are some of the alternatives that researchers are looking into since the last decade for augmentation of device performance at nanoscale [12,[14][15][16]. One of the promising device structure that surfaced in nano-regime having an additional gate on other side for better control over channel depletion region employing SOI technology is the double gate silicon-on-insulator (DGSOI) MOSFET, which avoids field penetration from source/drain to the substrate ensuing reduction in leakage enriching the output characteristics [17][18][19].
The DGSOI FET provide superior performance but for devices with Lg at sub-50 nm and beyond the performance worsens due to major short channel effects such as DIBL and punchthrough of carriers [17], which leads to stimulation of quantum tunnelling heaving in the nanostructure. Consequently, strain engineering phenomenon is designed in device physics. The concept of strain technology was first incepted in semiconductor physics in 1980s by growing strain silicon film over relaxed SiGe [20], but then the strain effect was largely overlooked. It was in 1990s that MIT, USA revived the concept of strain effect and the first n-channel MOSFET with strained silicon channel exhibiting 70% higher mobility was developed [21,22]. Strain technology was later adopted by major semiconductor device companies like Intel, IBM and AMD at 90 nm node along with Silicon on Insulator (SOI) technology [23]. In 2008, Kumar et al. [24] already developed a dual channel based strain silicon technology device for improved performance at 100 nm channel length. For nano-devices below 100 nm mobility becomes field dependent due to increase in lateral and vertical electric fields. Thus, velocity saturation and negligible scattering of carriers near the surface, affects in elevating mobility and drive current of the device immensely as observed by Khiangte et al. [25]. Thereby, Khiangte et al. [25] developed a trilayered (s-Si/s-SiGe/s-Si) channel heterostructure on insulator (HOI) planar MOSFET, where the concept of strain channel engineering was employed to modify the band structure, increasing mobility and drain current. The HOI MOSFET incubated ~49% drive current advancement for 40 nm channel length device [26]. On scaling down to Lg = 30 nm, the HOI MOSFET had to be deformed by Dhar et al. [26] for enriched performance with allowable short channel effects as per the International technology roadmap for semiconductor (ITRS) 2015 [27]; hence, further scaling the gate length is nearly impossible in planar MOSFETs. Henceforth, designing a novel device implementing the established HOI system in the vertical form may be a probable solution and is therefore the need of the hour.
Having the concept for inducing strain engineering in the channel region of FET to eliminate quasi-neutral floating body effect in SOI FETs to deepen drain current by quantum carrier confinement [23] and ballistic transport of carriers is the motivation, so employing HOI system in double gate (DG) structure to design and develop a novel DG-SHOI FET for the first time with the distinguished tri-layered channel system sandwiched between the two-gates is therefore, the focus of this paper. This SHOI structure based DG device is expected to induce quasi-ballistic transport leading to quantum carrier confinement in the well region of the channel and in turn achieve enhanced drain current when implemented. So, the novel nano-regime DG-SHOI FET anticipates to be capable of minimising short channel effects inculcating quantum tunnelling phenomenon for ballistic transport of carriers providing increased mobility at maximum electric field for minimal DIBL and high transconductance with boosted electron drift velocity.

THEORY AND DEVICE STRUCTURE
To design and develop the proposed Double Gate Strained Heterostructure on Insulator (DG-SHOI) n-channel transistor a detailed theory and understanding for the device is to be established, which is based on implementing strain engineering incorporated within the device channel. A schematic device structure in 3-dimensional (3D) is shown in Figure 1(a) while Figure 1(b) provides the cross-sectional view of the channel and Figure 1(c) details the channel lattice structure. The device structure is designed and developed using Sentaurus TCAD [28] employing the parameters and constraints as tabulated in Table 1. The drift diffusion and piezo-resistive coefficient models are combined along with the Shockley Read Hall (SRH) doping dependence parameters while modelling the device in Sentaurus TCAD [28].  Atomic structure layout for strained system within tri-layered channel.
The device surface considered for demonstrating is oriented along (100) direction while the channel is along (011) direction being oriented vertically on the structure. The buried oxide layer is incubated in the device to prevent the penetration path of the electric field from source/drain to substrate as is the case in SOI MOSFETs [29][30][31] thereby a DG-SHOI structure is designed and developed.
The SiO2 (gate oxide) layers are grown on either side over the s-Si layer as hard mask to avoid field penetration from the top eluding formation of additional defects in the structure, which may deform expected device performance. The strained heterostructure channel forms a tri-layered system comprising of s-Si/s-SiGe/s-Si with 2-6-2 nm thicknesses, is implemented and nurtured between front and back gates as depicted in Figure 1(b) while the strain amalgamation is shown in Figure 1(c). Both gates are symmetrically designed having same work function and are electrostatically coupled. So, strong electric potential is settled across the channel effectively controlling source and drain energy barriers for carrier transport with less scattering effect than in planer MOSFETs of Lg = 30 nm and beyond that installs variety of short channel effects [14-16, 25, 26, 32-34]. The electric field at drain edge is expected to reduce on employing the two gates due to hot carrier effect being condensed [4]. Hence, source/drain doping concentrations are made high to reduce the channel resistance, which eventually anticipates in increasing the drive current lessening the leakage current in the proposed device. Hence, stands the motivation for scheming of the vertical channel DG-SHOI FET, which is projected to be beneficial over the planer MOSFET ensuring admirable control on the channel providing greater device performance following minimal current leakage, though highly optimistic due to incorporation of strain engineering especially for the narrow width channel region [24][25][26]. The two Si layers generates a mismatch of 4.2% in the channel with sandwiched SiGe alloy inviting strain with the band structure of the layers [30][31][32][33][34], thus, biaxial strain is realized [25,26]. Based on the design developed by Harrington et. al. [32] the total strain for the proposed DG-SHOI FET device is calculated and is given as: where εch-strain is the biaxial strain induced in the channel which is a function of dch the strained channel thickness that embraces three layers (ds-Si ds-SiGe ds-Si) and each layer thicknesses are as specified in Table 1. Total device strain is calculated considering the mismatch strain along with the SOI substrate. εch-strain is designed as summation of the total strain among the layers in the channel and as s-SiGe is 6 nm thick it serves equally (3 nm each) as the base for both the s-Si layers of the device and is calculated as: So in total the channel strain (εch-strain) is given by: On substituting εch-strain, the total device strain, εstrain, is achieved for the tri-layered system to be: where − and − are different lattice thicknesses in channel as shown in Figure 1(b) and (c) and is the substrate thickness. On incorporation of this biaxial strain at high electric field negligible amount of degradation of electron and hole mobility is observed due to reduction in effective mass of the material [23,[28][29][30][31]. The strain in the channel is applied in (010) and (001)   The valance and conduction band energy level splitting along the thickness of the channel alters the band structure and affect the carrier transport phenomenon as atomic lattice spacing in the region becomes loosely packed in the s-Si layers enhancing electron mobility leading to ballistic transport at nanodimensions; an oblivious occurrence with less scattering events [24,25,36]. This is supplemented with the device having nanometer scale channel length and width that endorses in increasing mobility. Thereby, with incorporation of biaxial strain along with the cohort of additional control over the nano-channel DG-SHOI FET, enhanced carrier mobility is expected leading to influence device performance by enriching the drive current.

RESULTS AND DISCUSSION
The novel DG-SHOI FET structure is designed and developed for the first applied on the DG-SHOI FET and is given as: The calculated threshold voltage, Vth, and DIBL for DG-SHOI FET is plotted and compared with HOI MOSFET [25] and DGSOI FET [17] devices as shown in Figure 3. As evident the Vth for 22 nm DG SHOI FET is observed to be less with respect to DGSOI FET while an enormous reduction of 57.6% in DIBL is perceived, subsequently authorizing the benefit of implementing strained channel in the device. This reduction in DIBL can be substantiated due to unfolding of band bending effect on strain application in channel instigating quantum tunneling of carriers with minor scattering. Also the Vth and DIBL of HOI MOSFET and DG-SHOI FET are found to be analogous, which is highly advantageous as the leakage is maintained within limits, though device gate length is drastically scaled from 50 nm to 22 nm while forming the DG structure.
Therefore, it can be ascertained as two gates of DG-SHOI FET equally and simultaneously controls the ultrathin strained channel the threshold voltage roll off dispute in planar HOI MOSFET is outshined due to occurrence of ballistic transport of carriers with less scattering events in the channel as is inherent from Figure 3. Therefore, these effects are expected to stimulate improvement in mobility in the DG-SHOI FET device. is amplified with minimum intervalley scattering. This increased electron mobility as seen in Figure 5(a) shoves the velocity to reach velocity overshoot condition as observed in Figure 5(b) in comparison to 50 nm HOI MOSFET [25].  The strain when implemented in the short channel device the bandgap becomes narrower as the constituent atom befits heavier and they are tightly confined in all three directions. The transverse effective mass decreases due to smaller difference between lower and upper sub bands in the quantum well. The electron mobility is inversely proportional to the transport effective mass. The maximum electron velocity is attained by charge carrier in inversion layer as another gate also provide equal potential to the other side of the channel.
Therefore, maximum carriers are confined in the s-Si layers and relentless electron mobility is observed along lateral channel direction as observed in Figure   5(a). Though, mobility enrichment is observed but in the novel design of DG-SHOI FET the leakage is well within the ITRS 2015 standards [27] as revealed in Figure 6 in comparison to other existing devices.  The low leakage as observed in DG-SHOI FET is substantiated with increase in mobility and is further witnessed from Figure 7, which obviates the assessment of transconductance (gm(max)) to DIBL for the FET devices. As the device is detected to have less subthreshold leakage in Figure 6, the transconductance is alleged to maximize for DG-SHOI FET in comparison to other devices at very low DIBL providing boosted device performance. The improvement in transconductance by 87.6% for newly designed 22 nm channel length DG-SHOI FET as noticed in Figure 7 instil velocity overshoot condition with simultaneous decrease in DIBL. This is a huge gain for the novel DG-SHOI FET with respect to HOI MOSFET [25] that suffered from the trade-off due to short channel effects at nano-regime (below Lg = 50 nm). The potential barrier lowering exponentially increases the source to drain leakage current; therefore, DIBL becomes a crucial parameter measuring the performance of the device at 22 nm technology node. But, with DIBL reduction and increased transconductance the 22 nm DG-SHOI FET proves to be quite beneficial, thus provide enhanced carrier mobility due to quantum carrier confinement and ballistic transport across the device, which is overlaid in Figure 8   The self-heating effect (SHE) is an aspect that degrades device performance from the expected yield for strained channel devices and that mostly affects the saturation region of the characteristics, but on implementing a thinner base layer (s-SiGe is 6 nm for DG-SHOI FET) the effect is immensely annulled as low thermal conductivity of ultrathin thermally stable SiGe consents accumulated heat to dissipate through the layers [41,42]. So an enhancement of ~56% in drain current is observed without degradation due to SHE for the 22 nm gate length DG-SHOI FET in comparison to DGSOI FET as shown in Figure 8. This enriched current is supplemented due to the enactment of the biaxial strain, which induces boosted electron mobility leading to velocity overshoot condition for sub-nano device. Hence, the novel design of 22 nm DG-SHOI FET proves to be the most beneficial device by being able to reduce the leakage providing enhanced drain current when implemented as exhibited in Figure 8, which is directly attributed to quantum carrier confinement effect in nano-regime quantum well-barrier structure developed by the narrow-width channel in the tri-layered channel system installing biaxial strain in the device, thus instigating for improved mobility with velocity overshoot condition leading to ballistic transport of carriers in the device.

CONCLUSION
The

ACKNOWLEDGMENT
The authors thank NIT Mizoram for the support throughout the work.

Funding:
The authors have no relevant financial or non-financial interests to disclose.

Conflicts of interest/Competing interests:
The authors declare no conflicts of interest financial or otherwise that are relevant to the content of this article.