A new switch-diode cell-based single-phase cascaded multilevel inverter

A novel generalized modular MLI topology blends the unique advantages associated with existing MLIs to enhance the output voltage level incorporating a comparatively lesser number of power electronic components for similar performances. The unique features of the proposed topology pertain to lower distortion as well as total standing voltage (TSV) and best level-switch ratio (LSR) among the state-of-the-art MLIs. Extensive simulations using MATLAB/Simulation platforms as well as experimental models of single-phase 7-level, 9-level, 11-level, 13-level, and 15-level inverters validate the superiority of the proposed topology for pragmatic applications in uninterruptable power supplies, photovoltaic farms, wind farms, and fuel cells.


Introduction
The multilevel inverter (MLI) has emerged as an adequate solution for DC-AC converter applications due to its reduced harmonic profile of multilevel waveform in the output voltage as compared to the two-level waveform obtained from the conventional voltage source inverter (VSI). Low distortion of the output voltage and a low blocking voltage of power switches are the important advantages of the MLI compared to the traditional VSI (Rodríguez et al. 2002). Owing to its ability to produce an AC voltage of variable magnitude and variable frequency, MLI is being employed in a variety of applications, namely AC motor control, uninterrupted AC power supplies (UPS), flexible AC transmission systems (FACTS), high-voltage DC transmission (HVDC), and renewable energy sources (Sinha et al. 2018). MLI integrates many input DC voltage sources and power semiconductor devices to synthesize a staircase waveform. There are three popular traditional MLIs, namely (i) the flying capacitor (FC) MLI (Dargahi et al. 2015), (ii) the neutral-point-clamped (NPC) MLI (Nabae et al. 1981), and (iii) the cascaded H-bridge (CHB) MLI (Baker and Bannister 1975). The CHB-MLI is the most significant structure among the classical MLIs as it requires a lesser number of power electronic components. This MLI topology can be symmetric or asymmetric. In the symmetric topology, the values of dc voltage sources of H-bridges are equal. In the asymmetric topology, the values of DC sources are made unequal (binary and trinary configurations). An asymmetric CHB structure increases the number of output voltage levels for the same number of power electronic components (Baker and Bannister 1975). Over the past few decades, many MLI topologies (Saeedian et al. 2017;Agrawal and Jain 2017;Boora and Kumar 2017;Arun and Noel 2018;Samadaei et al. 2018Samadaei et al. , 2016Lee et al. 2018bLee et al. , 2018aLee 2018;Gautam et al. 2018Gautam et al. , 2016Alishah et al. 2016Alishah et al. , 2017Alishah et al. , 2015Babaei et al. 2014bBabaei et al. , 2014cBabaei et al. , 2014aFarhadi Kangarlu and Babaei 2013;Babei and Hosseini 2009;Ounejjar et al. 2011;Babaei and Gowgani 2014;Jain 2014, 2013;Mokhberdoran and Ajami 2014;Majumdar et al. 2020;Mahato et al. 2019aMahato et al. , 2019cMahato et al. , 2020aMahato et al. , 2020bMahato et al. , 2019bJagabar Sathik et al. 2020) have been studied for the reduced number of power electronic components. The modular structures of MLIs presented in Saeedian et al. (2017); Samadaei et al. (2018Samadaei et al. ( ), 2016Alishah et al. (2017) require a large number of switches and DC sources. The basic module of MLI requires a minimum of four DC sources. MLI discussed in references (Saeedian et al. 2017;Samadaei et al. 2018;Alishah et al. 2017;Babaei et al. 2014c) generate 25-level, 17-level, and 13-level, respectively. The advancement in Agrawal and Jain (2017) has led to reducing the number of DC sources by incorporating a large number of capacitors where the capacitor voltage balancing would be an issue of great concern. In Boora and Kumar (2017), generalized MLI topology is proposed that uses only unidirectional power switches, and thus the structure is not modular. Semi half-bridge cells (Arun and Noel 2018) are cascaded with cross-switch MLI to produce a new structure configured under the symmetric and asymmetric mode, producing all odd and even voltage levels. A square T-type (ST-type) module for asymmetrical MLI is proposed in (Samadaei et al. 2018). The MLI proposed in Lee et al. (2018b) introduced an improved symmetrical fourlevel submodule as a basic cell and a hybrid cascaded MLI topology. A single-stage switch capacitor module (S 3 CM)based MLI is suggested by Sze Sing Lee in Lee (2018), which can generate different both the positive and negative voltage levels without the use of H-bridge. Asymmetrical cascaded compact MLI (CCMLI) is presented in Lee et al. (2018a) which can generate output voltage of 7-level and 13-level. The researchers have suggested new MLI topologies in Gautam et al. (2018Gautam et al. ( , 2016 and Alishah et al. (2016) that can be used as symmetrical and asymmetrical DC sources and require high-voltage switches. In Gautam et al. (2016), a large number of switches (especially bi-directional switches) along with large number of capacitors are needed for topology-I. Topologies discussed in Alishah et al. (2016Alishah et al. ( , 2017 and Gautam et al. (2016) require a large number of switches and DC sources. Thus, to reduce the number of DC sources in cascaded MLIs topologies, a new MLI topology is presented in Babaei et al. (2014b) that reduces the number of voltage sources by half. In this process, two extra number of capacitors are to be added for one basic unit of the converter. Thus, some of the research works are considered to reduce the number of voltage sources (Agrawal and Jain 2017;Gautam et al. 2016;Babaei et al. 2014b;Lee 2018) for industrial applications using a few active sources with several capacitors in the circuit. However, an appropriate capacitor balancing technique or self-balancing technique is required to achieve the capacitor voltage balancing. The authors have proposed cross-switch MLI structure in reference (Farhadi Kangarlu and Babaei 2013) to generate the negative output voltage levels without the use of H-bridge and can also be extended for the three-phase. Babaei proposed MLI based on the series-connected sub-multilevel inverter (Babei and Hosseini 2009) consisting of two unidirectional switches and a DC source. Three algorithms based on different voltage magnitudes of DC sources have also been proposed. A new structure of MLI entitled 'Packed U-cells (PUC) inverter (Ounejjar et al. 2011) is proposed where each U-cells consists of two power switches and one capacitor. PUC inverter can be considered as a compromise between the flying capacitor and the cascaded H-bridge topologies. MLIs based on switched DC sources (SDCs) (Gupta and Jain 2014) (Gupta and Jain 2013) and switched capacitor units (SCUs) (Babaei and Gowgani 2014). SDCs can work with only symmetric values of DC sources, whereas SUCs can be implemented by a combination of conventional series and series-parallel switched capacitor MLIs. Basic unit based on H-bridge is developed using two DC sources of different magnitudes, being cascaded in series (Babaei et al. 2014c). The MLI proposed in (Babaei et al. 2014a) is based on developed H-bridge, where the magnitude of the DC sources depends on the chosen algorithms. The maximum blocked voltage is equal to the sum of all the voltages of DC sources, which would restrict their highvoltage applications. A large number of bi-directional power switches are used in Alishah et al. (2015), and the blocking voltage for these switches is high. MLI needs a full-bridge at output end for negative voltage generation. In Mokhberdoran and Ajami (2014) and Gupta and Jain (2013), the researchers have proposed asymmetric and asymmetric design of new MLI, which focuses on reducing the total standing voltage (TSV) as well as the blocking voltage of the switches.
T-type-based MLI is reported in Majumdar et al. (2020) and Mahato et al. (2019aMahato et al. ( , 2019c. In Majumdar et al. (2020), MCMLI is presented that uses a T-type inverter for the level generation part (LG) along with the voltage tripler circuit. Two back-to-back T-type inverters with a developed H-bridge are used (Mahato et al. 2019a) to generate the 31 voltage levels with ten power switches. This arrangement reduces the TSV of the inverter as well as the blocking voltage of the switches. Further, a T-type inverter is proposed in Mahato et al. (2019c), capable of generating both the positive and negative voltage levels where each cell or each T-type unit can generate a three-level output. A three-phase extension of this topology is possible with a reduced number of switches. The switch-diode-based configuration has been reported by the researchers in Mahato et al. (2020aMahato et al. ( , 2020bMahato et al. ( , 2019b. In Mahato et al. (2020b), H-bridge is employed for negative voltage-level generation leading to high-voltage stress across each of the power switches. In Mahato et al. (2020aMahato et al. ( , 2019b, new ideas for the negative voltage-level generation by using a halfbridge cell instead of a full-bridge circuit are being introduced. Thus, both the power switches in a half-bridge cell experience the high-voltage stress across half-bridge switches, and hence, the topology is not suitable for highvoltage applications. Similarly, the topologies with a full H-bridge (Lee et al. 2018b;Babaei et al. 2014b;Babei and Hosseini 2009;Alishah et al. 2015;Mahato et al. 2020b) restrict their applications for high voltage, and hence, the voltage stress across switches also increases considerably.
In Jagabar Sathik et al. (2020) and Choupan et al. (2017), switch-diode cell-based MLI is proposed where a prototype of 9-level inverter in Jagabar Sathik et al. (2020) and 13-level inverter in Choupan et al. (2017) are presented. In Jagabar Sathik et al. (2020), a large number of clamping diodes and capacitors are required, whereas a large number of clamping diodes and DC input sources are required (Choupan et al. 2017). Applications to the highly inductive loads are limitations of the inverters introduced in Jagabar Sathik et al. (2020) and Choupan et al. (2017). A prototype of the 13-level inverter (Sedaghati and Majareh 2019) and 15-level inverter (Anand and Singh 2020) are proposed to reduce the overall required power electronic switches. This led to increases in the required number of the DC sources, clamping diodes (Sedaghati and Majareh 2019) and bi-directional switches (Anand and Singh 2020).
In this paper, a generalized MLI (based on SDC module and T-type inverter) is proposed. The motivation of the work is the reduction in the number of power switches, DC sources, blocking voltage across the switches, and total standing voltage (TSV) for more levels. The organization of this paper is as follows. Section 2 deals with the working principle of the proposed generalized modular MLI. This section includes an exhaustive explanation regarding the generation of output voltage levels for two cascaded modules for two cases (case-I and case-II). The control strategy for the proposed 7-level inverter for different modes of operation and switching pulse patterns is described in Sect. 3. In Sect. 4, comparative studies of the different performance parameters have been carried out using the proposed MLI to compare with the recent MLI topologies and validate its efficacy for pragmatic applications. The simulation, as well as experimental results, are included in Sect. 5. The power loss of the inverter is calculated in Sect. 6, and the conclusion is drawn in Sect. 7.

Proposed modular MLI, extension and applications
The generalized structure of the proposed modular MLI consists of 'n' number of switch-diode cells (SDCs), and six unidirectional switches (S a , S a 0 , S b , S b 0 , S c , S c 0 ) along with a DC source V f (= V dc ) are shown in Fig. 1a. Each SDC (say n th SDC) of the generalized inverter module consists of a unidirectional switch (S n ), a diode, and a DC source of voltage V n . The inverter module having two numbers of SDCs with V f = V dc and DC link voltages (V 1 and V 2 ) of magnitude 2V dc and 4V dc as shown in Fig. 1b can generate a 15-level voltage across the inverter output with the magnitudes of 0, ± 1V dc , ± 2V dc , ± 3V dc ,-± 4V dc , ± 5V dc , ± 6V dc , and ± 7V dc as shown in Table 1.
However, the inverter module with a higher number of SDCs ([ 2), the blocking voltage of the switches (S b , S b 0 ) as well as (S c , S c 0 ) becomes comparative much higher than the other switches, which increase the overall TSV of the MLI as shown in Table 2 and further discussed in Section 4. Thus, for increasing the voltage levels further, several 15-level inverter modules can be cascaded to achieve comparatively lesser TSV than the single-inverter module with a large number of SDCs. A generalized cascaded MLI consists of' number of such 15-level inverter modules as depicted in Fig. 1b. Table 1 shows voltage generation of a 15-level inverter module-1 (V a1b1 ) with voltage magnitude 0, ± 1V dc , ± 2V dc , ± 3V dc , ± 4V dc ,-± 5V dc , ± 6V dc , and ± 7V dc . Thus, the cascaded MLI with two 15-level inverter modules, having identical DC link voltages for module-1 and module -2 (case-I), can generate a 29-level voltage. The generation of output voltage levels (V a1b2 /V dc ) of a 29-level inverter (case-I) by combining two 15-level inverter modules (in cascade) is depicted in Table 3, which ranges from -14 to ? 14 (14 positives, 14 negatives, and a 0 voltage levels).
However, with different DC link voltages, the cascaded combination of the aforementioned inverter modules can generate much higher voltage levels with the same number of components (case-II), as depicted in Table 1. The module-2 can generate 15 voltage levels (V a2b2 /V dc ) of magnitude 15 times than the module-1 (? 105, ? 90, …, -90, -105). Thus, the output voltage levels (V o /V dc ) of the 225-level inverter can be generated by combining (cascading) the same two inverter modules with different DC link voltages (case-2) in module-2 (15 times than module-1) ranging from -112 to ? 112 (112 positives, 112 negatives, and a 0 voltage levels) is depicted in Table 4. Several ways can be adopted to obtain different isolated DC sources required for the above type of MLI.
In this paper, a single-phase multi-winding transformer along with the diode rectifiers and capacitive filters [35] are used to obtain the isolated DC sources for supplying the proposed asymmetrical MLI for experimental verification purposes. For the proposed 7-level inverter, a low-power multi-winding transformer (two secondaries) with turns ratios 1:1 and 1:2 is used along with diode rectifiers and filter capacitors for obtaining the DC link voltages (V f and V 1 ) of magnitude 107 and 214 V (in the ratio of 1:2) as shown in Fig. 2.
Moreover, a single-phase variac may be used to adjust the required DC link voltage magnitude. However, the proposed MLI structure can be implemented with renewable energy sources, also such as photovoltaics, energy storage devices, and fuel cells, etc. The output of the renewable energy sources (DC nature) can be further converted to the appropriate isolated DC voltages by incorporating isolated DC-DC converters (Gupta and Jain 2014).

Operation of the proposed 7-level inverter
For analyzing the performance of the proposed modular MLI, the 7-level inverter of the proposed configuration is considered and implemented in the laboratory. The proposed 7-level inverter module has one switch-diode cell (SDC) and six unidirectional switches, as shown in Fig. 3a. The DC link voltages (V f and V 1 ) are chosen as V dc and 2V dc (in the ratio of 1:2) to obtain seven voltage levels of magnitude 0, ± 1V dc , ± 2V dc , and ± 3V dc using the sinusoidal PWM (SPWM) technique.
The detailed operation of the 7-level inverter under different modes (or states) is also explained with the help of the power flow diagram in this section. Abundant modulation techniques and control paradigms have been introduced, such as sinusoidal PWM (SPWM) (Gupta and Jain 2013), selective harmonics elimination (SHE-PWM) (Babaei et al. 2014c), multicarrier PWM, or level-shifted PWM (LS-PWM) (Mahato et al. 2019c), space vector modulation (SVPWM) (Babaei et al. 2014b), nearest level control (Majumdar et al. 2020) and others. For the proposed 7-level inverter, six triangular carriers are required that comprise three upper carrier signals C u1 , C u2 , C u3, and three lower carrier signals C l1 , C l2 , C l3 , respectively. The logic behind the control strategy is welldepicted in Fig. 3b. If the upper carrier is lower than the reference signal, the comparator generates 'ui' and generates 'ui À 1' if the condition is not satisfied. Similarly, for a lower carrier being lower than the reference signal, the comparator generates 'Àðli À 1Þ' and generates 'Àli' if the condition is not satisfied. This proposed 7-level inverter switching technique can be executed using any of the above modulation schemes. However, in this paper, a carrier-based LS-PWM technique is adopted for the implementation of a 7-level inverter. Six carrier signals disposed of vertically are compared with the sine reference signal to obtain the switching states S(t) of the inverter, which is further decoded to generate gate pulses of the power switches. The gate pulses thus obtained are used to generate the corresponding respective output voltage levels.
For a generalized n-level inverter, '(n-1)/2' number of triangular carriers are required on the top as well as the bottom of the zero references. Figure 4 shows the power flow diagram of the proposed 7-level inverter at various operating modes. Say, in operating mode-1 of the inverter to generate ? 3V dc , and power switches S a , S b 0 , S 1 , and S c should be ON in such a way that the two DC sources, V f = V dc and V 1 = 2V dc are connected to the load. Similarly, under mode-7 to generate the voltage -3V dc , the power switches S a 0 , S b , S 1, and S c 0 are conducting, which connects two DC sources V f = V dc and V 1 = 2V dc across the load in the reverse direction. Either the combinations of switches S a , S b , and S c or S a 0 , S b 0 , and S c 0 can be turned ON to obtain zero voltage level. In the same way, the operation of the circuit under the remaining modes can be explained with the help of Fig. 4.
Thus, it is observed that except for the SDC cell, all the other power switches are operated in a complementary fashion to generate the positive and negative voltage levels. Figure 5a and Fig. 5b show the switching pulse pattern of Fig. 1 Proposed asymmetrical MLI topology a A generalized switch-diode cell (SDC) inverter module, b Generalized cascaded MLI with 'm' number of 15-level modules the respective power switches for the proposed 7-level inverter obtained from simulation and experimental set-up (dSPACE-1103) at a switching frequency of 1 kHz. The losses are needed to be calculated using the switching pulse pattern of 1 kHz to obtain the efficiency of the proposed inverter is shown in Fig. 5b. A detailed explanation of the loss calculation is discussed in section-6.  Mahato et al. 2019aMahato et al. , 2019cMahato et al. , 2020aMahato et al. , 2020bMahato et al. , 2019bJagabar Sathik et al. 2020) for comparison in terms required the number of total power switches (N ps ), DC sources (N DC ), clamping diodes (N cl ), unidirectional switches (N us ), bi-directional switches (N bs ), and output voltage levels (N vl ). Generalized formulae for all the aforementioned parameters are also derived and presented in Table 5. Moreover, for better comparison, the graphical representation of the number of power switches (N ps ) and the number of voltage levels (N vl ) is presented in Fig. 6a. Similarly, the graph between the number of DC sources (N DC ) and the number of voltage levels (N vl ) are also plotted, as presented in Fig. 6b. It can be concluded from Fig. 6a that the proposed MLI stands best in terms of required power switches, whereas Fig. 6b depicts that the proposed MLI is comparatively better than most of the other MLI topologies in terms of required DC sources. Regarding comparison in terms of voltage levels per switching device used in the inverter, it is barely possible to plot a graph for all MLI topologies considering the same number of voltage levels. Therefore, N ps = 10 is chosen to cover up most of the MLI topologies referred to in Fig. 6c, and the graph of the LSR of the proposed topology, as well as other MLI topologies, is plotted and presented.
Regarding the comparison of diodes, the authors have differentiated the diodes as clamping diodes and diodes associated across the bi-directional switches. These four antiparallel connected diodes across the bi-directional switches are only considered for comparison. The antiparallel diode connected across the unidirectional power switches are not considered for the comparison as Table 1 Output voltage of the proposed two cascaded 15-level inverter modules Case-I (29-level inverter) (Similar DC link voltages of inverter Module-1 and Module-2 for modular design) Case-II (225-level inverter)(Different DC link voltages in module-1 and module-2 for maximizing voltage levels) Output voltage levels:  Table 3 Output voltage levels of two 15-level inverter modules in cascade to generate 29-levels (case-I)   Arun and Noel (2018), and the proposed MLI stands inferior to MLI discussed in Babaei and Gowgani (2014;Mahato et al. 2020b). Despite being inferior in terms of using more clamping diodes, the proposed MLI circuit cannot be neglected in other terms of performance parameters, i.e., power switches, DC sources, TSV, and LSR, as depicted in Fig. 6a Majumdar et al. (2020);and Mahato et al. (2019aand Mahato et al. ( , 2019cand Mahato et al. ( , 2020a are considered because the aforesaid MLI structures contain bidirectional switches with four antiparallel connected diodes. It is to be noticed that the bidirectional switches made of two unidirectional switches are not considered for comparison because an antiparallel diode is connected across the unidirectional switch are inbuilt available in the power switch from the manufacturer side. While extending one module of the proposed MLI topology, the inverter can be used for low and mediumvoltage applications. Thus, the extension of only one module requires only eight diodes and a very lesser number of clamping diodes. Moreover, the proposed MLI can also be used for high-voltage applications when cascading the modules of the proposed inverter. Thus, the cascading of modules for achieving the higher voltage levels would require only a comparatively higher number of diodes and the nominal number of clamping diodes. However, the proposed MLI circuit cannot be neglected in other terms of performance parameters, i.e., power switches, DC sources, TSV, and LSR, as depicted in Fig. 6. Moreover, for higher voltage levels, cascaded structure Fig. 6d depicts the plot between the TSV versus the number of voltage levels, and it has been noticed that though the TSV increases with the number of voltage levels, the TSV of the proposed MLI is at par with most of the other proposed MLIs developed in the recent years. While plotting the graph, the authors not considered the blocking voltages of the diodes (either clamping diodes or the diodes across the bi-directional switches). The total standing voltage (TSV) for different MLI topologies are calculated concerning the number of voltage level obtained is plotted as depicted in Fig. 6d. The To have an idea of the overall cost of the converter, the researcher must be aware of two factors, i.e., the total number of required power components and TSV of the inverter. In the proposed work, the value of TSV for the proposed 7-level, 9-level, 11-level, 13-level, 15-level, and 25-level inverter is calculated by determining the total sum of all the blocking voltages across each available switches under different operating switching states. The blocking voltage of all the power switches is depicted in the form of a bar graph, as specified in Fig. 7. Moreover, the maximum values of the blocking voltage of all the power switches (S a , S a 0 , S b , S b 0 , S c , S c 0 , and S 1 ) under all the switching states   are V Sa , V Sa 0 , V Sb , V Sb 0, V Sc , V Sc 0, and V S1 , respectively, and hence the maximum value of the TSV for the proposed 7level is given in Eq. (1), Similarly, the maximum value of the TSV for the proposed 9-level, 11-level, 13-level, 15-level inverter with two SDCs having different DC link voltage ratios and cascaded 25-level with two SDCs are found to be 22V dc , 28V dc , 34V dc , 40V dc, and 68V dc as derived in Eq. (2)-(6) as: For the 9-level inverter, the blocking voltages and TSV are For the 11-level inverter, the blocking voltages and TSV are For the 13-level inverter, the blocking voltages and TSV are For the 15-level inverter, the blocking voltages and TSV are For the 25-level inverter, the blocking voltages and TSV are where MLI of symmetrical nature is the most operational in industrial because photovoltaic farms (wind farm, HVDC,.…) have the same rated output. Although the PV panels can be a factor of each other in the output voltage by connecting in a cascaded fashion that can be used for asymmetric MLI in PV farms, thus reducing the power components. Nevertheless, the variety of DC sources are observed in asymmetrical CHB based on the trinary fashion (V dc , 3V dc , 9V dc , 27V dc , 81V dc , 243V dc , 729V dc …), Novel H-bridge (Babaei et al. 2014a) and proposed inverter module in case-II. There is some consideration as follows: I. Although the TSV is in a reasonable range for CHB (trinary fashion), but the voltage stress on these power switches for the higher level H-bridges module (27V dc , 81V dc , 243V dc , 729V dc …) becomes too high. For example, the stress of four switches on the first step is 1V dc , and the second step is 3V dc ; the third step is 9V dc, and the fourth step is 27V dc, and so 0 2 4 6  8  10  12  14  16  18  20  22  24  26  28  30  32  34  36  38  40 Proposed multi-level inverter 7-L 9-L 11-L 13-L 15-L

25-L
Blocking voltage on each power switch of proposed MLI topology for different voltage levels on. Therefore, these modules should be provided with a different and higher rate of switches, which increases the overall cost of the inverter. II. Accessibility to the variety of DC sources (27V dc , 81V dc , 243V dc , 729V dc …) is not feasible.
III. Availability of the high practical magnitude of DC sources (27V dc , 81V dc , 243V dc , 729V dc …) is needed for the series connection of several solar panels for the solar farm application. Moreover, it also requires a huge area with absorbing for irradiation of solar. Partial shading in high-amplitude sources due to sudden atmospheric obstacles such as clouds cause a deep drop voltage.
This paper presented the module in two modes of extension that case-I is more practical for industrial. Although proposed MLI with case-II extension, CHB with trinary algorithm and extend H-bridge (Babaei et al. 2014a) is satisfied mathematically and complexity in practical applications. It can be clearly understood from Fig. 7 that for an inverter module with an increased number of SDCs (for higher voltage levels), the blocking voltage on each switch increases, especially on the switches pair S b & S b 0 and S c & S c 0 . Thus, for the practical implementation, the cascaded structure of lower-voltage-level modules (with SDCs B 2) can be used for higher-voltage applications. Moreover, the amount of TSV also increases.

Simulation and experimental results
The experimental set-up of the proposed inverter comprising of the different required components such as variac arrangement for the different required sources rectified DC supply from an isolated transformer with capacitor filter, Delay board, and power circuit arrangements with the driver circuits, DSO, and the RL-Load is depicted in Fig. 8. In the driver circuit, an optocoupler TLP250 is employed to amplify the pulses that help to drive the gate of the power switches and provide isolation from the power circuit and control section of the circuit. Figure 9a depicts a 7-level inverter with 1 SDC having input DC voltage sources as V f = V dc = 107 V, V 1-= 2V dc = 214 V. Figure 9b depicts 9-level inverter with 2 SDCs having input DC voltage sources magnitude as V f-= V dc = 55 V,V 1 = V dc = 55 V, V 2 = 2V dc = 110 V, and Fig. 9c depicts 25-level inverter (cascaded module topology) having input DC sources magnitude as (V 1f = V dc-= 10 V, V 11 = 2V dc = 20 V, V 12 = 3V dc = 30 V): (V 2f = V dc = 10 V; V 21 = 2V dc = 20 V; V 22 = 3V dc-= 30 V). The simulation of the proposed topology and cascaded module topology is carried out using multicarrier PWM in MATLAB/SIMULINK at the switching frequency of 3 kHz. In a module with 1 SDC, 7-level is the maximum voltage level obtained from the proposed topology.
The proposed 7-level topology is tested at R = 65X, L = 65mH. Four different voltage levels 9-level, 11-level, 13-level and 15-level are obtained by considered four different ratio of DC sources ( , respectively, where 15-level is the maximum voltage level obtained from a module with two SDC topology. Different load conditions are considered for the different aforesaid MLIs. The different values of RL loads are considered for 9-level, 11-level, 13-level, and 15-level as R = 130 X, L = 50 mH, R = 123 X, 50 mH, R = 100X, L = 50 mH, and 115 X, L = 50 mH, respectively. Experimental work is carried out in the laboratory to develop the proposed module topology for different voltage levels with different DC source ratios, as mentioned earlier. Figures 10 and 11 show the simulation and experimental results of load voltage, load current for 7-level, and 9-level, respectively. Figures 10a and 11a depict the experimental results of load voltage and current at M i = 1 for 7-level and 9-level, respectively. The experimental @ 160V/div @ 7.80A/div @ 160V/div @ 7.80A/div results of load voltage and current for 7-level (M i = 0.5) and 9-level (M i = 0.4) are also incorporated to verify the effectiveness of the proposed MLI. The simulation result of the load voltage, load current, and % total harmonic distortion (THD) for the proposed topology has been analyzed in the MATLAB platform, as shown in Figs. 10c-d and 11c-d, respectively. The fundamental voltage of 7-level and 9-level is 319.9 and 119.4 V, respectively, whereas the %THD for the 7-level and 9-level is 18.35 and 12.60%, respectively. The simulation result of load voltage and load current for 11-level, 13-level, 15-level, and 25-level is depicted in Fig. 12a-d, respectively. The experimental result of load voltage and load current for the aforesaid proposed inverters (11-level, 13-level, 15-level, and 25-level) is depicted in Fig. 13 (a-d) with the different aforementioned magnitude of DC voltage sources having a peak of fundamental voltage as 150, 126, 133, and 120 V, respectively. Figure 13d shows the 25-level inverter based on cascaded module topology with two switch-diode cells (SDCs). Further, the analysis of %THD is done for the inverter generating 11-level, 13-level, 15-level, and 25-level and corresponding %THD found to be 10.12, 8.33, 7.37, and 4.22%, respectively, as depicted in Fig. 14a-d respectively.
Thus, it can be said that the %THD for voltage levels is reduced with increased output voltage levels. The peak output voltage magnitude and output current of the 9-level inverter is 220 V (peak voltage) and 1.68A (peak current), having a value of R = 130X and L = 50mH. The experimental results of the output voltage and current of the basic 9-level inverter for different modulation indices M i = 0 to M i = 1.0 are shown. The transition of modulation indices ranging from M i = 0.2, M i = 0.4, M i = 0.7, and M i = 1.0 having specific voltage output of 3-level, 5-level, 7-level, 9-level, and 11-level are shown in Fig. 15a. In addition, the experimental result of sudden load change is also incorporated in this paper from R = 130X, L = 50mH to R = 200X, L = 50mH, as depicted in Fig. 15b.
As the proposed topology possesses the merits of lower switches count, the proposed topology with its cascade connection finds suitable application in renewable energy. Figure 16 shows the integration of the proposed topology with a solar PV system. The three dc voltage sources are replaced by three solar panels with DC/DC converters which are used to change the output capacitors. The output voltage of these two solar panels decides the number of levels. As the proposed topology works on binary voltage configuration for the 7-level output voltage, i.e., V 1 /V 2 = 2, @ 100V/div @ 2.40A/div @ 96V/div @ 2.30A/div Here, (V PV#1 , d c#1 ) and (V PV#2 , d c#2 ) represent the voltage and duty cycle for the solar panels and DC/DC converters, respectively.

Power loss of the 7-level inverter
The proposed MLI aims to get rid of the power losses and experience an efficient system. The power calculation is calculated as the same as approached in (Mahato et al. 2019b;Jagabar Sathik et al. 2020). The total efficiency of the inverter discussed in this paper is determined by calculating the conduction as well as the switching losses for the proposed 7-level inverter. In order to find the efficiency, parameter of the power switch, IGBT CT60AM-18F, i.e., V on, IGBT = 1.3 V, V on, Dio = 1.5 V, R Dio-= 0.01X, R IGBT = 0.11X, b = 3 are considered for the calculation of efficiency.

Conduction losses
Conduction losses are related to the dissipation of the instantaneous power during the conduction period of a power semiconductor switch. During the turn-on period, the product of ON-state voltage drop, V on (t), and the amount of current, I(t) allowed by the device yields the dissipated power across a switch that can be expressed as, The total conduction losses (instantaneous) of the proposed MLI is the sum of the instantaneous value of conduction loss in the power switches (unidirectional) can be written as Eq. (8), whose value depends on various factors such as load type, switching pulse pattern, output voltage levels, and so on. where n uni = number of unidirectional switches in the current path at any instant of time. P con,uni = Power loss in any unidirectional switch. The conduction losses (instantaneous) of any bidirectional switches P con, uni (t) carrying load current, I = I L sin (xt), can be expressed as, Thus, putting the values of power switch parameters, the equation is modified as follows: P con;uni ¼ 2:8 Â I L Â sin xt ð Þ þ 0:01 Â I 2 L Â sin 2 xt ð Þ þ 0:11 Â I 4 L Â sin 4 xt ð Þ ð11Þ Figure 5 shows the pulse pattern of the proposed 7-level inverter. For the sake of simplicity in the calculation, the pulse pattern for the proposed topology is obtained at 1 kHz to find the average conduction losses. However, with an increase in switching frequency, conduction losses remain constant because any change in the operating frequency of the power switches does not change the load current. Summing of the integrated values of ON time pulse duration gives the conduction losses. Conduction losses depend on the load current and switching frequency. The power switches operate at fundamental switching frequency incurs higher conduction losses. The average conduction losses for one cycle can be calculated by observing the operating time of the different power switches from the pulse pattern obtained by simulation of the proposed inverter, as shown in Eq. (12) at 1 kHz switching frequency.

Switching losses
The total switching power losses (P sw ) of the proposed topology is the sum of losses incurred in all available power switches. The switching losses depend on the switching frequency of the power switches, and their @ 50V/div @ 3A/div @ 50V/div @ 3A/div @ 50V/div @ 1.76 A/div @ 50V/div @ 2 A/div (c) (d) Fig. 13 Experimental results of inverter designed in laboratory for different DC source ratio, a 11-level inverter with 2 SDC (V f : V 1 : V 2 = V dc :2V dc :2V dc ) at load of R = 123X, L = 75mH, V pk = 150 V, I pk = 1.2A. b 13-level inverter with 2 SDC (V f :V 1 :V 2 = V dc :2V dc :3-V dc ) at load of R = 100X, L = 75mH, V pk = 126 V, I pk = 1.33A. c 15-level inverter with 2 SDC (V f :V 1 :V 2 = V dc :2V dc :4V dc ) at load of R = 115X, L = 75mH, V pk = 133 V, I pk = 1.15A. d 25-level cascaded module inverter with 2 SDCs (V 1f :V 11 :V 12 = V 2f :V 21 :V 22 = V dc : 2V dc : 3V dc ) at load of R = 120X, L = 75mH, V pk = 126 V, I pk = 1A values can be calculated from the switching pulse pattern over one cycle or one fundamental period of the inverter switches.
where assuming, 'a' is a constant, i.e., a¼I t on þ t off ð Þ =6 for a specific value of load current (rms) flowing through IGBTs.
For the proposed 7-level topology, the blocking voltages across the power switches were found to be V sa = V dc , V sb = 3V dc , V sc = 2V dc , V sa 0 = V dc , V sb 0 = 3V dc , V sc 0 = 2V dc and V s1 = 2V dc . At inverter switching frequency (f s ) of 1 kHz with fundamental frequency (f o ) of 50 Hz, the operating frequency of the power switches f sa , f sa 0 , f sb , f sb 0 , f sc , f sc 0 and f s1 are approximately (f s /13), (f s /14), (f s /3), (f s / 4), (f s /7), (f s /8) and (f s /4) respectively. Thus, the total losses (switching losses) incurred in the proposed 7-level inverter can be expressed as Eq. (13). However, with an increase in switching frequency, conduction losses remain constant, whereas switching losses increase proportionally. The switching loss depends on the load current, blocking voltage across power switches, and the switching frequency. Thus, it can be concluded that the lower the blocking voltage, the lower would be the switching losses. Power switches operated at higher switching frequency result in comparatively lower conduction losses than the conduction losses that occur in the power switches operated at the fundamental switching frequency. The switching losses of the switches at fundamental switching frequency is neglected as it contributes to the output voltage (Mahato et al. 2019b). The calculated value of the switching frequency at 1 kHz is further multiplied by the chosen frequency for the experimental work. As calculated in Eq. (13), the switching losses were found as 3aV dc f s at 1 kHz, whereas at switching frequency of 3 kHz, the switching losses would be 3*3aV dc f s , i.e., 9aV dc f s . For a certain value of the load or varying load conditions, the blocking voltage across the switches remains in the same ratio. Only four switches conduct for each output voltage level. Henceforth, the switching losses are very small. The calculated efficiency and the losses for the proposed MLI are at par with the efficiencies calculated for other MLIs. Finally, for the proposed 7-level inverter, the measured power at the input and output is about 732.62W and 704W, respectively, and the inverter efficiency is about approx. 96.093%.

Conclusion
The proposed generalized modular MLI has unique advantages related to a lesser number power count for a comparatively higher voltage level, having reduced total standing voltage (TSV) and blocking voltage. The proposed MLI consists of switch-diode cells. Seven-level can be generated using 1 SDC, whereas 15-level can be generated using 2 SDCs. Two cases are implemented for determining the DC links magnitudes of the inverter. The important advantage of this module is its capability to generate negative polarity levels without any H-bridge inverter, while cascading the modules with 2 SDCs, 29-level (case-I), as well as the 225-level (case-II), is obtained using 18 power switches. The experimental verification has been carried out under steady-state and under dynamic loading conditions under the resistive-inductive load at a switching frequency of 3 kHz after being tested in the MATLAB simulation. This topology is thus significantly competitive, using a relatively lesser number of DC sources and semiconductor devices, having lower TSV, blocking voltage and better level-switch ratio. The Appendix Table 6 shows the circuit parameters in simulation and experimental tests.
Funding Not funded by any organization.
Data availability No third-party material is used.
Code availability No code is available.