Wideband High Gain Active Feedback Transimpedance Amplifier

A new wideband high gain CMOS transimpedance amplifier is presented without using any inductor. In the proposed TIA, gain enhancing path is introduced in the active voltage-current feedback TIA topology to increase both the gain and bandwidth. This path increases the transconductance of the proposed TIA which reduces the input resistance and leads to bandwidth extension. Additionally, for utilizing the benefit of this topology, cascading of common source stage is also done to increase the gain further without deteriorating the bandwidth. Mathematical analysis is also performed to evaluate both the gain and bandwidth enhancement. These analyses are supported by simulations that are done using TSMC 0.18 µm CMOS technology with the input photodiode capacitance of 0.3 pF. The proposed TIA occupies 0.019 mm2 area and consumes 3.2 mW from 1.8 V supply voltage. The transimpedance gain of the proposed TIA is found to be 57.15 dBΩ over the bandwidth of 6.5 GHz. The input noise is 17.16 pA/√Hz.


Introduction
The significant increase in the demand of huge data rates has motivated inventors to explore optical communication systems (OCS) that are apt to handle this requirement. Transimpedance amplifier (TIA) is the very crucial front-end block at the receiver link of OCS. TIA work is to convert small input current signal into an amplified voltage level. Therefore, gain is an important parameter of TIA and it should be as high as possible. Few design techniques are reported in the literature to boost the gain which includes positive feedback technique [1], self cascode structure [2,3] and cascading of buffer stages [4]. Positive feedback increases the gain by reducing the overall output conductance, however, it has stability issues. Self cascode structure also increases the gain but it enhances the voltage headroom. Cascading of stages increases the gain but at the expense of power dissipation and bandwidth. Apart from gain, bandwidth is also an important parameter which is restricted due to large input photodiode capacitance. Various bandwidth enhancement techniques are reported such as inductive peaking [5,6], capacitive degeneration [7,8], capacitive feedback [9,10], negative capacitance [11], common gate (CG) [12] and regulated cascode (RGC) [13,14]. Both the inductive and capacitive compensation increase the bandwidth but they occupy the large chip area. CG topology also gives a wide operating frequency range but yields relatively higher noise. RGC is the very common topology to design TIA due to its high stability, low input impedance and wide bandwidth. On the other hand, it has higher power dissipation and headroom voltage.
In this work, active voltage-current feedback (AVCF) TIA topology [15] is used which provides low input and output impedances. In this topology, thegain enhancing pathis introduced insuch a way that it increases both gain and bandwidth. This path increases the transconductance and thereby, reduces the input resistance which leads to bandwidth extension. Moreover, a common source (CS) stage has been cascaded to use the advantage of this topology to increase the gain further without deteriorating the bandwidth.
AVCF topology is reviewed in Sect. 2. The proposed TIA design is discussed in Sect. 3. In Sects. 4 and 5, noise analysis and simulation results are discussed, respectively. Section 6 concludes the paper.

Active Voltage-Current TIA
The TIA circuit based on AVCF topology is shown in Fig. 1 in which transistor M 1 provides feedback path and decreases the output and input resistances [15]. In this circuit, transistor M 1 itself converts the current into a voltage whereas other topologies use resistor to do the same. The drain current of transistor M 1 is given by [15]: The input and output resistances are given in Eqs. (2), and (3) respectively [15].
where R 1 is the total resistance at the input port due to both current source CS 1 and the output resistance of transistor M 1 . The transimpedance gain of the circuitis given by [15]: where C 2 and R 2 are the sum of parasitic capacitance and intrinsic resistance at the output port respectively. C 1 is the total capacitance at the input port. From Eq. (4), the transimpedance gain at low frequency has been deduced as: Since the output impedance of TIA (shown in Fig. 1) is very low, therefore, cascading of the gain stage can be done without affecting the bandwidth. The number of gain stages can be chosen based on the trade-off that exists between gain, power consumption and noise.

The Proposed TIA
The proposed circuit of TIA is presented in Fig. 2 where C pd is input photodiode capacitance and I in is photodiode current. The active voltage-current feedback (AVCF) TIA is formed by transistors M 1 and M 2 in which transistor M 1 is providing voltage-current feedback. In AVCF TIA, modification has been done by introducing gain enhancing path which includes resistor R p and transistor M p . This path not only increases the gain but also extends the bandwidth. It also increases the transconductance of the amplifier which leads to decrement in the input resistance. Additionally, a common source (CS) stage (M 3 and R D ) has also been cascaded with TIA to increase the gain further. This cascaded voltage gain stage does not affect the bandwidth due to the low output resistance of TIA as mentioned in Sect. 2. The small signal analysis is performed to show the gain enhancement and bandwidth extension.
In Fig. 3, the small signal equivalent circuit is depicted in which g mi (where i = 1, 2, 3, P) are the transconductance of transistors M i (where i = 1, 2, 3, P) respectively. C in is the total capacitance at the input node which comprises of gate-to-source capacitance (C gsp ) of transistor M p and the capacitance of photodiode. R 1 is the overall resistance at the input side and R 2 is the total resistance at the V o (shown in Fig. 2) node. The transfer function is determined by applying Kirchhoff's current law (KCL) at nodes V 1 ,V 2 , V 3 , and V out shown in Fig. 3. Body bias effect is neglected because g mp,2 > > g mbp,2 . C gs0 is the summation of the gate-to-source capacitances of M 1 and M 3 whereas C gdm is the total of the gate-to-drain capacitances of M p and M 2 .
The transimpedance gain is realized as: where Z(0) is transimpedance gain at low frequency and is obtained as: Assuming g m r o > > 1, Eq. (7) can be estimated as: On comparing Eqs. (5) and (8), it can be determined that gain is enhanced by introducing path (M p and R p ) and the common source stage (M 3 and R D ).
The dominant pole can be calculated as: The input resistance is obtained as: On comparing Eqs. (2) and (14), it is found that input resistance of proposed circuit is diminished by introducing path (M p and R p ) which isolates input photodiode capacitance and thereby, extends the bandwidth. In the proposed circuit, biasing is provided in such a way that the transistors are operated in a saturation region. Aspect ratios of transistors are selected in order to minimize the trade-offs between gain, bandwidth and noise.

Noise Analysis
The input of the transimpedance amplifier is photodiode current which is very small in magnitude. Therefore, noise becomes an important parameter for TIA which has to be analysed. Main noises exist in TIA are flicker and thermal noise [16]. The small signal equivalent circuit for noise analysis is depicted in Fig. 4.
The total input-referred noise of modified ACVF-TIA is obtained by: (1 + r op g mp )(r oP + R P ) (g m1 + g mp )(r op + R P )r o1 r op + r op g mp + 1 .  21), it is found that the value of the resistance R D and size of transistor M 1 should be high enough to minimize noise of proposed TIA. At higher frequency, noise rises due to the effect of dominating term ωC. However, the total noise of the proposed circuit would be slightly more than noise given in Eq. (21) due to cascading of the common source stage.

Simulation Result
Simulations of the proposed TIA are done using Mentor Graphics based Eldo simulation tool in TSMC 180 nm technology. The values of parameters of proposed circuit are mentioned in Table 1. For the comparison purpose, AVCF-TIA has also been simulated using the same technology and tool with similar circuit parameters as that of proposed TIA. Figure 5 represents the frequency responses of AVCF, AVCF with CS stage and proposed TIA (AVCF + CS + CGP). This figure shows that the proposed TIA circuit offers highest gain (57.15 dBΩ). Further, it also displays improvement in bandwidth, which gets extended to 6.5 GHz as compared to 1.7 GHz of AVCF with CS stage. All these improvements are obtained in proposed TIA while consuming only 3.2 mW power. Figure 6 presents the DC transfer characteristic of proposed TIA, which shows an almost linear relationship between input current and output voltage. The transient response of proposed TIA is presented in Fig. 7. It is observed that the swing of output voltage is nearly 10 mV for 10 µA input current. The variations in frequency response for different photodiode capacitances (C pd = 0.1 pF, 0.2 pF, 0.3 pF and 0.4 pF) and at different temperatures are presented in Figs. 8 and 9, respectively. It can be concluded from Fig. 8 that the bandwidth reduces with the increasing values of C PD . However, the variations in the bandwidth with photodiode capacitance are very low. Figure 9 shows that both the gain and bandwidth reduce with the increase in temperature. The effect of variations in temperature has been studied on DC behaviour of the proposed TIA and is depicted in Fig. 10. It can be observed that the variations in DC response due temperature changes are very nominal and the linearity is maintained. Figure 11 depicts the input-referred noise of proposed TIA which is around 17 pA/√Hz. Above simulations have been carried out using the exact values of parameters mentioned in Table 1. However, in practical environment the fabricated devices will not possess the precise dimensions and will lead to variations in the behaviour of the proposed circuit as compared to the simulated results as shown above. To show the robustness of the proposed circuit in practical environment, Monte Carlo analysis and corner analysis of the proposed TIA has been carried out. To perform Monte Carlo analysis in proposed circuit, a set of 200 samples of width of the transistors with ± 5% mismatch have been considered and the results obtained have been illustrated in Fig. 12. These results show   Further to justify the proper functioning of the proposed TIA without fail even in extreme design conditions in complete work space, the corner analysis of the proposed TIA has been performed. Since proposed TIA consist of only NMOS transistors, therefore, it has only two process corners that are Slow (S) and Fast (F). Figures 14 and 15 respectively show the frequency response and DC response of proposed TIA at different process corners. It can be observed that at the two process corners, bandwidth varies from 6.4 GHz to 7.3 GHz, while gain remains almost constant. Moreover, DC behaviour  Figure 16 presents the layout of proposed TIA which depicts that the proposed circuit occupies 0.0197 mm 2 chip area. The pre-layout and post-layout simulations are depicted in Fig. 17 which shows that the gain is the same as that of pre-layout simulation but the bandwidth is slightly reduced. Table 2 illustrates the comparative results of existing TIAs and proposed TIA. It can be observed that performance of proposed TIA is superior than all other TIAs mentioned in Table 2 except [15]. However, the gain and bandwidth of TIA presented in [15] are higher than the proposed TIA but at the expense of noise, chip area and power dissipation. Furthermore, the chip area of proposed circuit is also lesser than all other TIAs except [21]. But, other parameters of the proposed design are better as compared to [21]. Additionally, proposed circuit indicates the supremacy over other existing TIAs in terms of Figure of merit (FOM), expressed by:

Conclusion
Active feedback based TIA is proposed in which gain enhancing path is introduced to increase both gain and bandwidth. Bandwidth is extended by increasing the transconductance which reduces the input resistance. Moreover, a CS stage is also cascaded which leads to further gain enhancement without compromising the bandwidth.In the proposed TIA, gain and bandwidth both are enhanced along with both low power consumption and chip area.