Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.


Introduction
Filters have good number of applications in the area of signal processing for communication systems.In the modern communication systems like 5G, wideband frequency selection is required to achieve the high-speed data rate.To achieve high-speed data rates, FIR filters can be used because of its stability, linear phase and nonfeedback nature.FIR filters are stable due to non-feedback nature when compared to the infinite impulse response (IIR) filters, and also linear phase response is one of the reason to use FIR filters extensively.The coefficients must be symmetrical around center coefficient, which is the condition for linear phase.
The design of filter involves the selection of filter length, proper values of coefficients, delay circuits, multiplication and adder circuits.The basic operation of the filter can be implemented with the help of multiply and accumulate (MAC) blocks or shift and add algorithms.The multiply and accumulate requires 'n' bit multiplier and 'n-1' bit adder for each stage of the filter.As the number of the stages or taps increases, causes to increase more functional blocks to perform multiplication and additions.Therefore, the shift add algorithms reduces the complex functional blocks.But they consume more number of clock cycles, if we perform serial shift and add algorithm.The parallel processing of shift and add operations will increase the overall throughput of the FIR filter.The distributed arithmetic (DA) utilizes the shift and add algorithm to reduce the complexity of the circuit.Up to 50% less utilization in the number of slices and 75% decrease in utilization of LUTs for fully parallel implementations are observed (Mirzaei et al. 2007 ).
The reconfiguration of FIR filters can be achieved in different ways such as changing the filter length, increasing or decreasing the fractional delays, dynamically selecting the tap lengths and dynamically changing filter parameters.There are various methods to design reconfigurable FIR filter such as using control logic to change the filter length and introducing the fraction delays to achieve adjustable band widths.The control unit of reconfigurable filter implementation for UMTS terrestrial radio accesstime division duplex (UTRA-TDD) mobile receiver utilizes in-band and out-of-band ratios of power to select filter length (Veljanovski et al. 2003).Therefore, based on the input signal, the filter length is selected.In this method, adjacent channel selectivity (ACS) dB level can be adjusted with the help of filter length by switching the taps ON or OFF.It is the factor to determine the new length of the filter and would be reason for probability of data loss.Shaver is the signal used for changing the tap positions ON or OFF with in the FIR structure thereby changing the length of the filter.Shaver is the average of difference between maximum filter length and modified new filter length.More value of shaver means better the reduction in filter size.The average value of difference between maximum filter length and new filter length will give the shaver value.The simulation analysis presents that if ACS increases in terms of dB value from 14 to 60 dB, shaver value reduces from 30 to 0. Therefore, as the value of ACS increases, it will not reduce the number of filter taps.
Another method called adjustment fractional delay method is involved in the modification of delay units present in the FIR filter.The delay operators of a fixed coefficient FIR filter with second-order FIR fractional delay (FD) structure modify the cutoff frequency (Darak et al. 2011).Hence, it changes length of an impulse response, amplitude and transition bandwidth (TBW).The cutoff frequency should be varied over a certain frequency range by varying single parameter, which in turn increases the TBW.The proposed solution for better tunable F c and TBW is to choose the fractional delay units instead of unit delays.By incorporating the fractional delays, it is observed that the cutoff frequency is only shifted to either side of the original value.
The amount of shift depends on the value of the fractional delay.The tap lengths and coefficient selection are the most important aspects of the filter design for any specific bandwidth of the filter.The folded structure reconfigurable MxN FIR filter consists of M filter modules of N order and right side module.So it adds or removes the taps from the end to increase or decrease the stopband level (Oh et al. 2006).
In addition, new transformation techniques and sphere relaxation methods are proposed to achieve low complexity and lower power utilization, and fast filters for digital signal processing and wireless applications are proposed (Lu 2006;Goel and Shanbhag 1999).These two methods are used to improve the speed of computations.The variable digital filters with modified frequency transformations are used to improve the gate count utilization which has been discussed (Darak et al. 2014;Mahesh and Vinod 2010).The cutoff frequency of the filter can be adjusted over a wide range using the frequency transformation techniques, and the substantial reduction in gate count has achieved.The multiplication of partial sub-coefficients with possible input data is calculated and stored in the chip to design hardware efficient filters (Ketha et al. 2012).The authors proposed a binary signed sub-coefficient method to implement reconfigurable FIR filter and achieved 39% area reduction than the existing architectures.The modular multiplication is done by dividing the coefficients into signed sub-coefficients and multiplied with the input data.It may reduce the size of multipliers but increases the number of additions.
There is an implementation of low power digit-based reconfigurable FIR filter with CMOS technology with full custom architecture which was discussed (Chen and Chiueh 2006).This fabricated chip operated at maximum frequency of 86 MHz, which is very low in the modern day communication systems.To design the efficient FIR filters with minimax and canonical signed digit(CSD)-coded genetic algorithms, better area utilization and low-power architecture have been achieved (Lowenborg and Johansson 2006;Pan 2010).The frequency characteristics of the FIR filters can be adjusted by varying less number of parameters that has been proposed (Oppenheim and Mecklenbrauker 1976;Chan et al. 2004).But the proposed methods will increase or decrease the actual bandwidth of the filter with 0.2p when the phase changes from 0 to 1.An efficient multiplier architecture has been proposed (Dake and Terlapu 2013;Naga Sarvanthi and Terlapu 2020;Gali and Kumar 2018) with low complexity and area efficiency.These multiplier architectures are suitable for the areas where serial multiplication operations are required.
The reconfigurable FIR filter using distributed arithmetic with dynamically changing the filter coefficients has been proposed (Bhagyalakshm et al. 2015).The multiplexer-based control unit has been used to generate the filter coefficients dynamically, which requires additional data bits for selecting the coefficients through multiplexer unit.The proposed control unit selects the required set of coefficients based on the input signal frequency; therefore, it does not require any additional inputs.A state machine-based control logic with automatic frequency band selection is proposed in the implementation of reconfigurable FIR filter.
The unfolded and folded structures of FIR filters and approximate multipliers for reusable SoC designs have been proposed (Farooq et al. 2006).The architecture proposed by the authors requires addressing schemes and handshaking signals to produce the specific frequency band width.It is difficult to apply those signals for automatic frequency bandwidth selection in commercial applications.The proposed architecture is compared with the synthesis results of the unfolded direct form (UDF) and folded direct form (FDF) FIR filter structures.These filters are implemented with 11 taps and 16 bits.To make the comparison with the UDF and FDF architectures, the proposed architecture is also implemented with same number of taps and bits.
An FIR 'Tap' is a coefficient or delay pair.Letter 'n' is the indication for number of filter taps.A change in the value of 'n' reflects the amount of memory and number of calculations required to implement the filter.As number of taps increases, stopband attenuation increases, which also results in less ripple.The proposed implementation utilizes order of the filter(n) as 24.Hence, the length of the filter, number of taps and number of coefficients are 25.
Most of the filter characteristics of the FIR filter depends on the values of coefficients.While designing FIR filter for a specific bandwidth, the first choice should be determining the coefficients denoted by h [n].The Parks-McClellan filter design method is most generic filter design algorithm recommended.
Rest of the paper is organized as follows: Steps for implementation is given in Sect. 2. In Sect.3, FIR filter coefficient selection has been discussed.Reconfigurable FIR filter design with control logic is given in Sect. 4. In Sect.5, simulation results of the reconfigurable FIR filter are given.Conclusion and future extension are given in Sect.6.

Steps for implementation
The implementation reconfigurable FIR with control logic involves four steps (see Fig. 1).The following is the description of each step.
(1) FIR filter coefficients selection: The selection of coefficients plays an important role in the design of any filter for a particular bandwidth requirement.MATLAB R2020a has been selected to generate the required set of coefficients.The hamming window technique is used for generating the coefficients.The order of the filter should be chosen properly to reduce the transition bandwidth and ripple content in the passband as well as in stopband.The initial design is implemented with order (n) 4, and now the order of each filter increases to 24.The number of the coefficients of each filter needs to be 25.The following are the set of filter coefficients of each filter.Here, h1 and h2 are the set of filter coefficients of FIR filter1 and FIR filter2, respectively.After normalizing the filter coefficients with value 64 and rounded to the integer values, we get the following values of filter coefficients.The bandwidth of the filters using the above two sets of coefficients is simulated using the MATLAB online R2020a tool.h 1 ¼ ½0; 0; 0; 0; À1; 0; 4; 4; À3; 10; À7; 6; 14; 6; À 7; 10; À3; 4; 4; 0; À1; 0; 0; 0; 0 h 2 ¼ ½0; 0; 0; 0; 0; À2; 3; 0; À7; 10; À4; À8; 14; À 8; À4; 10; À7; 0; 3; À2; 0; 0; 0; 0; 0 It is evident that x p1 and x p2 can be adjusted by selecting the proper values of the coefficients.The passband (3 dB) of the FIR filter1 is x p1 = 0.25p to x p2- = 0.45p, and for FIR filter2, it is nearly x p1 = 0.6p to x p2 = 0.8p.The ripples in the passband and stopband can be reduced by increasing the number of coefficients and precision of the filter taps and coefficients.As the number of filter coefficients are increased, the transition band width decreased, and ripple content of the stopband can be reduced with increased precision of the coefficients.The magnitude and phase responses of h 1 set of coefficients are shown (see Fig. 2a, b), respectively.Similarly, the magnitude and phase responses of h 2 set of coefficients are shown (see Fig. 3a, b), respectively.Therefore to achieve multiple frequency bands in the overall frequency spectrum, we need more number of FIR filters.The overall power consumption of the system can be minimized with the help of control logic by selecting the required band of filter.The power consumption only includes the active FIR filter and control logic.

Proposed reconfigurable FIR filter with control logic
The proposed method is to implement reconfigurable FIR filter with auto-adjustment of frequency band widths with the help of control logic.The method involves a single module in which coefficients vary dynamically in accordance with the sampling frequency.The proposed architecture consists of a control unit, FIR filters, gate and a multiplexer.Control logic consists of frequency selection circuit which always tracks the sampling frequency of the clock signal with the frequency of the reference clock signal and finite state machine to generate the necessary enable signal to FIR filters.The finite state machine in the control logic for selecting the FIR filters is shown (see Fig. 4).During state S 1 , the conditional logic verifies the value of FS.If FS = 1, it moves to state S 2 ; otherwise, it goes to state S 3 .In state S 2 , the signal EnA is 1.This is the driving signal for the FIR filter1, and in state S 3 , the signal EnB is 1, which is the driving signal for FIR filter2.Therefore, based on the values of EnA and EnB, only one of the filter is active at a time.Power consumed by the overall system mainly depends on the control logic, active FIR filter and multiplexer.
The bandwidth of the individual FIR filters depends on the internal coefficients of that filter.Here, we have taken two filters; with properly chosen filter coefficients, we can double the frequency bandwidth without consuming much power.The main advantage of this structure is to achieve specific band widths, and they may not be adjacent as well.
The schematic diagram of the individual FIR filter with shift and add structure gives signed powers of two multiplication because of left shift used in the design.The shift and architectures save power and delay when compared to the multiply and accumulation method.In multiply and accumulate logic, each time the coefficient is multiplied with sample, the value needed is stored and then added to the previous value which is present in accumulation unit.As the length of the coefficient and sample increases, it increases the multiplication and accumulation logic.So it requires more power and delay.In order to decrease the power and delay, the shift and add structure is used in the FIR filter design.
The internal schematic and main module of the implemented reconfigurable FIR filter are shown (see Figs. 5, 6).The prototype RFIR filter (n = 4) has been implemented with the help of control logic, two FIR filters and a multiplexer as the functional blocks.There are two FIR filters in the schematic diagram with equal number of coefficients, but different set between each other has been considered in the implementation of the circuit to choose the different bandwidths.Initially for prototype implementation, (i.e., filter order, n = 4), the number of taps taken in the design is 5, input data width is 8 bit (i.e., x[7:0]), and coefficient size is 3 bit.Hence, the number of output bits For the bandwidths selected in the previous section, the tap value increased to n = 24 for the same architecture.A 2 9 1 multiplexer is used to select one output from the two FIR filter.The select line of the multiplexer is derived from a two input gate.The rate at which filter operates is defined by the CLK signal, and RST signal is used to disable the complete block whenever necessary.
The control unit is the decision-making unit of the entire system, which is implemented with finite state machine with four states.The internal schematic of the control logic is shown (see Fig. 7).The frequency selection unit present in the control unit identifies whether input sampling frequency of the clock signal is above or below the frequency

Simulation and synthesis results
In the initial state, both the enable signals of frequency selection circuit are logic zero.The simulation result of the frequency selection circuit is shown (see Fig. 8).Simulation result shows up to 50 ns on time scale, and time period of the reference clock (Clk\_Ref) signal is below the time period of the clock (CLK), and FS signal becomes '1.'The time period of the Clk\_Ref signal is above the CLK signal after 50 ns on time scale.Therefore, it forces the signal FS to '0.' The macrostatistics after generating the synthesis report has been presented for both the implementations, i.e., n = 4 and 24.The macrostatistics shown in Table 1 presents the number of register transfer level (RTL) blocks required to implement complete reconfigurable FIR filter.Comparator and FSM are integral parts of the control logic.Filters mainly utilizes the resources such as adders and flip-flops.
The simulation results for n = 4 are shown (see Fig. 9).The state S 0 is the default state where EnA = 0 and EnB = 0; if start = 1 and clear = 0, then it goes to state S 1 .Based on the value of clock signal frequency, the finite state machine moves to the either state S 2 or S 3 .In the simulation result, it is evident that up to 7 lsec EnB signal is active.So that it activates the FIR filter2 and gives the output as data2.This data2 is transmitted to the final output through digital selector such as 2X1 multiplexer.Similarly after a change in the input signal at 7 lsec, it enables the state 3 of finite state machine.So that it activates EnA, and it eventually activates the FIR filter1.Hence, FIR filter1 processes the input signal and gives filtered output as data2, which is supplied to the final output d out through the multiplexer .
Simulation is carried out using ISim simulator of Xilinx ISE design suite 14.7 and synthesis tool selected as XST(VHDL/Verilog).The following area, delay and power calculations are produced on Vertex 4 FPGA with device  2, Tables 3 and 4, respectively.The reconfigurable FIR filter design for the order 24 has occupied only 6% of the overall slices available in the Vertex 4 FPGA device.The maximum frequency can be allowed to operate is 738.962MHz.Clock signal connected to synchronize all the modules inside the implemented design takes a maximum delay of 1.935 ns.The static power is the power consumed by the internal logic, and signal paths in the entire circuit is observed to be the value of 167mW, and dynamic power which depends on the clock and other signal transition is observed to be 28mW.The overall power consumption is 195 mW.
In order to compare with the existing architectures of RFIR filters with unfolded and folded direct forms, we have implemented proposed RFIR filter with 16 bits and   11 taps (Farooq et al. 2006).Therefore, the area utilization statistics presented by the author is compared in Table 5.
It is evident from the comparison in Table 5 that 11.9 and 15% of less number of slice registers are utilized in the proposed RFIR filter when compared to the unfolded and folded direct form of FIR filters, respectively.Similarly, 19.3 and 33.5% of less number of four-input LUTs are utilized in the proposed RFIR filter with multiple band of passbands when compared to the UDF and FDF 16 bit 11 tap filter.

Conclusion and future extension
In this paper, reconfigurable FIR filter with auto-adjustment of frequency selections has been implemented.In the design of RFIR, we have used two filter blocks, controller and a multiplexer.The controller block automatically selects the filter with the desired set of coefficients based on clock signal frequency.To achieve more bandwidth, we can place more number of FIR filters in parallel, and control logic requires more number states to select one FIR filter at a time.So the automatic frequency selection is achieved by selecting the required set of coefficients based on the input signal.Unlike in partial reconfigurable design, this design needs no addition and removal of filter taps.The area of the entire design is reduced with the help of shift and add method within the FIR filter.The total number of four-input LUTs utilized is 630, and the power consumed by the overall design is 195mW.The area utilization is less when compared to the unfolded and folded direct forms of FIR filters.We can save 33.5% of less number of LUTs with the proposed architecture.The proposed method gives automatic selection of different frequency band widths without consuming much area.In the proposed implementation, two frequency band widths are considered, and they can be increased to any number by increasing the number of states in the control logic.Therefore, such multiple band selection filters are best suited for 5G applications.
As the number of required band widths are increased, the proposed architecture would also suffer from increasing the area utilization linearly.Area of the overall system can

Fig. 6
Fig. 6 Top module of the proposed RFIR filter

Fig. 8
Fig. 8 Simulation result of the frequency selection logic in control unit

Fig. 9
Fig. 9 Simulation result of reconfigurable FIR for n = 4

Table 1
Macrostatistics of the Item with * is the main block.Items without * are the sub blocks of the main block