FIN Junctionless Field Effect Transistor (FIN-JLFET) with Ground Plane for Surpassing Parasitic BJT Action

The lateral band-to-band tunneling (L-BTBT) leakage mechanism increases the OFF state current and prevents the junctionless transistor from scaling. The effect of L-BTBT on FIN shaped gate Junctionless field effect transistor(JLFET) with the ground plane (GP) in oxide has been investigated. The proposed device is simulated using 3-D Silvaco TCAD and shows that it can mitigate the L-BTBT and leads to efficient volume depletion which relaxes the requirements of ultra-thin silicon thickness and high workfunction of the gate electrode. The results show significantly reduced OFF-state current and high Ion/Ioff ratio even at scaled gate length beyond 10 nm along with the reduction in drain induced barrier lowering and threshold voltage roll-off. Thus, the proposed device shows better performance at sub-10 nm node.


Introduction
Trends in the semiconductor industry are towards scaling down the transistor size to reduced delay, power, and increased packing density. However, the scaling of channel length to extreme dimensions puts stringent requirements for doping in sub 10-nm devices as it requires ultrasteep doping profiles [1]. Furthermore, devices having junctions leads to increased power dissipation as junctions are the source of leakage current. Therefore, devices with uniform doping such as junctionless transistor do away with the ultra-steep doping profile constraint and thus holds very promising prospects in semiconductor technology. The junctionless transistor operates on the principle of modulation of carriers by the gate electrode.
A junctionless transistor has constant high doping throughout the device. It can be considered as a gated resistor with high doping [1]. The first device of this kind was introduced by J. E. Lilienfeld [2] and was successfully fabricated and demonstrated by J-P. Colinge [1]. Myriads of different structures for junctionless transistor has been Sangeeta Singh sangeeta.singh@nitp.ac.in 1 Microelectronics & VLSI Design Lab, National Institute of Technology Patna, Patna, India reported [3][4][5][6][7][8]. Junctionless transistor faces difficulty in turning off the transistor owing to inefficient volume depletion which results in increased off state current. The device is turned off by gate semiconductor work function difference and requires a thin channel and high metal work function above 5.5eV [10] to successfully turn off the device.
The lateral band-to-band tunneling at the channel-drain interface is another source of enhanced off-state current. The valence band of the channel region overlaps with the conduction band of the drain area due to the close vicinity of the drain and the channel area and if the tunneling width is small enough, an n-type junctionless transistor experiences lateral band-to-band tunneling (BTBT), which results in holes in the channel region. In the off state, these accumulating holes form a parasitic bipolar transistor (BJT) with the adjacent source and drain region, and they are the major mechanism for increased leakage current. Furthermore, once the parasitic BJT is actuated, the current dominated by parasitic BJT action may result in gate control loss.
The effect of parasitic BJT action due to the lateral band to band tunneling has been earlier reported [9]. After that, the effect of gate induced drain leakage (GIDL) and leakage current mechanism in silicon nanowire transistors [12][13][14] and many other devices have been investigated taking lateral BTBT into account. Several topologies have been found to reduce the effect of lateral BTBT and improve offstate current [15][16][17][18][19][20][21][22]. These topologies either increase the tunneling width at the channel drain interface or reduce the electric field due to field redistribution to accomplish the desired enhancement. Architectures that prevent parasitic BJT triggering by increasing the source to channel barrier height and the effective length of the channel, lowering the current gain of bipolar BJTs and providing a path to the ground for holes formed in the channel area.
Although the performance of multigate junctionless transistor has been analyzed in the past [24][25][26][27], the effect of parasitic BJT due to lateral BTBT for FINJLFET has not been taken into account. However, from the aforementioned discussion, it is obvious that the lateral BTBT turns out to be a very important effect especially in the nanoscale junctionless transistors where the drain is in significant proximity of channel region and thus cannot be ignored in investigating the performance parameters.
In the present work, the effect of parasitic BJT action due to the lateral band-to-band tunneling is investigated for a FINJLFET. Additionally, to mitigate the parasitic BJT action a ground plane (GP) is added to the oxide layer and its effect in improving the performance is also investigated. The ground plane has been used in past to improve the performance of SOI-MOSFET. The ground plane leads to redistribution of electric field and prevents the penetration of electric field lines that originate from the drain into channel region and thus minimizes the short channel effects such as drain induced barrier lowering (DIBL) as the ground plane acts like a sink to SOI-MOSFET [27].
The rest of this article is organized into three sections: Section 2 deals with the device structural parameters description along with the simulation framework, Section 3 highlights the device dc performance estimation and it also depicts the in-depth device optimization and sensitivity analysis. The last Section 4 concludes the work.

Device Structures and Simulation
The schematic illustration of FIN shaped gate junctionless transistor with the ground plane in SiO 2 BOX (GP-FINJLFET) is shown in Fig. 1. Further, cross-sectional views of the proposed structure along gate direction and along channel direction are shown in Fig. 1(a) and (b), respectively. For the device simulations, Silvaco TCAD [23] was used and the device structure was created in Devedit 3D as shown in Fig. 1(c). It is a silicon on insulator junctionless field effect transistor (JLFET) with FIN-shaped gate structure and a ground plane at depth d gp inside the oxide. Because of the triple gate structure which results in better gate control, the requirement of a metal gate with a very high workfunction for efficient volume depletion can be relaxed and in this work, the gate workfunction of 4.9 eV is taken. The channel doping is taken to n-type and for the ground plane p-type doping is used. The detailed parameters for the device simulation have been tabulated in Table 1. The Fermi Dirac carrier statistics, Shockley-Reed-Hall, and Auger recombination were employed along with Lombardi mobility model. To account for band gap narrowing effect, slotboom was used. The standard band to band tunneling model was used to account for the lateral band to band tunneling. The tunneling model was calibrated as per the reported work [11].

Results and Discussion
As discussed that the band-to-band tunneling effect increases the tunneling current in the OFF-state and reduces the gate control and also hinders the scalability of junctionless transistor. Figure 2 compares the characteristics of proposed FINJLFET with and without taking into the effect of the lateral band to band tunneling. It can be observed from the figure that the lateral band to band tunneling causes a significant increase in drain current. This can be attributed to the parasitic BJT that is being triggered due to hole accumulation resulting from lateral band to band tunneling at the channel drain interface. This is further aggravated by high electric field that is present at the channel drain interface resulting in reduced tunneling width leading to a high probability of quantum tunneling. As the parasitic BJT is triggered, it results in the loss of gate control and therefore hinders the scalability of the device. One way to inhibit triggering is to increase the source to channel barrier height in the OFF-state of the device. This is precisely what our proposed structure is providing. The GP spans the length of the device, and it can be considered as the effect of increasing the base width of the parasitic BJT and hence the current due to the parasitic transistor is reduced as it is inversely proportional to the width of the base of parasitic BJT. The inclusion of GP helps leads to electric field redistribution. Short channel effects arises when the drain electric field competes for the channel potential. This is due to the encroachment of drain electric field inside the channel which is evident from the potential contour plot for the FINJLFET structure without GP in Fig. 4(b) where the drain electric field lines can be seen approaching the channel through the BOX. The inclusion of GP redistributes the electric field and it's effect can be seen from the potential contour plots in Fig. 4(a). It can be seen from the figure that the drain electric field lines coupling with the channel is minimized which is the reason for improved short channel effects characteristics of the FINJLFET with the ground plane [24].
In addition to the aforementioned improvement in the short channel, the GP also facilitates the depletion of the drain extension region which therefore reduces peak electric field at the channel drain interface. This significantly enhances the tunneling width which consequently surpasses the L-BTBT [27]. This leads to a better OFF-state current as compared to the structure without the GP. Moreover, the increased source to channel barrier height in OFF-state inhibits the triggering of parasitic BJT.
The validity of the aforementioned discussion is more apparent by looking at the hole concentration contour plots of FINJLFET with GP and without GP which is shown in Fig. 3. From the figure, it is apparent that the inclusion of GP results in reduced accumulated hole concentration and holes accumulate in a larger region as compared to the structure

Ground Plane Depth Variations
The effect of adding the GP can be more clearly interpreted by looking at the results due to variations in depth of GP from the channel. It can be seen from Fig. 5 that the optimum depth for the GP is 10 nm and decreasing the depth further results in an increase in OFF-state current. This is attributed to reduced electric field at the channel-drain interface and increased source to channel barrier height at the source-channel interface due to an increase in the encroachment of electric field lines towards the channel. Figure 6 shows that the aforementioned reduction of electric field as compared to the structure without GP. The field for different GP depths have also been plotted. In contrast to the FINJLFET without the GP where the peak electric field in OFF-state is concentrated near the channel drain interface, in GP-FINJLFET, the electric field is reduced at the channel drain interface because of redistribution. Because of reduced electric field, the band bending becomes gradual and the tunneling width is increased which mitigates lateral BTBT and reduced hole accumulation in the channel region. Figure 7 shows the effect of GP and depth variations on the band diagram. It can be observed that the GP reduces the source to channel barrier height and thus prevents the triggering of parasitic BJT. In order to account for the GP depth variations, we must look at both the source to channel barrier height and the electric field at the channel drain interface. A higher electric field is undesirable at the channel drain interface since it increases the band bending and the corresponding reduction in tunneling width which results in increased Lateral BTBT and increased OFF-state current. Similarly, at the source end, a high source to channel barrier height is desirable since it inhibits the triggering of parasitic BJT.

Effect of Channel Length Scaling
Since the GP addresses the issue of lateral-BTBT which is the major hindrance in the scaling of JLFET, the proposed structure is expected to perform significantly better when scaling of channel length is considered. However, the OFFcurrent is expected to increase because of the increasing proximity of drain to the channel as the channel length is reduced. This will result in degraded short channel effects and increased OFF-state current due to leakage. Scaling also reduces the base width of parasitic BJT which increases the current gain and thus increased OFF-state current once the parasitic BJT is triggered.
The effect of scaling has been considered in Fig. 8, where it can be seen that the device has good scalability even in the sub-10 nm regime. The device exhibits lower hole generation rates because of reduced BTBT even at scaled gate length. Figure 9 compares the drain characteristics of L g = 20 nm and L g = 5 nm with and without GP. It can be seen that the inclusion of GP leads to a significant improvement in the OFF-state characteristics of the device. Figure 10 shows the I on /I off ratio plots for FINJLFET with GP for different gate lengths. Also, the I on /I off ratio of FINJLFET without the GP has been compared. The addition of GP results in considerable improvement in I on /I off and the proposed structure has a good I on /I off ratio even in sub 10 nm gate lengths. A channel length of 20nm and 5nm GP-FINJLFET gives the I on /I off ratio Comparison of effect of GP for L g = 20nm and L g = 5nm of order ∼ 10 8 and ∼ 10 5 respectively compared to the I on /I off ratio of order ∼ 10 6 and ∼ 10 2 respectively for FINJLFET without GP. Thus, the proposed structure in this article provides a very lucrative alternative for scaled devices. However, for the scaling of gate length beyond 5 nm, an increase in drain current in OFF-state and loss of gate control is to be expected and more sophisticated simulations like ballistic or quantum-based models called for appropriately model the device behaviour due to quantum effects.
It has already been established that the GP results in reduced short channel effects due to the reduced effect of drain electric field in the channel region owing to the redistribution of electric field due to GP. In Fig. 11(a) the drain induced barrier lowering (DIBL) has been extracted for our proposed structure. DIBL is calculated as the difference in V th at V DS =50 mV and at V DS =1.0 V. The constant current method of threshold voltage extraction has been used. The DIBL is computed at the constant reference drain current of 10 −7 A/μm which is widely used as a reference current for threshold voltage extraction [28]. Then the DIBL is calculated according to the equation: The threshold voltage(V t ) for scaled gate length has also been shown in the figure. Moreover, in Fig. 11(b) the DIBL and threshold voltage for FINJLFET without GP have been plotted for comparison. It can be observed that the structure with GP shows better DIBL characteristics than the one without GP. Figure 12 demonstrates the effect of variation of doping concentration on the drain characteristics. It can be observed that the I D −V GS characteristics are very sensitive to doping variations and a high doping concentration of the order of ∼ 10 20 /cm 3 is required to get the optimum results. Reducing the doping concentration of GP leads to a drastic increase in OFF-state current. A high doping concentration is required so that the GP can redirect the drain electric field encroachment away from the channel and facilitate the depletion of the channel region underneath the gate to achieve volume depletion and the subsequent reduction in leakage current. Figure 13 shows the effect of the width of active layer variation on the drain characteristics of the device. It can be observed that decreasing the width of the channel region significantly reduces the OFF-state current which is due to the reduction in the active region volume that needs to be depleted by the gate electrodes resulting in increased volume depletion. Moreover, a better electrostatic gate control is apparent from the constancy of the I D − V GS curve in the OFF-state as we scale down the width of the channel region. This improvement in gate control helps suppress the effect of drain electric field on the channel region alleviating the short channel effects such as DIBL. The reduction of short channel effects leads to decreased source to channel barrier height and thus inhibits triggering of parasitic BJT. The increased source to channel barrier height along with reduced drain electric field influence on the channel region accounts for the observed improvement in OFF-state current. However, decreasing the silicon FIN dimensions beyond 5 nm results in quantum confinement effects which must be accounted for while investigating the characteristics of the device. It requires the use semiclassical methods with quantum corrections or quantum simulations like the Schrödinger-Poisson equation to account for the effects of subband formation and change in density of states due to quantum confinement. In the present work, this has not been taken into account however, from the results of related work, quantum confinement improves the OFF-state characteristics of the JLFET due to increase in band gap and thus reduced leakage current.

Channel Width Variation
The ON-state current is slightly reduced as we reduce the width of the channel region owing to a reduction in the number of charge carriers available for current transport. However, in order to understand the ON-state performance, we also have to account for the effect of reduction of lateral dimensions of the FIN on the mobility of carriers. The three different kinds of mobilities to be considered are due to surface roughness, phonons, and the coulomb scattering. The ON-State current is a result of interplay of these three different kinds of mobilities. The net mobility is given by Matthiessen's rule: In FINJLFET, due to symmetrical structure of opposite facing gates, the electric field is low to moderate at the center of the channel. Moreover, since the transport of carriers happens in the bulk of the device rather than at the surface, the surface roughness mobility increases as the lateral dimensions of the field is reduced. This is similar to the reduction of surface roughness mobility in the case of double gate MOSFET or FINFET after the onset of volume inversion when the thickness is reduced so that the inversion layers interact and charge carriers move from the surface to the bulk of the device. Coulomb mobility arises due to scattering of charge carriers from the ionized impurities and the charges trapped at the Si − SiO 2 interface. The coulomb scattering is the reason of low ONstate current in JLFET compared to MOSFET because a moderate doping is required in order to relax the need of ultrathin channel and facilitate volume depletion. Thus, in the flat band mode of operation, where the electric field is low at the center of the channel, coulomb mobility is the dominant mobility and limits the ON state current of JLFET. However, reduction of lateral dimensions of the FIN results in better screening of charge centers by carriers in the channel in weak accumulation region of operation thus increasing the coulomb mobility. The phonon limited mobility is the major factor that results in the reduced ONstate current of the JLFET as the thickness is reduced. As the lateral dimension of the scaled down, the form factor which multiplies the phonon scattering rates [29] increases due to geometrical confinement. This results in increased phonon scattering and hence decreased ON-state current owing to the increased scattering rates. The rate of increase of this form factor increases with decreasing lateral dimensions and hence it is the limiting mobility as the thickness is reduced. Again, if the lateral dimensions are further reduced beyond 5 nm, quantum confinement effects and must be accounted which changes the density of states due to formation of subbands and also breaks the sixfold degeneracy of conduction band valleys in silicon and results in the formation of primed and non primed valleys leading to inter-subband and intra-subband scattering along with intervalley scattering. These confinement effects have not been accounted for in our present work.

Temperature Variations
The effect of temperature on the drain current characteristics of the device is shown in Fig. 14 where the I D − V GS characteristics is shown for four different temperatures namely 200K, 300K, 363K, and 500K. When the temperature is increased, the thermal energy of the carriers increases and they become more efficient in overcoming the source to channel barrier height which accounts for the increased drain current in the OFF-state characteristics as the temperature is increased.
In the ON state of the device, the current depends on the interplay of three different mobilities. While the phonon scattering increases as the temperature is increases, the ion impurity scattering shows the reverse trend and increases with decrease in temperature as it becomes more and more effective in deflecting the charge carriers when the temperature is reduced due to reduced speed of charge carriers. This is dominant in highly doped structures like in JLFET. Since the impurity scattering in heavily doped channel varies as T 3 2 while the phonon scattering varies as T −3 2 , the two scattering mechanism compensate each other and the observed mobility degradation is less in JLFET. This is apparent from the almost similar drain current in the ONstate of the proposed device as the lateral dimensions are reduced.

Conclusion
A ground plane based FINJLFET is proposed for sub-10 nm for SOI-JLFET. With the use of calibrated simulations, it has been demonstrated that the addition of GP results in a drastic reduction of OFF-state current and increased I on /I off ratio of 10 8 and 10 5 for gate lengths of 20nm and 8nm. Additionally, improved DIBL and threshold voltage roll-off has been observed for GP-FINJLFET which is attributed to the depletion of source drain extension region and reduced parasitic BJT action owing to the GP. This reduction in parasitic BJT action is attributed to suppressed L-BTBT at the drain channel interface. Thus, the proposed GP-FINJLFET shows better performance and is a very promising structure for sub-10 nm scaling.