Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

– In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.


I. INTRODUCTION
As per today's state-of-the-art technologies, device scaling plays a crucial role to enhance device packing density on a single chip. The scaling of device dimensions increase the device performance to faster speed, less area and low cost, but it also increases short channel effects (SCEs) for the devices. In nanoscale dimension, source comes closer to the drain which reduces gate curb on the channel region and upsurges the influences of drain voltage (VDS) which introduces drain-induced barrier lowering (DIBL) [1], [2]. Therefore, it is essential to improve effective gate control on the channel region to reduce DIBL. To enhance the gate control, multi-gate device structure has been introduced [3][4][5]. Among all the device structures, gate all around [6], [7] is a most promising and widely used device structure due to its better gate controllability, better SCEs immunity and improved transport properties [8] [9].
Moreover, to increase gate control and decrease gate oxide tunneling, SiO2 has been replaced by the high-κ dielectric material [10], [11] but devices still face the problem of DIBL at nanoscale dimensions. To overcome the issue, alternatives were carried out. Gate material engineering (GME) is one of them proposed by Chiang et al. [12] and Kumar et al. [13]. In GME technique, gate metal work function is tuned so that the metal with high work function accelerates charge carriers near the source region while the low work function metal is chosen at drain region [14], [15]. These expedited charge carriers collected at drain region provide higher ION. Moreover, a stepped size potential along the channel region has been provided by GME, which is due to the modulation in metal gate work function. This stepped potential provides a better immunity against DIBL.
As far as gate oxide is concerned, hetero-dielectric oxide materials are used at the source and drain region [16], [17]. This technique is called hetero-dielectric oxide. The accelerated charge carriers collected at the drain region. Hence the higher permittivity material has been used near the drain region to reduce gate oxide tunneling.
As the channel length diminishes till the nanoscale regime, the gate drops the control on the channel, which modulate the threshold voltage [18]. But in multi-gate devices, the whole channel region has been accumulated and inverted by gate terminal [19]. Hence, for GAAFET devices, a threshold voltage is calculated by gate voltage at which the minimum channel carriers sheet density Qinv met with the threshold value QTH [20], [21]. The channel mobile charge carrier density has been used in this paper to model channel potential. Hence the Poisson equation became nonlinear for this charge density. Therefore, to solve such nonlinear Poisson equation, superposition principle [22] has been used.
Further, in this research paper, DM-NO GAAFET device, which is the combination of GME and heterodielectric, has been modelled for channel surface potential distribution, threshold voltage, and DIBL. This DM-NO GAAFET device structure has already being proposed by Kumar et al. in [23] to reduce DIBL. All analytical results, meet the good agreement with simulated data. The attained results are then further compared along with DM-VO GAAFET to verify the better performance of DM-NO GAAFET.
The organization of this work as follows: The device structure and simulation set-up along with the considered models are included in section-2. In section-3, semi analytical models for threshold voltage, surface potential, and DIBL are given. The validation of the models and comparative analysis for both the devices are covered in section-4. Section-5 present the summary and conclusion of the work in the last.

SIMULATION
The device structure of DM-VO GAAFET and DM-NO GAAFET are delineated in Fig. 1. It can be infer from Fig. 1 that, in DM-NO GAAFET device, silicon nitride (Si3N4) has been adopted as the gate oxide near the drain region to reduce charge carrier tunneling while, in DM-VO GAAFET device, a vacuum has been used as gate oxide to reduce hot carrier effects [24]. Both the devices have been divided into two regions in which region 1 has been considered near the source region and region 2 has been considered near the drain region as per Fig. 1. The gate material engineering and hetero-dielectric techniques are used in both the devices.
In GME, high work function metal (Фm1) is adopted in region 1 with Фm1 = 4.9 eV and the low work function metal (Фm2) is adopted in region 2 with Фm2 = 4.62 eV. To get the desired metal work function, Molybdenum has been used as gate electrode material in which work function can be tuned [25]. In DM-NO GAAFET, silicon nitride has been used just above the silicon structure in region 2 whereas SiO2 has been incorporated as the gate oxide for region 1 in both the devices.
The doping concentration with 1 × 10 20 cm -3 has been used in source/drain region with donor impurity while the lower doping profile of 1 × 10 16 cm -3 is used in channel region with the acceptor impurity. Similar doping concentration are reported by Sahay S. et al. [26]. The length of region 1 and region 2 have been defined by L1 and L2 respectively. The total channel length has been shown by L. All the device dimensions for DM-VO GAAFET and DM-NO GAAFET have been depicted in Table-I  Visual TCAD Cogenda tool is used to carry out all the 3-D simulation [27]. For simulation, we have considered local band to band tunneling (BTBT), Shockley-Read-Hall (SRH), Philips unified and Lombardi mobility models. To include the degradation of mobility by high electric field and doping, Philips unified, and Lombardi mobility model are included in the present simulations. The effects of charge carriers have been examined by local BTBT model. The effect of charge carrier recombination and Boltzman statistics are calculated using SRH and Drift-diffusion model, respectively. To analyse the impact of highly doped source and drain regions, the Fermi diac statistics model has been incorporated. Since the quantum confinement effect is not the part of our current work, hence the dimensions are not less than 7nm.

III. SEMI-ANALYTICAL MODELING
As per the device cross-section shown in Fig. 1, the whole gate and oxide length have been divided into two different regions. Since the whole channel region is uniformly doped by acceptor impurity, hence the Poisson equation for the potential Øi (r,z) can be shown by [22]   (1) Where i = 1, 2 shows the two different regions, Na is channel doping concentration and ƐSi is permittivity of silicon channel.
To solve such non-linear Poisson equation associated with the potential distribution, superposition principle is used [22]. In this superposition principle, the solution of 2D Laplace equation is added with the solution of 1D Poisson equation Where Vi (r) and Ui (r.z) are the solutions of 1D Poisson equation and 2D Laplace equation respectively. The boundary condition has given in [22] have been applied to get the solution of Eq. (2). Hance the solution of 1D Poisson and the 2D Laplace equation for different regions are given as Where λn is the eigen value and given as . 1 ( 2 ) Where An, Bn, Cn and Dn are the Bessel's coefficient. In Eq.
(4), Ɛoxj is the permittivity of oxide material used in the region 2. In this research work, DM-VO GAAFET is compared with DM-NO GAAFET. If Ɛox1 is the permittivity of vacuum, which is equal to 1.Ɛo and used in DM-VO GAAFET while the Ɛox2 is the permittivity of silicon nitride, which is equal to 7.Ɛo and used in DM-NO GAAFET. The device structure DM-NO GAAFET shows the higher potential value as per the Eq. (4) and it also verified by Fig.  3. As the Ɛox2 is higher than the Ɛox1, it reduces the fifth term of Eq. (4) and increases over all potential for DM-NO GAAFET.
By the addition of the solution of 1D Poisson and 2D Laplace equations, the solution of Eq. (1) will be ∅ 1 ( , ) = .
The virtual cathode point (VCP) is defined as the minimum potential point at which or after it, the mobile charge carriers have been controlled by the gate electric field [28] and can be calculated as Substituting the value of Ø1 from Eq. (9) to Eq. (10). The VCP will be 1, Now putting z = z1, min and r = tSi/2 in Eq. (9) to calculate minimum inversion charge carrier density Similarly the minimum surface potential in region 2 will be As per the [22], the threshold voltage is considered which is equal to VGS when the minimum surface potential has been considered two times of bulk potential. As per given below Now putting the values from Eq. (15) to Eq. (12) and solve for VGS. To reduce the complexity of computation, λ1(L1+L2) >> 1, has been considered. The threshold voltage will be As per the Eq. (17), threshold voltage is directly affected by ω1, ω2, ω3, ω4, α and δ. According to the dependency of Cox' on α which has been given in Eq. (18) Where Y0 and Z0 are the values of Y and Z at VDS = 0.05V. As per the above sub section, DM-NO GAAFET provides higher value of threshold voltage compare to DM-VO GAAFET hence DM-NO GAAFET gives less DIBL and it has also been verified by Fig. 10 IV. RESULTS AND DISCUSSION The surface potential distribution modelling is adapted for different channel length, channel radius, VGS, and VDS. Fig. 3 (a) delineated the surface potential distribution for DM-VO GAAFET and DM-NO GAAFET devices along with the variation in channel length. The VGS = VTH and VDS = 0.05V are used for simulations. The surface potential is calculated 2 nm below the channel-oxide interface in the channel region. In Fig. 3 (a), the surface potential is compared for different channel lengths in region 1 and region 2 in such a way that the length for gate and oxide in region 1 are kept at 10nm and 20nm for L1:L2 = 1:2 and L1:L2 = 2:1 respectively while the length for gate and oxide in region 2 are kept at 20nm and 10nm for L1:L2 = 1:2 and L1:L2 = 2:1 respectively. From the Fig. 3 (a), it can be observed that the potential exhibits a step variation at the interface of two regions for both the device structures, which is due to the work function variation at these two region interface.
It can be observed from Fig. 3 (a) that this step sized variation is lower for DM-VO GAAFET and higher for DM-NO GAAFET which is due to the different electric field near the drain region at channel-oxide interface. In DM-NO GAAFET, silicon nitride material is adopted near the drain region to reduce tunneling. The accelerated charge carriers are poised at drain region, but silicon nitride reduces the tunneling of these charge carriers to reduce the electric field. Further, a vacuum region is used in DM-VO GAAFET and thus it has a higher electric field. Moreover, higher stepped size potential distribution provides higher immunity from SCEs [29]. Hence DM-NO GAAFET is more immune for DIBL. As channel diameter reduces, it boosts the gate control on the channel region, hence the gate can now control the channel region charge carriers effectively. Fig. 3 (b) exhibits the surface potential variation for different channel length and channel diameter. The voltage levels are kept fixed at VGS = VTH and VDS = 0.05V. In Fig. 3 (b), DM-VO GAAFET and DM-NO GAAFET have been compared for channel diameter of 10nm, 15nm, and 20nm. Analytical results have also been calculated for both the devices at the same channel diameter and found close agreement with simulated results. It can further be observed from Fig. 3 (b) that the potential is distributed in stepped size and this stepped size potential is high for DM-NO GAAFET which is caused by the electric field variation at channel-oxide interface near drain side. From Fig. 3 (b), it can be observed that the potential is high for 10nm channel diameter while the potential is low for 20nm channel diameter which is caused by the gate control on the channel region for both the devices. Although for 10nm channel diameter, a gate provides excellent control on the channel region compared to 20nm channel diameter for both the devices because of the higher vertical electric field between the gate and channel region [30]. Moreover, at 10nm channel diameter, a gate provides higher immunity from the SCEs due to higher stepped size potential in channel region. Fig. 4 (a) demonstrates the surface potential distribution along with the channel length at different VGS. VDS is kept fixed at 0.05V whereas channel length and channel diameter are kept fixed at 30nm and 20nm respectively. In Fig. 4 (a), it can be observed that the VGS has been kept fixed at 0.2V, 0.4V, and 1V. Since at VGS = 0.2V, both the devices are in the cut-off region; hence, it provides minimum potential in the channel region. As the VGS increases from 0.2V, devices move to the depletion region and starts conduction. At VGS = 0.4V, devices remain in the depletion region and in the depletion region, the channel begins to form. Hence in this region, surface potential became higher compare to the cut-off region.
At VGS = 1V, devices remain in saturation region which provides higher ION current for both the devices. The potential distribution is much higher for DM-NO GAAFET at VGS = 0.4V as compare to the potential distribution of DM-VO GAAFET at VGS = 1V. Since in DM-NO GAAFET, silicon nitride has been used as the gate oxide which minimizes the tunneling of charge carriers; hence, it provides the higher surface potential for DM-NO GAAFET at VGS = 0.4V in region 2. Moreover, from Fig. 4 (a), the stepped sized surface potential, and the surface potential in region 2 are higher at every VGS voltage levels. Hence it provides higher immunity to SCEs and higher ION current.  Fig. 4 (b) shows the deviation in surface potential when the channel length increases from 15nm to 45nm at different VDS. VGS is kept fixed at the threshold voltage level to keep the device in ON-state. In Fig. 4 (b), the surface potential of DM-VO GAAFET and DM-NO GAAFET are compared at VDS = 0.05V, 0.4V, and 1V. The surface potential is high for DM-VO GAAFET as the VDS is increasing from 0.05V to 1V and the vacuum gate oxide is adopted in DM-VO GAAFET. Due to the vacuum gate oxide, an additional electric field also present due to the charge tunneling which causes increment of DIBL in DM-VO GAAFET. However, due to this increased DIBL, VDS has a stronger influence on channel region's charge carriers, and due to this influence, DM-VO GAAFET provides higher surface potential in channel region 2. The surface potential is obtained higher at VDS = 0.05V as the lower VDS is used in DM-NO GAAFET (see in Fig. 4 (b)).
Electric field distribution plays a critical role in device operation and charge carriers movement. Fig. 5 (a) shows the electric field distribution along with the channel length at different channel regions. The oxide length is kept fixed at 10nm for region 1 and 20nm for region 2 at L1:L2 = 1:2 while it kept fixed at 20nm for region 1 and 10nm for region 2 at L1:L2 = 2:1. From Fig. 5 (a), it can be observed that in device structure L1:L2 = 1:2, a small electric field spike is observed at the interface of these two regions. Since the gate length is 10nm in region 1 and the interface of two regions, comes closer to the source region; hence, it gives a small spike at the interface. The electric field increases for DM-VO GAAFET, and it started decreasing for DM-NO GAAFET in the case of L1:L2 = 1:2 after electric field spike. The electric field has been increased for DM-VO GAAFET, which is due to the additional electric field that occurs by the tunneling of charge carriers whereas the electric field has decreased for DM-NO GAAFET which is due to the reduction of charge tunneling. The electric field provided by the silicon nitride layer plays important role to reduce overall electric field by the factor of Ɛ/Ɛ0.
The lower value of electric field in DM-NO GAAFET provides lower electric field in drain region, and hence, it gives less DIBL for DM-NO GAAFET. From Fig.  5 (a), it can be seen that the two region interface is close to the drain side for L1:L2 = 2:1. Hence it gives a parabolic distribution of electric field till the region interface, and then provides a big spike at the interface. After the spike, the electric field started decreasing for DM-NO GAAFET and gives small electric field at the channel-drain interface and hence reduces DIBL.  Fig. 5 (b) shows the variation in the electric field along with the channel length for different channel diameters. The electric field is higher at 10nm diameter than the electric field at 15nm diameter for both the devices. Since the small diameter channel influenced by the higher vertical electric field, which is provided by the gate terminal. Hence this additional electric field gives better control to the charge carriers available in the channel region. Fig. 5 (c) shows the electric field variation along with channel length for different VGS. VDS is kept fixed at 0.05V. The electric field is higher for both the devices at VGS = 0.2V. Since devices remained in cut-off mode at VGS = 0.2V which is due to the VGS is smaller than the VTH. In the cutoff mode, there would not be any conducting channel in source and drain, so a small electric field which is present between Source and Drain, is because of the unwanted charge carriers which move from source region to drain region due to lack of source-channel barrier height [31]. The electric field in cut-off mode is low for DM-NO GAAFET device because this device provides small DIBL.
Further, devices remain in the depletion mode for VGS = 0.4V, which is due to the VGS higher than the VTH. Although, the charge carriers have been depleted by VGS increment in depletion mode. These depleted charge carriers are than move towards the centre of the channel. Moreover, as the charge carriers depleted, fixed acceptor atoms are left behind near the channel-oxide interface. As the VGS increases, it also increases the vertical electric field. However, the fixed acceptor ions also offers limited electric field at channel-oxide interface. Therefore, these two electric fields provide higher electric field for both the devices as per Fig. 5 (c). The electric field spikes present at the metal gate interface due to the variation in an electric field.
The threshold voltage is directly affected by the DIBL. As far as improvement of VDS is concerned, it diminishes the threshold voltage due to the DIBL effect and source-channel barrier height, which further increases subthreshold leakage current [31]. The threshold voltage deviation has been shown in Fig. 6 (a), when the channel length increases from 20nm to 100nm for channel diameter of 20nm. From Fig. 6 (a), it can be observed that when the channel length increases from 20nm to 100 nm, it increases threshold voltage till 40nm for both the devices and after 40nm, threshold voltage became almost constant. At 20nm channel length, threshold voltage is less due to the SCEs, but at 40nm, SCEs have been minimized. Moreover, after 40nm, SCEs became insignificant for channel length increment and provided almost constant threshold voltage for both the devices. The value of threshold voltage is high for DM-NO GAAFET, due to the higher immunity against SCEs. The calculated analytical results are more close to the simulated results, which validate the threshold voltage model. DIBL is an SCE which occurs due to the influence of VDS on the channel region. DIBL is calculated by the threshold voltage difference for lower and higher values of VDS. The formula used for calculation of DIBL is expressed in Eq. (28). Fig. 6 (b) exhibits the variation in DIBL along with the channel length for DM-VO GAAFET and DM-NO GAAFET. The DIBL reduces exponentially till 50nm and after 50nm it became almost constant. Since at 20 nm channel length, the SCEs are more prominent for both the devices and hence, it shows a higher value of DIBL. When the channel length increases from 20nm to 50nm, DIBL has reduced due to the increased channel length. It also increases gate control over the channel region [18]. After 50nm, source and drain became as far enough so that the horizontal electric field component became insignificant, which in general controlled by VDS. Hence it reduces DIBL in both the devices. As per Fig. 6 (b), DIBL offered by DM-VO GAAFET is high whereas low for DM-NO GAAFET, which is due to the minimized charge carrier tunneling. This reduced charge carrier tunneling helps to reduce addition electric field near the drain side and hence reduces DIBL in DM-NO GAAFET. This reduced DIBL helps to lower down leakage current.

V. CONCLUSION
The semi-analytical modeling and the effect of device engineering are carried out for surface potential, threshold voltage, and DIBL on DM-NO GAAFET and DM-VO GAAFET. The analytical and simulation result shows the better device performance for DM-NO GAAFET to suppress DIBL, and enhanced threshold voltage. DM-NO GAAFET provides more immunity against SCEs due to the more stipe stepped surface potential distribution. Moreover, a limited electric field is observed in DM-NO GAAFET near channel-drain interface due to which DIBL is reduced for DM-NO GAAFET. Since the threshold voltage is higher and DIBL is lower, which provides excellent charge control by gate terminal on the channel region, as per channel length decreases for DM-NO GAAFET.