A novel architecture for 10-bit 40MSPS low power Pipelined ADC using simultaneous capacitor and op-amp sharing technique

This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp-p,diff input signal while consuming only 7.3mW power from 1.8V supply.


Introduction
With the increasing demand for the Application Specific Integrated Circuits (ASICs) there is a wide development of mixed-signal design, compatible with System-on-chip (SoC). Data converters have become an important block in SoC design for data communication and image processing applications [1].Among the different ADC design pipelined ADCs are suitable for high speed,medium resolution and low power applications [2--4].Since the accuracy decreases in the later stages of pipeline ADC, proper scaling of capacitors are required in pipelined ADC [5][6][7] Sharing an op-amp between two consecutive stages can further reduce power consumption [8][9][10]. Furthermore switched-op-amp techniques [11][12] was proposed to reduce the power consumption of pipelined ADC. The maximum power is consumed in the first stage of the pipelined ADC [12].
To reduce the power consumption of ADC capacitor sharing technique was proposed [13][14][15][16]. To further reduce the power consumption, the front-end sample and hold circuit (S/H) is eliminated [17][18].SHA introduces additional noise signal which is integrated to the analog signal and results in large power dissipation and occupies more die area. Also the S/H circuit is removed by integrating the SHA in first stage of pipeline ADC to reduce the power [19]. Hence it is essential for certain applications to simplify the pipelined ADC 2 by eliminating the supplementary blocks such as SHA circuit [20]. The aperture error is reduced by matching the delays that occur between the sampling networks of the subblocks including first MDAC and comparators [21]. In this paper, a novel SHA-less pipelined ADC using a combination of simultaneous capacitor and amplifier sharing with a sampling frequency of 40 MSPS is presented. To achieve low-power and high performance, the P-gain and N-gain boosted variable gm op-amp and dynamic comparators have been designed.

2
Architecture of SHA-less Pipelined ADC The proposed SHA-less Pipelined ADC architecture is shown in Fig.1. It mainly contains a SHA-less front-end followed by second stages in which two op-amps are shared in neighboring stages followed by 3-bit Flash ADC. In order to limit the overall conversion rate the bandwidth of the Switched Capacitor (SC) circuit is to be maximized. The closedloop gain of the amplifier is 2 so that a large feedback factor and a low load capacitance is achieved. Since the capacitance load is very less and the feedback factor is large the bandwidth of the amplifier which is used in the intermediate stages can be increased. Fig. 2 shows the first and second stages of the ADC.

Operational amplifier
An op-amp is the main important sub-circuit of analog systems [22][23][24][25]. The common mode noise and even harmonics are reduced in the fully differential amplifier which employs a two-stage topology when compared with the single ended output op-amp. Also the linearity is increased in the fully differential amplifier. Fig. 3 shows the designed two-stage fully differential OTA which uses the gain boosted auxiliary amplifier. Here the fully differential structures are used in P gain boost and N gain boost amplifiers. With 1.8 V supply voltage the gain boosted amplifier is simulated initially to verify the desired specifications which was described by [26][27][28].

Design of the op-amp:
The op-amp is the most essential block in ADC [29][30]. The output impedance Rout is increased by the added gain stage AOTA as given in the following equation: 4 (1) Further more ,the DC gain of the op-amp is improved in several orders of magnitude: (2) (3)  To improve the voltage gain of the folded cascode amplifier the output impedance of the circuit need to be increased as shown in Fig.4. The design procedure starts with the design of fully differential op-amp and the second step is to introduce the gain boosting amplifier to obtain the desired gain without affecting the bandwidth of the op-amp. To start with, the sizing of the main differential input pair of the transistors MN0, MN1 is selected using the desired phase margin and the gain bandwidth specifications. This op-amp design includes the design of differential inputs, differential outputs, folded cascode bias circuits with common mode feedback (CMFB) and gain boosting amplifiers. [31][32][33] The feedback factor β is given by: (4) The unity gain frequency is given by: The settling time τ can be found by: (6) In Fig.5 the overdrive voltage of M10 is assigned high than that of input transistors M8 and M9 to boost the gain. The gain of this op-amp is mostly based upon the transistors M3, M5 and M8. The transistors M0 and M1 should be matched and kept wide enough to act as a resistor i.e. the overdrive voltage assigned is more compared to all.

Fig. 5 P gain boost amplifier
The bias circuit is used in this op-amp is current biasing circuit which is current source with one Silicon based NMOS for n-bias and current source with one Silicon based PMOS for pbias. The current in the current source is scaled to give the bias voltage needed to make the circuit stable. Fig. 6 shows the N gain boost amplifier.

Analysis of the op-amp
For the residue signal generated by the MDAC the op-amp loop-gain has to be at least 2 9 (54 dB) . In the design of the op-amp the main stage is the folded cascode op-amp which produces high gain.The Vcm node is used to control the common mode bias voltage of the op-amp. Table 1 shows the performance summary of P Gain and N Gain Boost Amplifiers.  6 Simulation results show that the total DC gain of the op-amp is 86dB. Phase Margin value of the variable gm op-amp is greater than 80 0 . Table 2 shows the performance summary of variable gm op-amp.

Simultaneous Capacitor sharing and Op-amp Sharing MDAC
The capacitor C1f is composed into two parts: C2f and C2s. During the phase Φ1,the analog input signal is sampled on the two capacitors C1f and C1s.The residue signal is generated from each stage during the phase Φ2 and the residue signal is not provided to the sampling capacitors in the second stage of the pipelined ADC.The residue signal is detained on C1f which is the feedback capacitor.Using the stored value on the capacitor C1f , residue signal is produced. This stored value is provided to the sampling capacitors of the third stage C3f and C3s during the next phase Φ1.When the second stage is generating its residue signal, the next input signal need to be sampled are used [34][35][36]. The feedback capacitors named as C1fe and C1fo are used.The matching network is used in the initial stage of ADC. In the proposed pipelined ADC the simultaneous capacitor sharing and op-amp sharing technique is used . Fig.7 shows the simultaneous capacitor and op-amp sharing technique.

Specifications
Variable

Sampling Network for Stage1
The use of S/H circuit is avoided with the MDAC and the sub-ADC performing the sampling procedure [37]. In this work, the aperture error is minimized by matching the sampling network through cautious design of the aspect ratio (W/L) of the transistor. The gate source voltage (Vgs) is same for the sampling capacitance Cs and Ccom1-Ccom4 in the sampling network.This is because the above mentioned sampling capacitance is connected to the same common mode voltage. Fig.8 shows the proposed sampling network for the initial stage. Fig.9 shows the timing diagram for the sampling network.

Results and Discussion
The SHA-less Pipelined ADC is simulated in a 180nm Silicon based CMOS process. Various sub circuits like dynamic comparator, op-amp, MDAC, Sub ADC and sub DAC was integrated for pipelined ADC [38][39]. Fig.10 shows the 1024 points FFT spectrum with the input frequency of 2 MHz. Fig.10 Obtained FFT spectrum of pipelined ADC Fig. 11 shows the layout of 10-bit SHA less pipelined ADC.The delay and the power consumption obtained after post layout simulation is 15.1ns and 15mW. C. Fig. 11 The layout of the 10-bit SHA less Pipelined ADC Table 3 shows the Performance summary of 10-bit SHA less pipelined ADC. The10-bit SHA less pipelined ADC was designed in a 180nm Silicon based CMOS process and achieves 56.12 dB SNDR,56 dB SNR,70 dB SFDR, from a 1.8V supply voltage.   Table 4 shows the comparison of the 10-bit SHA-less pipelined ADC with some reported pipelined ADCs. Comparing the present work with the reported work at [27] 39.1% of power reduction has been achieved. When compared to the other pipelined ADCs reported in previous reported works this 10-bit SHA less Pipelined ADC has less power consumption.

CONCLUSION
A 40MSPS pipelined ADC which is suitable for low power has been described. By removing the front-end SHA, considerable power saving is obtained. The variable gm operational transconductance amplifier used in the design has been designed with a gain of 45dB .Clocked dynamic comparator is also designed and the same is used to build sub-ADC's which generates the LSB and MSB of the each single stage.Simulation results of the pipelined ADC in a 180nm Silicon based CMOS process shows an SFDR of 70 dB, SNDR of 56.12 dB, ENOB of 9.02 bits and FOM of 0.35pJ/step while consuming only 7.3mW for a 2 MHz input signal.From the results it was shown that the designed ADC maintains a good dynamic performance and low power consumption suitable for SOC Digital TV Application.

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