A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature

The article reports the extraction of DC characteristics and small signal parameters of Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. The reliability of the device is examined by analysing: (1) the impact of the presence of interface trap charges, (2) the impact of temperature variation (200- 400 K). In the analysis it has been observed that in case of absence of interface trap charges the increase in frequency reduces the value of parasitic capacitances. In addition, the presence of interface trap charges lessens the value of parasitic capacitances up to a certain gate to source voltage after that it shows a reverse effect. Further, it has been perceived that the effect of change in temperature is more on device ambipolar current when interface trap charges are present, whereas the reverse is true in the case of OFF state current and different parasitic capacitances.


Introduction
Over the past decades, MOSFET played a very crucial role, however as devices scale down short channel effects of MOSFET dominated the platform. Hence, new alternative structures are on demand which can mitigate the drawbacks associated with MOSFET. One of the promising alternatives in place of MOSFET is the tunnel field effect transistor (TFET). It is reported that TFET has the ability to exceed subthreshold swing (SS) from the physical limit of 60mV/decade and have an extremely low leakage current because of its unique current conduction mechanism. The mechanism is called band to band tunneling, where electrons move from source valance band to the channel conduction band [1][2][3][4]. These advantages of TFET attracted the attention of a lot of researchers as a reliable contender for low power applications.
For low power applications maintaining the minimum SS is not sufficient, in this case, an average SS should be taken into consideration for V dd reduction [5,6]. Unfortunately, in TFET the value of SS increases for an increase in gate to source voltage, thus can not provide lower average SS, which can be generally explained by (V T -V OFF )/log(I T /I OFF ) [5]. Further, limited ON current of TFET is another factor of concern. To overcome these problems, many new TFET structures have been proposed some are Double gate TFET [7], III-V-semiconductor-based TFET [8], SOI TFET [9], Carbonbased TFET [10], SG-ESTFET [11], etc. However, in the process of device optimization, it is a challenge to preserve all the parameters in a single device. In this case, [12] has proposed a non-uniform silicon TFET with a dual-material source to maintain lower average SS, the non-uniform body which increases the ON current and the compressed body of the drain side maintains a low OFF and ambipolar current too. The performance of the structure has been analysed in terms of various structural and material parameters in literature.
Counting the switching characteristics of device a detailed analysis of analog/RF parameters of the device needs to be investigated to know the perspective in the analog and digital applications. In literature, different parasitic capacitances are studied and it has been analyzed that the gate to drain capacitance (C gd ) is much higher than gate to source capacitance (C gs ), which limits the performance of TFET [13,14].
However when reliability of a device is concerned the above mentioned small signal parameters along with DC characteristics need to undergo various situation where consistency of the device can be examined. Further, the temperature of the device plays a dominant role in device performance, as with the advancement in technology node number of transistors onchip increases, which leads to large heat dissipation and change in the operating temperature of the transistors [15,16]. It is observed that, the current conduction mechanism of TFET depends on band gap energy which is a function of temperature [17,18]. In addition, it is also articled that the effect of temperature on device performance is more when interface trap charges are present [18,19]. Hence a detailed understanding of device parasitic capacitances and DC performance parameters need to be analyzed in the presence of trap charges as well as in varied temperature conditions. This work investigates the analog/RF analysis of the device in the presence of interface trap charges at various frequencies. Further, a temperature analysis of the structure has been executed for both DC and AC performance parameters. The paper is structured in four sections including introduction, the depiction of the device structure, and simulation methodology provided in Sec. 2. Section 3 explains the analysis of results and finally, Sec. 4 concludes the work in brief. Figure 1 shows the schematic structure of Non-uniform Si TFET with dual material source (NUTFET-DMS) [12] having p + source and n + drain regions. In TFET when V gs increases SS and Avg. SS increases. To reduce the average SS source is made of two materials such as Silicon (upper part) and germanium (lower part). The incorporation of the Ge in the source materials reduces the SS of the TFET device at higher gate to source voltage (V gs ) thus reducing Avg. SS [16,20]. In addition the asymmetric arrangement of the body is to provide a high ON current as well as low OFF and ambipolar current. The higher body thickness at the source side leads to decreased effective mass results in higher mobility, thus increasing tunneling current. Similarly the lower body thickness at the drain side reduces mobility which further decreases OFF and ambipolar current [16,21].

Device Structure and Simulation Methodology
The entire device length is 60 nm. The thickness of the source is 15nm and the drain is 7nm each. The upper gate and lower gate are made up of aluminium and PolySi, respectively. The dielectric material for the upper, lower gates is HfO 2 in the source side and SiO 2 in the drain side, respectively.
Sentaurus TCAD has been used to simulate the structure. Fermi-Dirac statistic transport model has been used for the incorporation of high doping concentration and the doping dependent mobility model is used for the resulting mobility of the device. Non-local BTBT model has been activated at each mesh point of the tunneling region to consider the generation of carriers and the basic operation of TFET. Bandgap narrowing model is enabled to reduce the semiconductor bandgap. Shockley-Read-Hall (SRH) recombination model is used for the recombination of carriers [22]. The simulation models mentioned above is tested and calibrated with the experimentally validated structure of [23]. The appraisal among drain current characteristics of the structure are shown in Fig. 2, the adjacency between the current characteristics demonstrates the validity of the models used. In addition, the performance of the device has been analysed by considering the fluctuation of temperature from 200 to 400 K. Finally, the presence of both uniform and Gaussian distribution of trap charges of varying concentration is incorporated at both the semiconductor-insulator interface. Different interface trap charge distribution parameters for simulation of NUTFET-DMS are indicated in Table 1.

Analysis of Small Signal Parameters of NUTFET-DMS Under Absence of Trap Charges
The capacitances among different pairs of electrodes viz. source, drain, and gate are calculated at various frequencies  Figure 3(a) and (b) show the variation of C gd , C gs , and C gg vs. gate to source voltage of the device for the absence of trap charges. In TFET as the inversion layer is connected to the drain side even at the higher drain to source voltages the C gd contribution in total capacitance C gg is more, which limits the performance of the device. But the device presented in this work has reduced the value of C gd in comparison to other structures, which is for the sake of the low-K dielectric near drain side of the device for both front and back gates [24]. From Fig. 3(a) it can be observed that the value of the C gs remains comparable to C gd up to a higher value of gate to source voltage (V gs ) (near 0.7 V) but later C gd dominates. It can be observed that the value of capacitances (C gs , C gd and C gg ) decreases with an increase in frequency this is because of the inverse relation between capacitance and frequency. Table 2 presents the comparison of the C gd with the literature, which infers that the value of C gd of the device is better than other compared structures. Figure 3(c) reports the cut-off frequency (f T ) of the device, at 10 GHz signal frequency the f T of the device rises as compared to the case of 10 MHz. This is because of the increased C gg value at 10 MHz, as f T ¼ g m 2C gg , where gm and f T are the transconductance and cut-off frequency of the device, respectively.

Impact of Trap Charges on Small Signal Parameters of NUTFET-DMS
In this module, the effect of trap charges on different capacitances of NUTFET-DMS is explored. The plot of different capacitances of the device against gate to source voltage for the presence of trap charges is shown in Fig. 4. Two different frequencies have been considered to analyse the effect of presence of interface trap charges on parasitic capacitances at different concentrations. From Fig. 4(a) and (b) it can be observed that till V gs =0.7 V, C gs dominates and the introduction of trap charges reduces the value of C gs , hence the value of  C gg . This is due to the presence of trap charges at various interfaces which causes carrier fluctuations and It can be observed from Fig. 4(a) and (c) that for V gs greater than 0.7 V, C gd dominates C gs , and the effect of trap charges gets reversed. In addition, as the concentration of trap charges increases the value of C gd increases which is due to the higher e-density at higher values of V gs . At higher values of Vgs the rising Fermi level and the effect of traps charges lead to a significant change in C gd [28]. In addition, at very high V gs and higher frequencies the capturing and emitting process of trap charges cannot track the AC signal which increases C gd as compared to the case of no trap charges, thus results in more delay [25,28]. Similarly, the same variation can be noticed in the case of total capacitance C gg which can be observed in Fig. 4(b) and (d). Finally, it can be observed that the existence of the uniform trap distribution has less effect on parasitic capacitances as compared to the case of Gaussian trap distribution due to its lower rate of carrier fluctuations.

Impact of Temperature on the Performance of NUTFET-DMS
The existence of interface trap charges and the effect of change in temperature fluctuates the sensitivity of the device which may cause severe complications for various sensing-  based applications of the device. Hence, in this section, several DC and analog/RF performance parameters of NUTFET-DMS are analysed at various temperatures (200-400 K) considering the presence of trap charges with Gaussian and uniform types of distribution. Figure 5 presents the drain current aspect of NUTFET-DMS at various temperatures including the existence of trap charges at the Si-insulator interface at 10 MHz frequency. It can be noticed that, as the temperature increases the device OFF current increases, which is due to the dominancy of the SRH mechanism in the subthreshold region [29]. A change in OFF current in the order of 10 − 17 to 10 − 14 A/µm, 10 − 16 to 10 − 12 A/µm, 10 − 13 to 10 − 12 A/µm can be observed for no trap charges, uniform and Gaussian distribution of trap charges, respectively. It can be perceived that, temperature effect is prominent on the device ambipolar current, because of the introduction of gate-drain underlap which makes the ambipolar current dependent on TAT (trap assisted tunneling) and SRH [30]. However, in case of no trap charges, the effect of temperature on ambipolar current is less as compared to the case of presence of trap charges. The impact of temperature on ON current is less as compared to OFF and ambipolar current. This is because of less dependency of BTBT mechanism on temperature; a small increment can be observed which is because of the increase in the electric field. The fact can be validated the Eq. (1), where increase in BTBT can be observed with increase in the electric field, leading to increase in drain current [31].
Where, AKANE, BKANE are constants, E f ld is the electric field, E G is the band gap.
Analysis of device parasitic capacitances considering the temperature effect and the presence of non-idealities is very important for different analog and digital applications. In order to analyse the impact of temperature on parasitic capacitances, the C gd , C gs , and C gg as a function of V gs are examined under varied temperature conditions. In Fig. 6 parasitic capacitance vs. gate to source voltage characteristics of NUTFET-DMS are presented in the presence of interface trap charges, various temperatures at a frequency of 10 MHz. It can be perceived that, with the increase in temperature C gd and C gs increase, which leads to an increase in C gg for both presence and absence of trap charges. This is due to the decrease in potential at channel drain junction with the increase in temperature. Further, the presence of trap charges enhances the value of parasitic capacitances at higher temperatures. This is because when the temperature is increased, the thermal electron and tunneling effect get intensified which makes the trap charges to capture or emit more charges. However, at various temperatures (200 to 400 K) the percentage increase of C gg is 13 %, 12 %, and 10 %, in case of C gs and C gd are 25 %, 23 %, 23 %, and 12 %,10 %, 9 % for no trap charge, uniform, and Gaussian distribution of trap charges respectively. It is found that the effect of temperature is more on the device with no trap charges as compared to the case of the presence of trap charges.

Conclusions
In this work small signal analysis of Non-uniform Si TFET with dual material source (NUTFET-DMS) is performed at different frequencies. In addition, the reliability check of the device in presence of interface trap charges and varying temperature conditions in terms of DC and small signal performance parameters have been studied. It is observed that, in the absence trap charges the increase in frequency reduces the value of parasitic capacitances. Further the results show that, in presence of trap charges the values of C gg , C gd , and C gs reduces for an increase in gate to source voltage, but after attaining a certain voltage of 0.7 V the values of these capacitances increase predominantly. Finally, it is found that the impact of temperature on OFF state current and different parasitic capacitances reduces when trap charges are present but increases in case of ambipolar current. The analysis provided in this article could be valuable for the design of different TFET at an unstable temperature environment and in the presence of non-idealities.