Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12 nm with Contact poly pitch (CPP) of 48 nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10−16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022 × 10−5 S at the gate to source voltage of 1 V. The radiation effect of an alpha particle at different energies on NS-TFET is investigated. The injection causes drain current fluctuation for a short span and the result can serve as a guideline for designing of a robust circuit. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.


Introduction
Nanosheets have emerged as a potential successor to conventional Finfets and stacked nanowires for 7 nm technology and beyond [1][2][3]. Finfets need tall and thin fins, which enhance the fabrication cost and complexity [4] while the surface roughness factor degrades the performance of stacked nanowires [5]. The Nanosheet Field Effect Transistor (NS-FET) exhibits enormous current density due to its increased effective width per footprint [6]. NS-FET has good electrostatics control and hence remains immune to short channel effects [7]. It has been reported that NS-FET shows superior electrostatic performance in comparison to stacked nanowires or Finfets [8]. Thus NS-FET with 3D vertically stacked channels is a promising candidate for future advanced technology applications [6].
At low voltages, the device miniaturization below 50 nm leads.
to immense OFF-state power consumption and elevated subthreshold swing (SW) [9,10]. The SW at CPP of 48 nm has been reported as 83mv/decade and 94 mv/decade for nfet and pfet respectively [11]. The thermionic conduction mechanism of NS-FET makes SW temperature-dependent and this temperature constraint makes SW worse.
Vertically stacked Junctionless nanosheets(JL-Ns) show highly improved performance in terms of leakage current and SW [12]. JL-Ns with a different number of channels exhibit high ON current. At channel/oxide interface, JL-Ns provide indemnity for mobility degradation due to scattering of carriers [13]. The major bottleneck associated with JL-Ns is the exhibition of high leakage current while SW becomes nonscalable below 60 mv/decade. Tunnel Field Effect Transistors (TFETS) provide a remedy for high OFF-state current and exhibit steep SW [14][15][16]. TFETs work on the principle of the BTBT mechanism. In NS-FETS, the BTBT mechanism can be incorporated; thus making it a novel device consisting of vertically stacked nanosheet tunnel field effect transistor (NS-TFET). Inner spacers can be treated as an underlapped region for TFETS. It has been further reported that underlapped source and drain regions assist in reducing ambipolarity [17,18]. The fabrication process of TFETs varies from that of Mosfets in terms of their source doping. Thus, the fabrication of NS-TFET is comparatively easier to implement with minimal deviation from the NS-FET fabrication process [19,20].
In section 2, we have discussed the calibration characteristics of NS-FET. Section 3 describes the design of a vertically stacked NS-TFET device with three layers. In our proposed work, the design parameters of the NS-TFET device are optimized to achieve good electrostatics. To the best of our knowledge, no tunneling-based Silicon stacked nanosheets with P-I-N configuration have been reported in the literature. Section 4 highlights the performance metrics of NS-TFET. The ultimate aim of NS-TFET is to tune the tunneling barrier at the extended source-channel junction; thereby reducing short channel effects such as low leakage current, minimal DIBL, and superior Subthreshold swing. Section 5 explains the drawn conclusions.

I. Calibration Characteristics
Vertically stacked Nanosheet transistors exhibit excellent ON-current density due to their increased effective width. The reference model of NS-FET with three layers having CPP of 48 nm, the gate length of 12 nm, and a sheet thickness of 5 nm are simulated on a visual TCAD platform [21]. The inner spacer thickness and the width of NS-FET are kept at 5 nm and 50 nm respectively. The vertical sheet-to-sheet spacing is 10 nm. A combination of high-k dielectric material HFO 2 having thickness 1.28 nm and SiO 2 having thickness of 0.5 nm has been used for effective oxide thickness of 0.7 nm. The symmetrical source and drain doping have a value of 3 × 10 20 cm − 3 while the channel doping is 1x10 17 cm −3 . Titanium Nitride material has been selected for gate with gate metal work function of4.7 eV. The calibration graph of the simulation result is benchmarked with the experimental data at a drain voltage of 0.65 V as shown in Fig. 1.

The Fabrication Process Flow of NS-TFET in Tcad
The process flow of NS-TFET starts with the formation of Silicon on insulator (SOI) substrate. Then nanosheet stack is epitaxially grown over the substrate. The nanosheet stack comprises of alternating series of Si/SiGe layers. After that, fin patterning is done by anisotropic etching of Si and SiGe layers. Shallow trench isolations are filled with oxide in low thermal budget conditions. In a selected region of nanosheet stack, patterning of dummy gate and spacers is done. After dummy gate patterning, source and drain regions are epitaxially grown. The doping of the p + source region involves three steps i.e. lithography, implantation and removal of photo-resist. The same procedure is then followed for n + drain doping. Then etching of the dummy gate stack is performed. Then the subsequent release of the Si channel is done with the etching of sacrificial SiGe layers. The gate stack is formed by depositing high-k oxide and gate metal. A similar fabrication process flow is reported in the literature [11,35].

Device Structure
The dimensions of NS-TFET are in accordance with the reference structure [21]. The proposed NS-TFET device differs from the NS-FET device in terms of the type of doping. The reference structure has n-type symmetrical doping in both source and drain [21] while in NS-TFET; asymmetrical P-I-N configuration has been employed. P-I-N design with BTBT mechanism shows tremendous improvement in short channel effects (SCE). In the BTBT mechanism, the width of the tunneling barrier is modulated on the variation of gate voltage at constant drain voltage. The asymmetric lower drain doping is used to curb ambipolar behavior [22,23]. Work function engineering has been done to achieve desirable results. For simulation of NS-TFET, the work function is chosen to be 5.00 eV. Figure 2 represents the 3-D view of NS-TFET. Figure 2b depicts a cross-sectional view of NS-TFET with P-I-N configuration. The geometric parameters, doping concentrations of NS-TFET are listed in Table 1. Physical models used in Genius code define the behavior of semiconductor devices [22]. These models specify physical parameters like mobility, recombination rate, etc. Drift-Diffusion (DD) model is the fundamental solver for Poisson's and continuity equations [23] and has been recommended to use for determining the transport of charge carriers and computation of the drain current. The Lombardi model is invoked for carrier mobility in the inversion layer of the NS-TFET device. This mobility model incorporates bulk mobility, mobility due to surface charge, and scattering [24]. Gate tunneling plays a pertinent role in NS-TFET devices. Kane's Model invokes the BTBT mechanism for carrier generation. For 3D simulations; Kane's model provides better convergence results [31]. Shockley-Read-Hall (SRH) model has been considered for carrier recombination mechanism and it stimulates the leakage current that determines Ioff in TFETs [32].

Results and Discussion
Three-dimensional simulations of NS-TFET are done using COGENDA-TCAD software [24]. The physical models such as the DD model, Lombardi mobility model, Kane's BTBT model, and SRH model are evaluated at each mesh node using TCAD software. The performance metrics of vertically stacked NS-TFET device has been discussed in this section.

Triple Nanosheet
Gate all-around devices provide little room for carriers to drift when the transistor is in ON state [25]. The stacking of nanowires increases the effective width and allows the carriers to flow, but the increased device capacitance along with surface roughness decreases the speed of carriers [26]. Stacking thin nanosheets atop one another enhances the effective width and hence provides larger room for carriers to flow. This further enables the large drive current while maintaining constricted control of the leakage current [25,26].
We have performed the simulations for vertically stacked single, double and triple NS-TFETs at the drain to source voltage (Vds) of 0.65 V. The plot of drain current of single nanosheet (Id_1ns), double nanosheet (Id_2ns), and triple nanosheet (Id_3ns) is depicted in Fig. 3. The results show that ON-current increases exponentially in the case of double and triple NS-TFETs as compared to single NS-TFET. The drain current of Id_3ns and Id_2ns is observed to be 2.0168 and 3.03 times higher than Id_1ns respectively. Ion/Ioff ratio in triple-stacked NS-TFET is 9.557 times that of single NS-TFET while with double-stacked NS-TFET, it is observed to be 4.73 times high. Hence, three-layered NS-TFET exhibits superior performance in terms of drive current. Table 1 The design parameters of vertically stacked NS-TFET [21] Parameters Dimension

Energy Band Diagram
The NS-TFET exhibits similar behavior to that of n-TFET on the application of constant drain voltage. In NS-TFET, an interband tunneling conduction mechanism has been incorporated. In the OFF state of the p-type extended source of NS-TFET, very few electrons are available at the conduction band of the source for injection into the channel. This results in negligible movement of carriers and hence poor leakage current. With variation in the gate voltage, the energy band of the channel varies relative to the extended source. From Fig. 4, it is evident that at saturation voltage of Vds = 0.65 V with positive gate to source voltage (Vgs > 0 V), the valence band of the extended source is aligned with the conduction band of the channel. The carriers tunnel through the potential barrier between the valence band of the extended source and the conduction band of the channel. These charge carriers present in channel drift towards the extended drain (ext_d) to produce drain current.

Sub-Threshold Swing and DIBL
The main premise of designing NS-TFET as an alternative to NS-FET is due to its refined subthreshold swing. NS-FETs operate on a thermionic injection mechanism and thus have a thermal limit of 60mv/decade [27]. In NS-TFETs, the BTBT conduction mechanism is utilized. NS-TFET offers desired steep SW of 23mv/decade at low Vds = 0.10 V with the desired ON-state performance. For this subthreshold regime, the threshold voltage is 0.402 V and negligible Drain induced barrier lowering (DIBL) of 10.5 is found. SW gives a higher Ion/Ioff ratio and thus makes itself apt for faster switching circuitry. Table 2 represents the performance metrics of NS-TFET in terms of threshold voltage, SW, DIBL, etc.

Ambipolairty
The transfer characteristics of three-layered NS-TFET under different doping concentrations have been represented in Fig. 6. It is evident from the figure that NS-TFET shows its ambipolar behavior when it is subjected to the negative gate to source voltage(Vgs < 0 V). The electrons tunnel from the channel to the conduction band of the extended drain and thus results in the current flow of the same polarity and hence behave as p-type. This behavior is not desirable in digital circuitry where tunneling between channel and drain is curbed [28][29][30]. The best results are observed for the doping concentration of 10 17 cm −3 . It is evident that with the decrease in the doping concentration of drain, an ambipolar current is reduced up to a considerable amount. The depletion width of the drain side increases due to lower drain doping concentration. As a result, the ambipolar current reduces.

Transconductance(g m )
Transconductance (g m ) is a performance metric, which reflects the device efficiency in terms of effective input voltage conversion into output current [31]. It is described by first-order differentiation of drain current with reference to the gate to source voltage [32].
where I dd represents current tunneling from the source terminal to the drain end. V gs , V ds represents the gate to source voltage and constant drain voltage respectively. The simulation of single, double and triple NS-TFETS is done at Vds = 0.65 V. The plot of the transconductance variation of single nanosheet (single_ns), double nanosheet (double_ns), and triple nanosheet (triple_ns) is depicted in Fig. 7. From the figure, it is evident that there is an  voltage. This is due to the hike in tunneling of carriers in the channel. It is unambiguously clear that triple NS-TFET exhibits comparatively higher transconductance of 3.022 × 10 −5 S at the gate to source voltage of 1 V. The transconductance of triple_ns is 1.5 and 3 times higher than double_ns and single_ns respectively. Hence, threelayered NS-TFET exhibits enhanced transconductance due to the larger effective width.

Transconductance Generation Efficiency(TGF)
Transconductance generation efficiency (TGF) is another vital parameter that determines the efficiency of NS-TFET in terms of conversion of the current into transconductance (g m ) and is given by [33]. The value of TGF increases with an increase in transconductance. High TGF depicts good analogue performance.
The TGF variation of single (TGF_1ns), double (TGF_2ns) and triple nanosheet (TGF_3ns) with respect to the gate to source voltage is depicted in Fig. 8. It is observed that the TGF of NS-TFET reduces with an increase in gate voltage. This is due to the saturation of the drain current to a specific value. As a result, TGF decreases with an increase in Vgs. At low voltages, three layered NS-TFET shows max T G F .

Total Gate Capacitance(C gg )
The total gate capacitance (C gg ) is the summation of intrinsic capacitances of the source and drain terminals. High transconductance and low gate capacitance are requisite for good analogue performance [32]. The plot of the total gate capacitance (C gg ) as a function of gate-source voltage (Vgs) at Vds = 0 V and Vds > 0 V is depicted in Fig. 9. For Vds = 0 V, total gate capacitance (C gg ) shoots at a lower value of Vgs = 0.8 V while for Vds > 0 V, a significant increase of (C gg ) is observed at higher Vgs. The value of (C gg ) at Vgs = 1 V and Vds = 0.65 V Vgs = 1 V is found to be 1.662 × 10 −17 F.

P-ns-TFET Design
The vertically stacked NS-TFET with N-I-P configuration has been designed to demonstrate its p-type characteristics. The geometry parameters are kept the same as mentioned in Table 1. Work function engineering has been implemented to match ON and leakage currents. For p-SN-TFET, the work function is kept at 4.23 eV. The source has donor impurities with a concentration of 3 × 10 20 cm −3 while the drain has   Table 2.

Alpha Particle Effect on NS-TFET
The effect of alpha particle radiation on NS-TFET has been investigated in Fig. 11. The impact of alpha particle injection into the source region is greater than that into the drain region [34]. So in the proposed device, the particle is injected into the centre of the source region with an incident angle of 90°. On injection, drain current shoots due to the generation of electron-hole pairs and then restores to the steady-state due to recombination of electron-hole pairs. Figure 11 depicts the variation of drain current with time at three different alpha particle energy injections (3 MeV, 4 MeV and 5 MeV). The peak drain current is observed to be 24.9 μA, 23.3 μA and 21.83 μA for 3 MeV, 4 MeV and 5 MeV alpha particle energy injections respectively. The hike in the current is observed for a short duration of 13.80 ps, 13.70 ps, and 13.50 ps at incident energies of 3 MeV, 4 MeV and 5 MeV respectively.

Conclusion
In this paper, vertically stacked NS-TFET with three layers has been modeled and simulated. The short channel effects have reduced tremendously by using the BTBT mechanism with P-I-N configuration. A high Ion/Ioff ratio with a low leakage current has been achieved. NS-TFET renders 23mv/decade SW and 10.5 DIBL which is 70% and 65% lower than NS-FET respectively. High Transconductance, device efficiency, total capacitance parameters of NS-TFET have been extracted. The injection of an alpha particle on NS-TFET results in drain current fluctuation for a short span and recovers soon. p-TFET configuration for NS-TFET has also been proposed which makes it apt for faster switching applications. All these advantages make NS-TFET a viable option for next-generation applications and future advancements.