Crosstalk Noise Analysis in Coupled On-Chip Interconnects Using MRTD Technique

In this paper, the Crosstalk noise analysis of coupled on-chip interconnects have been analyzed. The multiresolution time-domain method (MRTD) is used to analyze the crosstalk noise model. The crosstalk induced propagation time delay and crosstalk peak voltage on the victim line of interconnects have been de-termined and compared to those of the conventional ﬁnite diﬀerence time domain (FDTD) method and validated with HSPICE simulations at the 22nm technology node. The results of the proposed method shows that crosstalk induced propagation delay in dynamic in-phase, out-phase and peak voltage timing, as well as the peak voltage value for functional crosstalk in the copper interconnects are an average error of less than 0.53% for the proposed model and HSPICE simulations. The results of the proposed model are closely similar to those of HSPICE simulations. Electromagnetic interference and electromagnetic compatibility of on-chip interconnects can also be addressed using the proposed method.

these requirements, the chip's complexity and number of sources of variations have increased, and the tightly packed interconnects emit transient crosstalk at high operating frequencies [1,2]. For a long time, accurate peak noise timing and peak crosstalk noise estimation in a driver-interconnect-load system has been a key architecture view [3]. On the basis of lumped and distributed RC interconnects, various crosstalk and delay models are proposed in [4,5]. Masoumi et al. [6] computed crosstalk noise effects in a capacitively coupled RC interconnect line using closed form expressions. Ismailetal. [7] strengthened the model by integrating selfinductance effects and estimated the RLC line propagation delay. Because of the introduction of low resistive interconnect materials and fast operating switching frequencies, parasitic inductance has began to play an important role in on-chip interconnect efficiency. To accurately estimate the output, the on-chip interconnects must be viewed as scattered RLC lines or transmission lines [8].
In order to evaluate crosstalk noise, previous models interpreted the non-linear CMOS driver to be a Simply linear resistor [9,10] which appears to deviate from the effects. MOSFET operates approximately 50 percent of its operating in the saturation region during the transient period, and later in linear (or) cutoff regions. Several methods with different analytical solutions, Finite Difference Time Domain (FDTD) approach and SPICE results have been documented in recent works for the DIL system in [11]. In the current state, several researchers have researched the crosstalk results based on the algorithm of the traditional finite-difference timedomain (FDTD) as it is precise [12] and Vobulapuram et al. [13] applied the FDTD approach to a nonlinear driver of CMOS by using the model of alpha-power law and the model of nth-power law, respectively, and studied the effects of crosstalk in Cu interconnects.
The FDTD approach is an important computational procedure used to solve problems of electromagnetic and partial differential equations. The FDTD approach is numerically dispersive [14] and is used for propagation along the discretization. Thus, there is an extreme need for a model with an edge in numerical dispersive properties [15]. Krumpholz and Katehi [16] have suggested a multi-resolution time domain (MRTD) approach with an additional advantage of the numerical dispersion characteristics. Grivet-Talocia [17] suggested the MRTD model in view of the Haar Scaling function as a basic function and gives the same precision with respect to the FDTD model. And MRTD technique used as a basic function based on Daubechies' scaling function, is proposed by Fujii et al. [18] as three and four extinguished moments, which are more precise than the FDTD system. Transient analysis for twoconductors transmission lines with admirable numerical dispersion, Tong et al. [19] proposed an MRTD model. Features and improved precision with SPICE, relative to the FDTD model. Rebelli et al [20,21] suggested the MRTD approach to evaluate the signal integrity of coupled Copper interconnect driven by linear resistive and a nonlinear CMOS dependent on the Daubechies scaling function at four extinct moments. and also, Rebelli et al. [22] applied the MRTD approach driven to nonlinear CMOS using the nth-power law model to evaluate crosstalk noises in coupled on-chip interconnects.
In this paper, the analyses of crosstalk effects of onchip interconnect were studied using the MTRD technique and considered the nonlinear CMOS driver model using modified Alpha-power law model that includes the velocity saturation effect. The most effective time domain analysis is presented for mutually coupled MRTD based on-chip interconnects. The obtained results using the MRTD model is compared with the conventional FDTD method and HSPICE as well.
The rest of the paper is arranged as follows. transmission line-based MRTD model is discussed in Section 2 and the MRTD Model Comparisons and Evaluation is presented Section 3. Finally, section 4. conclusions are given.

MRTD MODEL OF ON-CHIP INTERCONNECTS
The model of two-coupled on-chip interconnect with driver and load is shown in figure1. The parasitic capacitances of CMOS are expressed by C m , which stands for gate-to-drain coupled capacitance, and C d , which stands for drain/source diffusion capacitance. R 1 and R 2 are the line resistances, C 1 and C 2 are the line capacitances, L 1 and L 2 are the line inductances, and C L1 and C L2 are the load capacitances of line1and line2, respectively. All these values are obtained in per unit length (p.u.l). Both capacitance and inductance are coupled to the interconnect lines. C c and L m are the p.u.l coupling capacitance and mutual inductance of coupling interconnect lines, respectively. The interconnect line's position and time are denoted by x and t, respectively.
The MRTD model for mutually two-coupled on-chip interconnects is built in this section using basis function of Daubechies' scaling function with four vanishing moments (D 4 ). Fig. 1: CMOS drivers driven two-coupled on-chip interconnect lines, which are terminated by capacitive loads.

Model formulations for two-coupled on-chip interconnects line
The Telegrapher's equations can be used to describe the coupled interconnects mathematically. The coupled on-chip interconnects are defined as [22,23] using these equations.
where x and t are the positions and time, respectively. R, L, and C are two-dimensional interconnect impedances that are measured using [23]. The current and voltage variables for a two-coupled interconnect line are I = [I 1 , where subscript 1 corresponded to a line 1 and subscript 2 corresponded to a line 2. The voltage and current evaluations point on interconnect line 1 are shown in Figure. 3.
Alternatively, current and voltage points are considered in time and space to evaluate telegrapher equations. The currents and voltages are separated by ∆t 2 in time and ∆x 2 in space for better accuracy, as shown in Figure 2, where∆t is time and ∆x is space represent in discretization intervals.  The interconnects line l of length is resistive driver at x = 0 and terminated at x = l is capacitive load. The line is divided consistently to N x segments of a length ∆x = l N x , indicating the discretization voltages(V) and currents(I) nodes, which are coefficients of unknown as seen in Figure 3, where source current represents I 0 . Fig. 3: Spatial discretization for I and V on on-chip interconnect line.
The voltages and currents terms can be extended using a known function (h n (t) and Φ k (x)).. the coefficients of unknown in order to solve equations (1) and (2) by following the method defined in [16] as: is the coefficient of expansion current and V k n is the coefficients of the voltage expansion in terms of functions scaling, and the indices n and k are discrete time and space indices related to time and space organizes via t = n∆t, and x = k∆x. Functions h n (t), and Φ k (x) defined as: Where, pulse function h(t) is defined as Where, Φ(x) signifies the scaling function of a Daubechies, and h(t) represents the Haar scaling function The following integrals [24] are considered in order to derive the MRTD technique for a equations (1) and (2): Where the Kronecker symbol is represented by 'δ k,k ′ ' and 'δ n,n ′ ' The effective support sizes of the basis functions is indicated by the Ls. By considering the scaling function of Daubechies as the basis functions with four vanishings moment (D4). The coefficients b(i) are called connections coefficients. Table1 shows b(i) for 1 ≤ i ≤ L s ,, whereas b(i) for i < 1 it can be accomplished by symmetry condition b(-1-i) =-b(i), and zero Where the scaling function of Fourier transform f (x) iŝ Φ(λ).
The follow iterative calculations for currents and voltages were carried out to employing the Galerkin technique [16] in equation (1) and (2) and by using the test functions Φ k h n+ 1 2 (t) and Φ k+ 1 2 h n (t): for i = 1, 2, 3, · · · , L s − 1 and voltages are V n+1 i and V n+1 N x−i+1 for i = 2, 3, · · · , L s Many of these currents and voltages have a number of terms that surpass the index ranges in iterative equations (8a) and (8b) Equations (8a) and (8b) need to be decomposed using the relationship in [25] to update the iterative equations of currents and voltages, which satisfies the connection coefficients b(i) provided by the connection coefficients b(i) given by By Substituting (9) into (8b), to get To decompose (8b) considering a corresponding term with i as: for at i = 1, 2, 3, · · · , L s − 1 Equation (11) is further adapted by employ the at boundary conditions as proved in Sections 2.3 and 2.4.

Modeling of CMOS Driver
Two-coupled on-chip interconnect line equivalent electrical circuit model is shown in figure2. The input voltage (Vs) is a two-dimensional vector with the formula The interconnects line is driven by a CMOS driver [26] that follows a modified Alpha power law model. The velocity saturation effects, as well as the finite drain conductance parameters, are included.  Table 2 are used for this analysis.

Modeling at near-end boundary condition
The DIL system's modeling is used under boundary conditions. The current and voltage node points are at the near-end terminals defined by I 0 and V 1 , respectively. where the nodal analysis of the terminal equation is given Applying discretization and Galerkin technique to (14) then the near end terminal a voltage is carry out at k=1 from (8b) By following the steps from the equations (9) (11) to decomposed equation (16) as Iterative equations (17a)(17c) to be considered as CAD, i.e., central difference equations. in the particular calculations, the subscript to the terms I have surpassed the index range. To solve this, substitute the central difference scheme by using the forward difference scheme. By leaving the weight coefficient in each equations unchanged, iterative equations can also be obtained.
From the above equations (18a) -(87c), the iterative equation at the near-end boundary node voltage of V n+1 1 is obtained through the following: In equation (19), substituting by I Where,

Modeling at far-end boundary condition
Similarly, the nodal analysis equation at load current I N x+1 is given by the far-end terminal (k = Nx+1) is: then the final iterative equations given at the far end of the terminal is Where Some of the term indices surpass the index ranges for all the nodes between the terminals in the algorithm extension to obtain and update the iterative equations, so a truncation method is applied by taking V n+1 k as an examples for k = 2, 3, · · · , L s and by subsequent the steps of equations (10) and (11), it can be decomposed (8b) as an example for k = 2, 3, · · · , L s From the equations (23a)(23f) stated above, it is also observed that the indices of the equation do not surpass the index ranges for the first k terms. In addition, all calculations for which the index terms surpass the index spectrum appear in the remaining L s −k term. As L s − k terms are out-of-bound these equations are not available for iterative equations in MRTD model. To prevent problem, a truncations is built in calculations where the index range is surpassed. first k terms by summing up the in equations (23a)(23f), iterative equations can be updated for at k = 2, 3, · · · , L s V n+1 Using the same steps illustrated in equations (23a) -(23f), a altered iterative equation of voltages at interiors point as presented in equation (25) and voltages near a load as presented in equation (26) is. for at the k = L s + 1, for at the k = N x − L s + 2, N x − L s + 3, · · · , N .
Iterative current equations can also be modified by subsequent the same voltages iterative equations with minor modifications. As seen in Figure3, it is observed that at the half-integer points the current nodes appear. It implies that at the interiors points of the terminals, all the currents are located. Therefore, the current near the terminals need alteration. For iterative current equations near to the terminals, it is necessary to decompose (8a) using the steps of iterative voltage of the equations. The final updated iterative current equations are given as for at the k =1, near at the source for at the k = L s +1, L s +2, · · · , N x−L s , N x−L s +1. at the Interior point iteratives equations for at the k = N x − L s + 2, N x − L s + 3, · · · , N x, Near the load, iteratives equations are In the context of this bootstrapping method, modified voltage and current iterative equations are tested. Firstly, in terms of historical Voltages and current values, voltages iterative equations are solved at a rigid time using equations (20), (22), (24)- (26). Then, equations (27)-(30) solve the iterative equations of currents in terms of voltages measured initially and past values of current. The courant stability condition [19,25] is thus known as the stable output for MRTD iteratives equations.
Which states that for each cell, the time of propagation must be higher than the time step. Where q is the current numbers given by q = 1/ Ls i=1 |b(i)| = ϑ∆t/∆x and ϑ and v is the phase velocity of the line propagation. However, the boundary conditions will always gratify the stability requirement as these are explicitly derived out of a implicit expression.

The MRTD Model is compared and validation
The Performance analyses of two-lines coupled on-chip interconnects structure is presented. The proposed model is validated by comparison it to conventional FDTD model and with HSPICE simulation. The interconnects load is driven by CMOS driver, the interconnects dimensions are taken from ITRS [27,28]. At 22nm technology node, the interconnect is placed from a ground plane is 99nm. thickness of the line is 66nm. The width and space between lines are to be equal and the value is 33nm. The inter level dielectric medium permittivity is 2.3. The length and load capacitance of the interconnects are 1mm and 2fF. The voltage Vdd is 0.8V. The signal voltage swings from 0 to 0.8V (LowHigh) or 0.8 to 0V (HighLow). The input source voltages have a transition time is 20ps. The proposed MRTD model implemented by MATLAB using Intel(R) Xeon(R) CPU E3-1225v6 operating at 3.30GHz and HSPICE tool [29].

Analysis of transients and crosstalk in two coupled on-chip interconnects
This section covers the transient and crosstalk studies of a two-line coupled on-chip interconnects system. Line 1 is the aggressor in the coupled two on-chip interconnects system seen in Figure 1, and line 2 is the victim line. On the other end of the victim spectrum, the effect for functional, dynamic in-phase, and dynamic out-phase switching has been found using the proposed model, HSPICE, and the conventional FDTD model. On the victim line, the transient reaction is investigated. The effect of functional crosstalk is explored by modifying line 1's aggressor input from 0.8V to 0V while holding line 2's victim in quiescent mode. When both aggressor and victim stimuli turn at the same time, the impact of in-phase or out-phase is also explored. At the far end of the victim line, the transient graph results based on the above conditions are compared. Figure (4a) displays the functional, dynamic in-phase, and dynamic out-phase transient responses (4c). Figures 4(b) and 4(c) demonstrate that the victimline peak solution has higher dispersion errors than the conventional FDTD method. The proposed model, on the other hand, is superior to the conventional FDTD model in terms of precision due to its significant superiority in numerical dispersion properties. Figure 4(c) illustrates how miller coupled capability allows signal transitions to take longer during out-phase than during in-phase switching. The results of proposed MRTD  In comparison to HSPICE, Table 3 indicates the computational error associated with estimating functional crosstalk effects over victim line2 for conventional FDTD and then suggested MRTD models. Efficacy at multiple input transition times. The proposed model's average error in predicting crosstalk peak voltage timing is found to be 0.42 percent, compared to 0.92 percent for the conventional FDTD method. Table 4 also indicates that the proposed model correctly      The computational error associated with estimating dynamic in-phase crosstalk effects over victim line2 for conventional FDTD and proposed MRTD models is shown in table 5. sturdiness of input transitions at different times the proposed model is observed to have a 0.53 percent average error in propagation delay estimation, compared to 1.4 percent for the conventional FDTD method.
In table 6 indicates the computational error associated with estimating dynamic out-phase crosstalk effects over victim line2 for conventional FDTD and proposed MRTD models. sturdiness of input transitions at different times the proposed model has a 0.18 percent average error in propagation delay estimation, compared to 0.38 percent for the conventional FDTD method. The simulation results of proposed MRTD model match HSPICE correctly in all input switching situations and outperform the conventional FDTD method The graphs for peak voltage timing and peak voltage value on the victim line as a result in functional crosstalk generated by a varied in input transition time are seen in Figures 5 and 6. At different input transition times, Figures 7 and 8 illustrate dynamic in-phase and out-phase crosstalk propagation delays.The results for both functional and dynamic crosstalk are MRTD model validated with HSPICE and outperform the conventional FDTD model.  line2 in functional switching with varying values of load capacitance CL. Figure 11 demonstrates the CPU computing time specifications for crosstalk study of coupled on-chip interconnect lines in various scenarios. The simulation results of the proposed MRTD model fit HSPICE adequately and outperform the conventional FDTD model, according to the results.

Conclusion
The modified alpha power law model is used in this paper to build an analytically dependent MRTD model for functional and dynamic crosstalks study of coupled two transmission lines driven by a CMOS driver. For two line coupled on-chip interconnects, in this work provided a detailed study of functional, dynamic inphase, and out-phase induced effects on the victim line. The Courant condition is strictly followed by the suggested model's stability. The influence of input transition time on crosstalk propagation delay under dynamic and peak voltage timing, as well as the peak voltage value for functional crosstalk, is studied. With regard to HSPICE, the proposed MRTD model and the FDTD validate that the proposed MRTD model is in good agreement with HSPICE. The findings show that the average error of crosstalk-induced propagation delays in both dynamic in-phase and out-phase on-chip interconnects is 0.53 percent and 0.18 percent, respectively, according to the proposed model. Functional crosstalk has a peak voltage timing of 0.42 percent and a peak voltage value of 0.27 percent. Furthermore, the suggested MRTD model and FDTD model are validated with HSPICE for peak voltage timing and peak voltage value on victim line for functional cases for various values of load capacitances with an average error is less than 1%. The proposed model time efficiency over the FDTD model and HSPICE is reported, suggesting that it has the ability to analyses crosstalk in on-chip interconnects quickly and accurately. The analysis was performed on two coupled interconnects, but it can also be generalised to M-mutually coupled on-chip interconnects.

Figure 1
CMOS drivers driven two-coupled on-chip interconnect lines, which are terminated by capacitive loads.

Figure 2
Space and time discretizations on on-chip interconnect line. Spatial discretization for I and V on on-chip interconnect line.   The victim line of dynamic in-phase 50% propagation delay varied input transition time.

Figure 8
The victim line of a dynamic out-phase 50% propagation delay varied input transition time.

Figure 9
Peak voltage timing with varied Load capacitance for victim line.

Figure 10
Peak voltage with varied Load capacitance for victim line.

Figure 11
Computational time with different crosstalk switching.