In this paper, a generic FPGA implementation of the Grunwald-Letnikov definition of fractional-order derivative is presented, where the parameters are adjustable without changing the Verilog HDL code. Besides, there is no strict limit on the range of parameters and no need to pre-store coefficients to approximate the binomial coefficients. The memory length changes dynamically to reduce the number of calculation times. When the memory length becomes large, the advantages of this method will be more noticeable. Theoretically, it is a more generic FPGA algorithm not only suitable for the short memory principle, but also for the general Grunwald-Letnikov definition. In addition, a multi-scroll fractional-order NEW-SPROTT-41 system is designed by using a square family function. Its stability is simply analyzed, and the proposed FPGA implementation is applied to the proposed system. What’s more, the integrated logic analyzer(ILA) is used to capture internal signals of the FPGA without an oscilloscope. The experimental results are consistent with the numeric simulation results very well.