A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.


Introduction
Our day-to-day life has taken a massive turn in evolving exponentially with the help of newly developed technology. In large storage devices data processing speed should increase to process massive data. It provides an interface with easy access, fast operation, better performance and output signal processing. Fast processing and operating speed parameters are achieved by 1 3 the proper storing and retrieval of data to and from the memory locations. Rapid processing of huge quantity of records implies quick access of these data at anytime and anywhere essential. Memory modules take part an imperative position of data storage and data retrieval of records whenever it required. For Graphical Processing Unit(GPU), Microprocessors which are highspeed processors, one among the main choices for system designers are Static Random-Access Memory(SRAM) as cache memory. The critical program files, repeatedly used commands and stored data, all are in cache memory. Since data retrieval rate in cache is greater than in SRAM. It is possible to select RAM(Random-Access Memory) for RISC(Reduced Instruction Set Computer) systems PC (Personal Computer) etc. based on certain tradeoffs in design. As compared to DRAM(Dynamic Random-Access Memory), SRAM is much favorable in process, if the major feature for selection is not cost, owing to its advantage in volatility, density, rapidity and further custom performance attributes.
The configuration of SRAM is normally a latching circuitry and it is bistable i.e., two inverters connected back-to-back to form a cross coupled structure and in one side of inverter same information and other side its complemented form. Six Transistor(6 T) structure is used in conventional SRAM. It requires a bit refreshment in every few seconds, SRAM has a feature of self-refreshing to avoid extra circuitry. The optimization in RAM cell is focused on the other perspectives such as energy depletion, stability and dissipation of power. SRAMs are the primary contributors of power even though it has a stable structure and alignment. Static power dissipation and dynamic power dissipation are the major classification in dissipation in CMOS(Complementary metal-oxide semiconductor) style. These two classifications definitely affect the power dissipation capacitance, output rise time, output loading effects, input voltage level, etc. are a few parameters. So, identifying the net leakage in power is significant in circuit design since scaling of the circuit, current requirements, heating effects are there by can redesign. It is also mandatory to consider in circuit design.
Here the 6 T and 9 T(Six Transistor) SRAM array have been implemented and is compared in terms of power [1]. By using dynamic power reduction methods power of 9 T SRAM cell is reduced as compared to conventional 6 T SRAM and thus by reducing total power in single cell, the power dissipation in a whole array can be factorized. Each SRAM cell holds a single bit, practically a word or blocks of data are stored into an array of cells that can be accessed randomly for both read and write operation by the use of addresses. These operations are carried out in an array using the peripheral circuitry that ensures the proper implementation of the read or write operation in the SRAM array. Periphery circuits like Write Driver Circuit(WDC), Pre-charge Circuit(PCH), Sense Amplifier(SA) and Row Decoder(RD) are also implemented. Here a frequency analysis is conducted in the proposed design and compared with existing. It is the modification of conventional six transistor SRAM cell. Tanner-Tool v16.01 for a 250 nm technology node is used for the analysis. Also, the delay(speed), power dissipation and Power-Delay-Product(PDP) as performance parameter is evaluated and then compared. It gives an idea of system stability also cell structure performance. Nevertheless, the investigation is put through the design layout and parameters such as placement in addition to the area and proximity problems.

Methods
The modified design of SRAM cells having less power dissipation. There are 5 pMOS(p-channel metal-oxide semiconductor) transistors and 4 nMOS(n-channel metaloxide semiconductor) transistors are used to design the proposed structure of 9 T SRAM cell and using Tanner tool the projected design is related with six transistor SRAM cell at high frequencies.

A. Single SRAM with 6 Transistors
There is combination of nMOS and pMOS transistors formed simple SRAM cell. Here 4 nMOS transistors and 2 pMOS transistors are used, so it is known as 6 transistor SRAM cell or 6 T SRAM cell. A cross coupled structure is used to create inverter by using two pMOS and two nMOS devices. The Q and Qbar are the simple and complemented output of inverter, stored within the inverter itself. The bit line and bit line bar of the memory is used for read or write operations, which are connected to the cell using two nMOS transistors called access transistors. When WL(Word Line) is on i.e., the access transistors will turn on therefore Bit Line and Bit Line bar will connect to the cell. Thus, the two access transistors play an important role in the read-write process of the cell [2]. The schematic of SRAM cell in Fig. 1, designed using S-Edit of Tanner tool. The bit lines will attain a value of Vdd in read operation. Also, the pMOS access transistors will turn on when a logic 1 is applied to Word Line in a particular cell. If one cell carries a value of logic 0 then the bit lines are discharged. Similarly, if one cell carries a value of logic 1 then the bit lines are pre-charged or remains same. Thus, the bit lines are updated with the exact value stored inside cell. So, in read operation the sense amplifier will sense the voltage difference of bit lines. If the data needs to written into the cell is 1 then load the bit line as 1(bit line bar as 0) and change word line as high. Therefore, the pass transistors will turn on and the value will move from bit line to cell. In write operation, if the data is logic 0 then load the bit line as 0(bit line bar as 1) and change word line as high [3].

B. Proposed 9 T SRAM Cell
Forced sleep technique [4] is a mixture of forced stack and sleep effect technique. In sleep transistor technique pMOS is coupled between pull-up track and Vdd however nMOS is coupled between the pull-down track and ground whereas in forced sleep technique this connection is reversed. Here nMOS is connected to Vdd and pMOS to ground. For reducing average power consumption, swing voltage reduction method is combined with forced sleep technique [5] (Fig. 2).
A pair of pMOS and nMOS is connected back-to-back as in a cross coupled inverter fashion similar to conventional 6T SRAM as shown in Fig. 2. There are two nMOS transistors connect bit lines to the cell, they are entitled as access transistors. The coupled voltage sources may reduce bit line swing voltage, the two pMOS transistors are controlling this swing. In forced sleep technique sleep transistors are designed using pMOS and which are in the pull-down path. The control signal will control the operations of sleep transistors which are pMOS in structure [6] also the voltage sources are coupled to pMOS transistors.

Array of 6 T and 9 T SRAM Cells
A low power 4X4 array with a storage capacity of 16 bits is designed using proposed SRAM cell which is in forced sleep SVR(Swing Voltage Reduction). Array structure including peripherals such as SRAM cell, Precharge circuit [7], write driver circuit, Row decoder and Sense amplifier are connected to the basic array block as shown in Fig. 3.
The output of 4 × 4 9 T SRAM cell [8] is compared with that of previously obtained 6 T array results in terms of total power consumption.

Performance Evaluation
The proposed 9 Transistor SRAM cell is analyzed and power dissipation is compared with 6 transistor SRAM cell. Additionally, the parameters such as speed, power consumption and the PDP as performance parameter are evaluated then frequency analysis is done for various frequencies like 500 MHz, 1 GHz, 2 GHz.
The power dissipation in SRAM cell is the sum of static and dynamic power dissipation.
where P tot is the total power dissipated, P sta is the static power dissipation, which is due to the effect of all leakage currents such as subthreshold leakage, drain induced barrier lowering, reverse current of PN junction in MOSFET(metal-oxide-semiconductor field-effect transistor), gate-induced drain leakage, punch through currents, gate oxide tunneling, and hot carrier effects [8] and P dyn is the dynamic power dissipation which is due to the short circuit current and capacitive switching current.
(1) P tot = P sta + P dyn Fig. 3 Schematic of 9 T SRAM array The dynamic power dissipation of SRAM is given in the above equation [9]. Where C is the load capacitance, which is due to the load connected in the bit lines and α is the activity factor, f is the clock frequency and V is the voltage swing at output node. So, the power dissipation is directly proportional to the frequency of operation, voltage swing and the load capacitance. In static power dissipation the subthreshold leakage current is shown below. This is one of the major contributors of static power dissipation.
I Dsub subthreshold drain current, it is the current flows from drain to source when the transistor is off or when the gate voltage is less than threshold voltage. I s0 drain current depends on transistor geometry. v off model parameter which will vary from device to device. VT volt equivalent of temperature. v gs gate to source voltage. v ds drain to source voltage. v t threshold voltage, it is the minimum voltage required to turn on the device.

From the Eq. (3), it is very clear that the subthreshold leakage increases exponentially with decreasing threshold voltage.
The short circuit power dissipation due to leakage current is given in Eq. (4), where. P sc power dissipation due to the short circuit current. t sc short circuit current duration. V DD supply voltage. I peak saturation current. f 0→1 gate switching factor.

A. Forced Sleep SVR 9 T SRAM Cell
Proposed 9 T SRAM structure is considered out of all other conventional models.
Since it has less Power Dissipation, PDP and Delay [9]. The structure is power up with DC(Direct Current) supply of 5 V. The frequency of operation is chosen as 5 MHz where the power reduction of 87% as compared to the existing structure. Similarly, a drop of 65% if the comparison is with 7Transistor SRAM cell structure. Correspondingly, in relation with 8 Transistor SRAM cell structure 87% power reduction is the yield of the suggested structure. This statistic shows by increasing number of transistors the dynamic power increases. But here leakage power is not counted [10].

B. Frequency Analysis
Constant frequencies such as 5 MHz, 2 GHz, 1 GHz are selected for transient analysis.
It is to compare and contrast 6 Transistor and 9 Transistor SRAM cells. The analysis about power dissipation was additionally added with the effect of delay and power delay .e −Vgs − VT − Vof nVt (4) P sc = t sc V DD I peak f 0→1 product on various frequencies as shown in Table 1. All these studies carried out on the proposed structure of 9 Transistor SRAM and the compared with the conventional structure. It is done for the frequencies such as 0.5 GHz, 1 GHz and 2 GHz. All the results were tabulated and graphically represented. It will help to ease the analysis part.
The performance of CMOS circuit can be closely evaluated with device parameters such as Propagation delay and energy consumed [11]. High speed of operation is suggested for improved operating frequencies. Power Delay Product is a simple evaluating parameter that helps to weigh up the total energy consumption over a period of time in a device. To obtain the battery life the designers may use these parameters. And this is how, it is easy to maintain at minimum level (Table 1).

III. Power Dissipation
When the circuit performance increases and the speed improved, it requires power to work. So, both power dissipation and speed are directly proportional. In Fig. 4 the graph shows a linear increase in power level for various frequencies in the existing 6 transistor cell structure whereas in the proposed structure it is a gradual process [12].

Fig. 4 Power Dissipation v/s Frequency
The experimentally evaluated decrease is at 1 GHz, it is 64.3% similarly at 2 GHz it is 62.2%. The power results can further be improved by implementing a layout design. This optimizes the proximity and wire issues [13]. It also helps in optimizing the area occupied by the circuit. The W/L(Width/Length) ratio of the circuit is also considered for device performance evaluation [14].

Propagation Delay
Both the frequency and propagation delay are inversely proportional as shown in Fig. 5. Therefore, it helps to enable high speed operations. The product of power and delay gives the PDP value, which is accounted as performance parameter [15].

Power Delay Product
The power dissipation of proposed cell decreases drastically while analyzing the PDP [16] factor as shown in Fig. 6. At 2 GHz the power delay product is 66.6% lesser than the conventional system. Similarly, at 1 GHz the difference is 65.8%. In high-speed applications of VLSI(Very Large-Scale Integration) the proposed 9 Transistor SRAM structure is better than the existing cells. As the number of transistors increases the effective area also increases, nevertheless at high frequencies the power dissipation decreases. This will overcome the drawbacks of the circuit.

Comparison of Arrays
The proposed structure and conventional structures were extended to an array for observing the factorization of power [17]. The basics of the array implementation as explained were carried out and obtained the simulation results as shown in Fig. 7.
The power consumed by 6 T conventional 4 × 4 array was found to be 45.2209mW. The same peripherals were used to evaluate the effect of the power dissipation of the designed cell. The proposed 9 T Forced-Sleep SVR SRAM 4 × 4 array was observed to have a power dissipation of 16.3617mW. Thus, a reduction in power occurs with the

Conclusion
Practical components like memory devices with multiple units of the same structure contribute to power consumption, delay and area issues. During technological development and evolution, the upgradation of power is significant. Here a stable 9 transistor SRAM structure is proposed and which has low power dissipation. In device fabrication, the power optimization in 9 T SRAM structure is done by controlling static and dynamic power dissipation. The results validated the core underlying concept that by optimizing the power consumption of a unique cell, the power dissipation in a whole array can be factorized. The additional voltage sources and forced sleep transistor in the pulldown path helps in lowering the leakage power of the cell. While comparing the dissipation in power, it is significantly lower in 9 Transistor SRAM than 6 Transistor SRAM. Besides, the Power Delay Product, operations based on variation in frequency and dependency of delay, power was investigated. It is concluded that the recommended structure noticeably dissipated lesser delay, power, and PDP. Consequently, the proposed system is good at high frequency operations. The 9 T array was experiential to dissipate 16.3617mW of power, which accounts for the connected peripheral circuitry as well. At 2 GHz operating frequency, a 4 × 4 array of proposed 9 T cell structure experimentally proved 62.273% of power reduction as compared with conventional system. Furthermore, 66.6033% reduction is obtained at PDP while compared with 6 Transistor SRAM structure. Thus, a highly efficient SRAM array with low power consumption and adequate performance is designed. It is suitable to operate at high frequency.

Authors Contributions
All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by AJ and JK. The first draft of the manuscript was written by AJ and the other author commented on previous versions of the manuscript. All authors read and approved the final manuscript.
Funding None.

Data Availability
The authors confirm that the data supporting the findings of this study are available within the article and its supplementary materials.

Conflict of interest
There is no conflict of interest.
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