Sensor Design and Fabrication
Figure 1a shows a schematic illustration of the integrated cantilever. The sample is placed directly onto the free end of the cantilever, which has an integrated heater for on-chip heating and cooling. Two polysilicon thermocouples are also integrated into the cantilever. The hot junction is in the sample area, while the cold junction is on the bulk silicon substrate, ensuring accurate temperature detection. To separate the high-temperature zone from the low-temperature zone, an adiabatic window is placed in the center of the cantilever to block heat transfer from the free end to the fixed end. The detection of mass changes in loaded samples is based on the resonance frequency shift of the cantilever.
As shown in Fig. 1b, we use integrated thermocouples that rely on the Seebeck effect to detect the temperature difference between hot and cold junctions30,31. According to the Seebeck effect, the output voltage of thermocouples can be expressed as31,32:
\(\begin{array}{c}V=N\left({{\alpha }}_{B}-{{\alpha }}_{A}\right)\left({T}_{hot}-{T}_{env}\right)=N\left({{\alpha }}_{B}-{{\alpha }}_{A}\right)\left({T}_{heat}-{T}_{env}+\varDelta {T}_{loading}\right)\#\left(1\right)\end{array}\) where N is the number of thermocouple pairs, αA and αB are the Seebeck coefficient values of the two materials that form the thermocouples. Thot is the temperature of the hot junction, which is composed of the temperature generated by the heater (Theat) and the temperature difference caused by the loaded sample (ΔTloading). Tenv is the temperature of the environment. Therefore, we can measure the Thot by recording the output voltage of thermocouples. To perform DTA measurement, two integrated cantilever chips with identical characteristics should be applied simultaneously under the same conditions to reduce the common mode noise and disturbances. One chip acts as a reference sensor, and the other as a test sensor for the load sample. Hence, the differential output voltage between reference and sensing can be expressed as:
$$\begin{array}{c}\varDelta V=N\left({{\alpha }}_{B}-{{\alpha }}_{A}\right)\left({\varDelta T}_{heat}+\varDelta {T}_{loading}\right)\#\left(2\right)\end{array}$$
The ΔTheat is the difference between temperatures generated by heaters, caused by differences between chips in the specifications such as the heating resistance, the heat capacity, and the thermal conductance. It may be caused by some inevitable unevenness in the deposition rate and etching rate in the fabrication process. Therefore, it can be eliminated by measuring the same chips before loading the sample under the same conditions as the baseline for formal DTA measurement. This method allows us to determine the temperature difference produced by the loaded samples.
As illustrated in Fig. 1c, we utilize the frequency change of the cantilever to quantify the mass change based on the conservation of mechanical energy at the resonant cantilever. When a small mass change occurs at the free end, and the mass change is much smaller than the effective mass of the cantilever, the relationship between the mass change and the 1st mode frequency shift can be expressed as27–29,33.
$$\begin{array}{c}\varDelta m\approx \frac{k\varDelta f}{2{\pi }^{2}{{f}_{0}}^{3}}=2{m}_{eff}\frac{\varDelta f}{{f}_{0}}\#\left(3\right)\end{array}$$
where Δm is the tiny mass change on the free end, k is the elastic coefficient of the cantilever, f0 is the resonant frequency of the cantilever before mass loading, Δf is the resonant frequency shift of the cantilever, and meff is the effective mass. The Eq. (3) shows that a small change in mass is directly proportional to the frequency change. In our chips, we can measure the mass change in real time by recording the frequency shift of the resonant cantilever, as shown in Fig. 1b.
Figure 2a shows the detailed structure of the integrated cantilever chips. The sample loading area is near the free end, where the surrounding bulk silicon is etched to reduce additional heat capacity. Molybdenum (Mo) is utilized to create microheaters for precise temperature control. The two hot junctions of the thermocouples are covered with semicircular molybdenum to ensure a uniform temperature across the sample region. For high temperature-sensitivity, we use n + and p + polysilicon to fabricate the thermocouple, which has a Seebeck coefficient significantly higher than the commonly used metals in IC fabrication13,30. In order to achieve both integrated resonance excitation and frequency readout functions, a silicon resistor is designed near the fixed end of the cantilever for electrothermal driving. Additionally, a Wheatstone bridge composed of silicon piezoresistors is fabricated near the fixed end to facilitate resonant frequency readout27,33. Due to the limitations of silicon resistors, which may not function properly at temperatures exceeding 125°C 29,34, a thermal isolation window has been designed to separate the heater and piezoresistors. This design blocks direct thermal conduction within the cantilever while improving thermal resistance from the sample area to the surrounding environment. As a result, the design of the thermal isolation window helps to increase the power responsivity of the system.
We then perform finite element simulation to model the temperature distribution of the integrated cantilever using COMSOL Multiphysics analysis software. The software modeled the thermoelectrically generated heat using the electric current interface. The element also accounts for convective heat transfer in the air atmosphere and a fixed convective heat dissipation coefficient is set to reduce simulation time without compromising accuracy. The thermal conductivity of single-crystal silicon is adjusted for temperature based on the literature35 to improve accuracy at high temperatures. Figure 2b illustrates the simulation results for the overall temperature distribution on the surface of the cantilever when the temperature at the center of the sample region reaches 500°C. Additionally, we conducted a simulation to analyze the impact of the thermal isolation window, which blocks heat transfer from the free end to the fixed end. Figure 2c presents the effect of the thermal isolation window on the temperature distribution along the center axis of the cantilever. With the isolation window, the temperature around the Wheatstone bridge remains below 65°C as the temperature at the free end exceeds 500°C. In contrast, without the isolation window, the temperature around the Wheatstone bridge increases to 160°C, which could lead to p-n junction leakage. The simulation results demonstrate effective thermal isolation between the free and fixed ends, protecting the resonant excitation and readout silicon resistors at high operating temperatures. In Fig. 2d, the temperature distribution of the sample loading region along the horizontal axis is shown at different heating voltages. The simulation results indicate a uniform temperature distribution in the center of the sample loading region, with a variation of within ± 1%.
Our chips are produced on 4-inch (100) SOI wafers, enabling precise control over the cantilever layer thickness of 3 µm, a handle layer thickness of 500 µm, and a box layer thickness of 700 nm. The detailed fabrication process is shown in Fig. 3: (a) The thermal SiO2 of 350nm is fabricated through a heating oxidation furnace. After photolithography and RIE etch of SiO2, a pool is defined by KOH wet etching for the sample loading region. (b) The silicon resistors of resonant excitation and readout resistors (Wheatstone bridge) are defined by photolithography, ion-implantation, and diffusion. (c-d) After depositing 200nm of SiNx and 500nm of polysilicon films by LPCVD, the main part of polysilicon thermocouples is fabricated through ion implantation, diffusion, and RIE sequentially. A 300nm SiNx film is then deposited to protect the thermocouples. (e) After etching the connection window of the polysilicon thermocouple and silicon resistors, the Mo films are patterned using the lift-off process to create microheaters and connect the thermocouples. Subsequently, the Al films are patterned using the lift-off process to establish electrical connections for the silicon resistors. (f) Depositing a 200nm PECVD Si3N4 layer provides protection against oxidation and electrical isolation. (g) A RIE process of dielectric layers is followed by DRIE of the device layer and RIE of the box layer to form the shape of the resonant cantilever. (h) The handle layer is removed from the back side using a DRIE process, thus releasing the cantilever.
Characterization of the Integrated Cantilever Chips
Figure 4a depicts the morphological image of the manufactured resonant cantilevers. The cantilever measures 340 µm in length, 190 µm in width, and 3 µm in thickness. The sample loading area has a diameter of 60 µm, and the thermal isolation window measures 100 µm × 90 µm. The SEM image of the cantilever in Fig. 4a clearly reveals the structure and morphology of the integrated thermocouple, heater, resonant excitation/readout resistor, and sample loading area. Figure 4b illustrates the wafer-level fabrication of the cantilever chips on a 4-inch SOI wafer. Figure 4c schematically depicts the test system for TGA and DTA measurements. The resonant excitation and readout resistors of the sensing chip are connected to a phase-locked-loop (PLL) circuit for tracking the resonant frequency. The output voltage from the thermocouples and integrated heaters of both chips is connected to a signal readout and heater drive circuit, which records and controls the temperature of the sample region. Both circuits are linked to a computer for data recording and further processing.
The temperature dependence of the chip was first assessed by measuring the temperatures of the hot junction at various heating voltages using a non-contact infrared thermal imager with a spatial resolution of 20 µm. Simultaneously, the test system recorded the output voltage of the thermocouples. Figure 5a shows the measured and simulated temperatures of the sample loading area as a function of the heating voltage, and the agreement is very good, indicating that our simulation is reliable. The sample region can be heated up to 530℃ under a heating voltage of 6.2V. Meanwhile, Fig. 5b shows the corresponding relationship between the output voltage and heating power of the seven chips. The average power response of each chip is 6.1V/W, which is three orders of magnitude higher than that of traditional instruments (generally in the mV/W level)16,17, and the relative standard deviation is only 3%, indicating strong consistency between different chips. In Fig. 5c, the output voltage of thermocouples is shown for different measured temperatures. The output voltage demonstrates a linear response to the temperature, with a high-temperature responsivity of 0.73mV/K. The root-mean-square (rms) voltage noise of the MEMS thermocouples can be expressed as follows:
$$\begin{array}{c}{V}_{noise,rms}=\sqrt{4{k}_{B}TRB}\#\left(4\right)\end{array}$$
where kB is the Boltzmann’s constant, T is the room temperature, R is the thermocouples resistance (10kΩ), and B is the system bandwidth (400Hz) 19,20. According to Eq. (3), we can have a rms voltage noise of 0.26µV for our chips. Therefore, we can calculate a noise equivalent temperature (NET) of 2.8mK, based on the 8×V noise, rms, and temperature responsivity20. We also measure the change in heating resistance with the working temperature, as illustrated in Fig. 5d, indicating a TCR (temperature coefficient of resistance) of 0.0014/K.
Then, the mass-sensing properties of the fabricated cantilevers are calibrated. A flowing DC-biased AC is applied to the excitation resistor, and the Wheatstone bridge is also connected to the PLL interface circuit. In this way, we can measure the real-time frequency shift. The resonant frequency of our cantilever is approximately 35 kHz, with a Q factor of 190. To calibrate the mass sensitivity of our cantilever, we measure the resonant frequency of the cantilever before and after placing a standard polystyrene (PS) sphere on the sample region, as illustrated in Fig. 6a-b. The diameter of the standard PS sphere is 25 µm, and the density is 1.05 g/cm3. A resonant frequency change of 399 Hz is measured after loading the standard PS sphere, which leads to a mass responsivity of 0.090 Hz/pg for the cantilever. The noise floor of the frequency signal is approximately 0.5 Hz, leading to a mass resolution of 5.5 pg. Therefore, our chips can conduct thermogravimetric analysis with ng-level samples. When the sample region of the cantilever is heated from room temperature to 400℃, only a slight frequency shift of 50 Hz is measured, equivalent to a mass change of 0.56 ng.
DTA Measurement Using Integrated Cantilever Chips
Metal standards with a fixed melting point are commonly used to calibrate DTA measurements. In this work, we have selected indium (In) and tin (Sn) standards to validate our DTA measurement performance. As mentioned above, two chips are used simultaneously in DTA measurement. One chip contains a sample, while the other is left empty. The DTA measurements are carried out at various heating rates in an air atmosphere. Because our cantilevers are small, we place them under a microscope to observe the morphological changes of the samples in situ during the DTA measurements.
We first measure the melting process of In and Sn at a heating rate of 10°C/s. The results are shown in Fig. 7a-b. We can observe the sharp heat absorption peak caused by the melting process. The video in Supporting Material S1 and the insets in Fig. 7a show the in situ optical images of the indium melting process. The indium undergoes a noticeable morphological change after reaching its melting point. Based on the heat absorption peak in the measured DTA curve, we can calculate the melting point of the metal using our chips36. The measured melting point of indium is 157.7°C, which is only 1.1°C higher than the standard value of 156.5°C in literature36,37. As for tin, the melting point is measured as 231.7℃, only 0.2℃ smaller than the standard valve (231.9℃)37. The results presented in Fig. 8a-b confirm the temperature accuracy of our chips.
We further test the indium melting and solidification process at different heating and cooling rates from 1°C /s to 200°C /s. The heat absorption and release during melting and solidification processes induce sharp peaks in the DTA curves, as shown in Fig. 7c. As the rate of temperature rise and fall increases, the DTA signal becomes larger, thereby facilitating the measurement of small heat absorption or exothermic processes. We also calculate the melting point of indium at different heating rates, as shown in Fig. 7d. The melting point at 200°C/s exhibits only a 5°C difference compared to the melting point at 1°C /s. The results demonstrate that the chip exhibits small thermal hysteresis even at rapid temperature changes.