An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

doi:10.21203/rs.3.rs-4696885/v1

Download PDF

Research Article

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

https://doi.org/10.21203/rs.3.rs-4696885/v1

This work is licensed under a CC BY 4.0 License

You are reading this latest preprint version

Shallow Trench Isolation laterally diffused metal oxide semiconductor (STI LDMOS) is a crucial device for power integrated circuits. In this article, a novel framework that integrates an optimal objective function, Bayesian Optimization (BO) algorithm and Deep Neural Network (DNN) model is proposed to fully realize automatic and optimal design of STI LDMOS devices. On the one hand, given the structure of device, the DNN model in the proposed method can provide the ultra-fast and high-accurate performance estimation including breakdown voltage (BV) and specific on-resistance (R_onsp). The experimental results demonstrate 98.68% prediction accuracy in average for both BV and R_onsp, higher than that of other machine learning (ML) algorithms. On the other hand, to target the specified value of BV and R_onsp, the proposed framework can fully automatically and optimally design the precise device structure that simultaneously achieves the target performance with the optimal figure-of-merit (FOM) of device. Compared to Technology Computer Aided Design (TCAD), there is only 0.002% error in FOM and 2.83% average error in BV and R_onsp. Moreover, the proposed framework is 4000 times more efficient than other conventional frameworks. Thus, this research provides experimental groundwork for constructing an automatic design framework for LDMOS device and opens up new opportunities for accelerating the development of LDMOS device in the future.

Laterally diffused metal oxide semiconductor

Machine learning

Bayesian optimization

Deep neural networks

Automatic design

Laterally diffused metal oxide semiconductor (LDMOS) devices have been widely adopted in power integrated circuits due to its high Breakdown Voltage (BV) and low specific on-resistance (R_onsp) [1–5]. It is the key determinant of the performance, cost, and integration level of power integrated circuits [6, 7]. Currently, the conventional device design approach relies on simulation tools such as Sentaurus, Medici, Silvaco and so on. These simulation tools acquire the device electrical characteristics by solving the physical equations such as Poisson equation, Continuity equation and Transport equation of electrons and holes at the set mesh point [8]. However, the simulation results do not meet the expectations to some extent, it must require significant human intervention and configuration that spend great efforts on the remodeling and optimization. It is time-consuming and cumbersome.

On the other hand, in the development of LDMOS devices, the most crucial performance metrics are BV and R_onsp. There exists a ‘silicon limit’ constraint relationship between these two electrical performances, which increases the difficulty and cost of development [9–13]. In consequence, multiple parameter adjustments and iterations are essential for optimizing device performance, which in turn substantially raise manufacturing costs. Besides, capturing the influence of multiple processes on the performance of variable devices through manual methodologies presents significant challenges. Therefore, the traditional development method cannot satisfy the requirements of the widely applied LDMOS devices.

Recently, Machine Learning (ML) algorithms exhibit great ability to efficiently accelerate device simulation and design. For example, Carrillo-Nunez et al. investigated the possibility to replace numerical time-consuming device simulations with a multi-layer neural network [14]. Mehta et al. demonstrated the possibility of predicting full transistor current-voltage and capacitance-voltage curves using trained prediction model based on Deep Neural Network (DNN) [15]. Han et al. proposed to use a neural network to learn an approximate solution for desired bias conditions to accelerate the simulation [16]. Wang et al. present a novel method of predicting and optimizing the performance of the existing TFETs by using deep learning to accelerate the device design [17]. Chen et al. proposed an automated structural design method for SOI lateral power device based on optimization algorithm [18]. These research firstly demonstrate the significant advantage of machine learning methods in device simulation, while also proving the possibility of using optimization algorithms to automatically design devices. However, there is no research that designs an optimal objective function to drive the optimization algorithm to iterate more diligently, to construct devices that better meet the design specifications. In the traditional device development process, device structure adjustments are performed not only to ensure the device satisfies fundamental performance requirements, but also to iteratively optimize the device to attain the optimal figure of merit (FOM). Hence, for an automated design framework, designing devices that can simultaneously exhibit target performance and optimal FOM is the most desired outcome after applying ML algorithms. Furthermore, there is also no research utilizing ML algorithms to accelerate and automate the design of Shallow Trench Isolation (STI) LDMOS device.

This research proposes an ultra-fast and extremely precise framework to design STI LDMOS device automatically and optimally by the integration of an optimal objective function, Bayesian Optimization (BO) algorithm and DNN model. Firstly, a higher prediction accuracy model for STI LDMOS based on DNN algorithm. By inputting the structure parameters of device, the DNN model can effectively output BV and R_onsp with precision of 98.68%. Then, an optimal objective function is defined, which includes two parts: (1) Optimal Function (OF): driving the device structure to attain the optimal FOM; (2) Target Function (TF): driving the device structure that exhibits target performance. By integrating this objective function, not only can the designed device meet the specified device performance, but also achieve the optimal FOM. Compared to TCAD, there is only 0.002% error on FOM and 2.83% average error on BV and R_onsp performances. The entire processing time of the proposed framework for the automated design is less than 4 minutes.

2.1 A TCAD Simulation and Electrical Characteristics of Device

Device Structure and TCAD Simulation

Figure 1 shows a schematic diagram of the device structure of STI LDMOS. It includes five electrodes on the device. The constant doping profiles and Gaussian doping profiles are simultaneously defined in the device. The constant p-type doping background is used in the substrate. There is n + Gaussian doping profiles of source/drain and p + Gaussian doping profiles of bulk/psub placing on the device surface. Besides these Gaussian doping profiles, it exists two more extensive distributed doping profiles: n + Gaussian doping profiles of n-type drift region and p + Gaussian doping profiles of p-type body (pbody) region. There are two STI regions by deposit process to enhance BV.

In Table 1, nine parameters listed are used as the input parameters for TCAD simulations. They include: (1) the peak doping concentration of the pbody Gaussian doping (Npbody.p), (2) the doping concentration in specific depth of the pbody Gaussian doping (Npbody.s), (3) the length of the overlap region of pbody to gate (Lpog), (4) the peak doping concentration of the ndrift Gaussian doping (Nndrift.p), (5) the doping concentration in specific depth of the ndrift Gaussian doping (Nndrift.s), (6) the length of the extension region of ndrift beyond STI (Lnes), (7) the width of STI (Lsti.w), (8) the depth of STI (Lsti.d), (9) the length of the overlap region of STI to gate (Lsog). These structure parameters determine the doping distribution and the size of the pbody region, ndrift region, and STI region. The parameter sets were randomly generated by Python script, which size is 2578. Next, by inputting parameter sets, TCAD simulation tool can output performance sets. The commercial device simulator Sentaurus is used for device modeling and performance simulation [8].

Electrical Characteristics of Device

BV represents the maximum voltage between the source and drain that the device can sustain without experiencing avalanche breakdown when it is in off state. The $\:{I}_{DS}-{V}_{DS}$ measurement is performed and $\:{V}_{DS}$ is ramped up to extract the maximum $\:{V}_{DS}$ when the TCAD no longer converges:

$$\:\begin{array}{c}BV={max}\left({V}_{DS}\right),\:{V}_{GS}={V}_{BS}={V}_{SS}=0V\#\left(1\right)\end{array}$$

We calculate the specific on-state resistance by

$$\:\begin{array}{c}{R}_{onsp}={R}_{onds}\times\:AREA\#\left(2\right)\#\#\end{array}$$

Where AREA is half-pitch times a unit length (default value is 1 $\:\mu\:m$ on the z-direction since 2D simulations is performed) and

$$\:\begin{array}{c}{R}_{onds}=\frac{{V}_{DS}}{{I}_{DS}}\:({when\:V}_{GS}=5V,{V}_{DS}=0.1V)\#\left(3\right)\#\#\end{array}$$

Finally, the FOM is the most important metric in this study, equaling

$$\:\begin{array}{c}FOM=\:\frac{{BV}^{2}}{{R}_{on,sp}}\#\left(4\right)\end{array}$$

The FOM is one of the most well-known metrics for evaluating the performance of power devices. A higher FOM indicates that the device has characteristics closer to an ideal switch. Researchers can use this FOM to gauge the performance of a power device.

Table 1

The description and bound of device structure parameters
Symbol(units)	Description	Bound
N_pbody.p (cm^− 3)	The peak value of the pbody Gaussian doping	[1.4e17, 2.6e17]
N_pbody.s (cm^− 3)	The value of the pbody Gaussian doping in specific depth	[0.7e15, 1.3e15]
L_pog (um)	The length of the overlap region of pbody to gate	[0.07, 0.13]
N_ndrift.p (cm^− 3)	The peak value of the ndrift Gaussian doping	[0.7e17, 1.3e17]
N_ndrift.s (cm^− 3)	The value of the ndrift Gaussian doping in specific depth	[1.4e16, 2.6e16]
L_nes (um)	The length of the extension region of ndrift beyond STI	[0.375, 0.715]
L_sti.w (um)	The width of STI	[1.4, 2.6]
L_sti.d (um)	The depth of STI	[0.14, 0.26]
L_sog (um)	The length of the overlap region of STI to gate	[0.7, 1.3]

2.2 Automatic Design Framework

Deep Neural Network Algorithm

Firstly, a total of 2578 samples in the dataset prepared for training the DNN model is obtained from the commercial device simulator Sentaurus which is presented in above session. The input features contain nine structural parameters listed in Table 1. The output features contain the BV and R_onsp, whose density distributions are illustrated in Fig. 2. The dataset is divided into 8:2 for training dataset and testing dataset, respectively. It is obviously that there are different ranges and magnitudes of different input features. Note that the length Lpog is only tenth of micron, while the concentration Npbody.p is more than 1e17, which greatly affects the accuracy and generalization ability of the DNN model. Thus, the dataset needs to be normalized before training so that the values of each input feature will be scaled to the range of 0 to 1.

Secondly, the DNN algorithm is inspired by structure of mammalian visual system that contains many layers of neural network [19]. Different numbers and weights of neurons and diverse activation functions will result in different relationship functions between input and output. The construction of the proposed DNN prediction model can be divided into two parts: the network design and the model training. In fact, continuous adjustment of the neural network structure and training strategy based on the training and validation results are required for the construction of neural networks. Figure 3 shows the overview of the proposed DNN model. The model is a regression network for BV and R_onsp prediction with five hidden layers, and the neurons in each layer are 8, 32, 24, 16, 12, 8 and 2 respectively. This layer structure is verified for achieving highest accuracy and well optimized for STI LDMOS design to minimize the computational cost. Comparing among all these activation functions, the Relu function is selected and used for the input and hidden layers of all networks. During the training process, regression task used the mean absolute percentage error (MAPE) as the loss function, which is presented in Eq. (5).

$$\:\begin{array}{c}Loss\:Function=\frac{1}{2n}{\sum\:}_{i=1}^{n}\left(\left|\frac{Bvdss-\widehat{Bvdss}}{\widehat{Bvdss}}\right|+\left|\frac{Ronsp-\widehat{Ronsp}}{\widehat{Ronsp}}\right|\right)\times\:100\%\#\left(5\right)\end{array}$$

Bayesian Optimization Algorithm

The two critical modules (surrogate model and acquisition function) constitute BO algorithm. The surrogate model is a statistical model attempting to replicate the objective function and the acquisition function is used to decide where to sample the next data point [20]. In the proposed framework, the Gaussian Process Regression (GPR) algorithm is used as surrogate model and the Expected Improvement (EI), Probability of Improvement (PI) and Bayesian Confidence Bound (UCB) are utilized in acquisition function.

Optimal Objective Function

An optimal objective function, which includes two parts: OF(x) and TF(x), is defined in Eq. (6). OF(x) represents the optimal term of the optimal objective function, TF(x) denotes the target term of the optimal objective function. As shown in Eq. (7), the above nine structure parameters of STI LDMOS device are defined as independent variable.

$$\:\begin{array}{c}O\left(x\right)=OF\left(x\right)+\:TF\left(x\right)\#\left(6\right)\end{array}$$

$$\:\begin{array}{c}x={\left\{{N}_{pbody.p},{N}_{pbody.s},\dots\:,Lsti.d,{L}_{sog}\right\}}^{T}\#\left(7\right)\end{array}$$

As defined in Eq. (8), the optimal term OF(x) represents the FOM, where BV(x) and R_onsp(x) denote the corresponding performance values of the device constructed in each iteration of the automatic design framework. This function measures the comprehensive performance of the designed device. A higher value indicates that the device can achieve a higher BV under a lower R_onsp condition. Therefore, OF(x) will drive the automatic design framework to further iterate and produce the optimal result when current performance of constructed device meets the target performance.

$$\:\begin{array}{c}OF\left(x\right)=FOM\left(x\right)=\frac{{BV\left(x\right)}^{2}}{{R}_{onsp}\left(x\right)}\#\left(8\right)\end{array}$$

The target term TF(x), defined in Eq. (9), consists of two parts: P₁(x) and P₂(x). P₁(x) is the performance target function for BV, while P₂(x) is the performance target function for R_onsp. The constant terms $\:{\text{B}\text{V}}^{\text{t}}$ and $\:{\text{R}}_{\text{o}\text{n}\text{s}\text{p}}^{\text{t}}$ are included in these functions, respectively, which represent the target performance values that the designed device should achieve. By substituting Eqs. (10) and (11) into Eq. (9), the expanded form of TF(x) is shown in Eq. (12). This function indicates whether the designed device has reached the basic target performance values. The P₁(x) term being greater than zero indicates that the target BV has been achieved, while the P₂(x) term being greater than zero indicates the target R_onsp has been reached. Consequently, TF(x) drives the automatic design framework to construct devices that meet the target performance.

$$\:\begin{array}{c}TF\left(x\right)=\:{P}_{1}\left(x\right)+{P}_{2}\left(x\right)\#\left(9\right)\end{array}$$

$$\:\begin{array}{c}{P}_{1}\left(x\right)=\left(BV\left(x\right)-{BV}^{t}\right)\#\left(10\right)\end{array}$$

$$\:\begin{array}{c}{P}_{2}\left(x\right)=\left({\:R}_{onsp}^{t}-{R}_{onsp}\left(x\right)\right)\#\left(11\right)\end{array}$$

$$\:\begin{array}{c}TF\left(x\right)=\:\left(BV\left(x\right)-{BV}^{t}\right)+\left({\:R}_{onsp}^{t}-{R}_{onsp}\left(x\right)\right)\#\left(12\right)\end{array}$$

Architecture of proposed Automatic Design Framework

Figure 4 shows the flow diagram of automatic design flow. Firstly, the target values of BV and R_onsp are specified to automatic design framework. Meanwhile, the two constants in the target term TF(x) of the objective function are determined. This objective function represents the goal of the automatic design framework, which can be expressed mathematically as follows:

$$\:\begin{array}{c}O\left(x\right)=\frac{{BV\left(x\right)}^{2}}{{R}_{onsp}\left(x\right)}+\left(BV\left(x\right)-{BV}^{t}\right)+\left({\:R}_{onsp}^{t}-{R}_{onsp}\left(x\right)\right)\#\left(13\right)\end{array}$$

$$\:\begin{array}{c}Goal=argmax\left(Objective\:Function\right)\#\left(14\right)\end{array}$$

The automatic design framework will iterate to find maximum of the objective function. Hence, the goal of this automatic design framework will enable to ultimately obtain a device structure whose achievable performance can even surpass the target performance, while also exhibiting the optimal overall performance. This framework will start from a device with nine initial random parameters. The FOM, BV and R_onsp of device are calculated by using the trained DNN model for each iteration. It run five hundred iterations optimization in BO process, which is experimentally proved to be enough to achieve high accuracy with the training dataset. After each iteration, the optimal objective function will drive the optimization algorithm generates new nine structure parameters $\:{\varvec{x}}_{\varvec{i}+1}$, and the DNN model calculates the FOM, BV and R_onsp for the next device. When the iteration counter equal five hundred, the automatic design framework will output the maximum of FOM in specified target boundary of BV and R_onsp and corresponding structure parameters.

3.1 Performance analysis of proposed DNN Model

Model performance in dataset

Figure 5 and Fig. 6a shows MAPE of the BV and R_onsp prediction for the training and test sets during the model training process. The train loss and test loss represent the model performance of different epoch. Especially, test error can be applied to assess the application quality of the trained model. The prediction error gradually decreases with the training epoch until convergence. Besides, the DNN model prediction performance of BV and R_onsp is illustrated in Fig. 6 (a) and (b). The x-axis represents the BV or R_onsp obtained by TCAD simulation, and the y-axis represents the BV or R_onsp value predicted by the model. The distance of the dots from the diagonal line illustrates the accuracy of the prediction results. As shown in the figure clearly, most of the dots are focused on the diagonal attachment. In fact, there is only an average prediction error of 2.21% on BV and 0.43% on R_onsp, which means an average performance prediction error of 1.32%. Compared to the previous work [21], the proposed DNN model use less than 20% of their neuron count, and the performance prediction error decreased from 3.81–1.32%. The results indicate the proposed DNN model for device predication owns higher accuracy with less computational cost.

Table 2

Experimental results comparison about DNN with different ML algorithms (Corresponding Calculation Equations listed in Eq. (15) and Eq. (16))
Algorithm	DNN	Linear Regression	Gradient Boosting	SVR	Random Forest
MAPE	1.32	10.83	6.36	7.89	7.62
PA	98.68	89.17	93.64	92.11	92.38

Performance comparisons: proposed DNN vs. traditional ML algorithms

As shown in Table 2 and Fig. 7, other ML algorithms for BV and R_onsp prediction and the comparison of these algorithms are illustrated. It is obvious that the error of the proposed DNN algorithm (with an error of 1.32%) is significantly lower than that of other traditional ML algorithms. The DNN algorithm has an excellent ability to predict BV and R_onsp precisely.

$$\:\begin{array}{c}Mean\:Absolute\:Percentage\:Error\left(MAPE\right)=\left|\frac{{Y}_{pred}-{Y}_{true}}{{Y}_{true}}\right|\times\:100\%\#\left(15\right)\end{array}$$

$$\:\begin{array}{c}Prediction\:Accuary\left(PA\right)=1-MAPE\#\left(16\right)\end{array}$$

Performance comparisons: proposed DNN vs. TCAD

Our proposed model is implemented in Python on a Linux server with 3.5GHz CPU. We use Pytorch library for the DNN model. TCAD simulation also run in this server. The contrast of TCAD simulation and DNN calculation results using randomly selected structure parameters are illustrated in Fig. 8.The comparison of the executed time for performance prediction between DNN model and TCAD is listed in Table 3. The DNN model only takes 0.0039 seconds to execute, while the TCAD tool requires 1500 seconds. The DNN model runs several hundred thousand times faster than TCAD simulation. Therefore, for the development of STI LDMOS devices, using DNN model instead of TCAD simulation can significantly enhance research efficiency and greatly reduce development costs.

Table 3

Executed time comparison between DNN model and TCAD
Algorithm	DNN	Linear Regression
MAPE	1.32	10.83
PA	98.68	89.17

3.2 Performance analysis of proposed design framework

In this section, the automatic design framework is constructed to automatically design device structure of STI LDMOS, which significantly accelerates the development process. The framework focuses on optimizing device structures using an optimal objective function. BO algorithm is utilized to iteratively generate new structures, which are used by DNN model to evaluate the optimal FOM, BV and R_onsp values. In all, the automatic design framework is used to search for the optimal device structure.

Table 4

Executed time comparison of different frameworks
Method	BO + DNN	BO + TCAD
Time	190s	At least 750000s

Different operation modes of proposed automatic design framework

Figure 9 illustrates different automatic design frameworks. In Fig. 9 (a), the proposed automatic design framework that integrates BO with DNN model, while in Fig. 9 (b), it’s traditional BO coupled with TCAD simulation tool [22]. The central advantage of proposed framework lies in the speed improvement. As shown in Table 4, after iterating 500 times, the former takes only 190 seconds, whereas the latter requires at least 750,000 seconds. The automatic design speed of the former is nearly 4,000 times faster. Therefore, there is a significant advantage in ultra-fast speed for our proposed automatic design framework. This advantage mainly comes from using ML algorithms with DNN performance prediction model to replace TCAD Simulation Tool. It allows for much faster exploration of the device structure parameter space and optimization of STI LDMOS devices.

The effectivity of target function with TF(x)

The target value of BV is specified to be 50V, while the target value of R_onsp is specified to be 25 $\:m{\Omega\:}\bullet\:{mm}^{2}$, the optimal FOM, BV and R_onsp with the correspond structure parameters are eventually generated by the proposed framework. In Table 5, the results with the optimal objective function integrating both OF(x) and TF(x) are compared to those with only OF(x). It’s illustrated that the desired results are better obtained through the proposed automatic design framework with optimal objective function integrated OF(x) and TF(x) in Fig. 10. Although the automatic design framework is 2x slower after adding target term TF(x), it still cost only 190 seconds. This framework can also output optimal FOM, BV, and R_onsp when the objective function only integrates OF(x). Nonetheless, the BV and R_onsp with optimal FOM of this case cannot satisfy the target requirement of STI LDMOS. Hence, when the objective function integrated not only optimal term OF(x) but also target term TF(x), the automatic design framework will get another constraint to drive it to optimize device structures. As shown in Fig. 9. a), the space below the two yellow dotted lines is constrained space defined by OF(x). And the automatic design framework will spare no effort to construct device performance located in this space. Therefore, device design requirements can only be met if the objective function integrates target term TF(x).

Table 5

Outcome of different objective function
Objective Function	OF(x) + TF(x)	OF(x)
Time(s)	190	82
FOM (kW/mm2)	145.8	145.08
BV(V)	59.88	75.95
R_onsp ($\:m{\Omega\:}\bullet\:{mm}^{2}$)	24.60	39.76

Table 6

Outcome of different objective function.
Objective Function	OF(x) + TF(x)	Eq. (17)
Time(s)	190	82
FOM (kW/mm2)	145.8	145.08
BV(V)	59.88	75.95
R_onsp ($\:m{\Omega\:}\bullet\:{mm}^{2}$)	24.60	39.76

The effectivity of objective function with OF(x)

Uniformly, the target value of BV is specified to be 50V, while the target value of R_onsp is specified to be 25 $\:m{\Omega\:}\bullet\:{mm}^{2}$. In Table 6 and Fig. 11, the results are compared between proposed optimal objective function and Eq. (17) in previous research [18]. The devices constructed by the automatic design framework that integrates the proposed optimal objective function demonstrate superior performance. Not only do they achieve the target performance values, but they consistently surpass these targets. Furthermore, the overall performance of constructed devices, considering FOM, is optimal. The automatic design framework integrating Eq. (17) can only generate approximately approach target performance.

In the objective function of Eq. (17), this function also specifies the target values of BV and R_onsp, similar to the target term TF(x) in the proposed optimal objective function, which aims to drive the automatic design framework to construct devices that meet the target performance values. However, for Eq. (17), its gradients in the BV and R_onsp directions are shown in Eqs. (18) and (19). As illustrated in Fig. 11.b), when BV is greater than $\:{\text{B}\text{V}}^{\text{t}}$, Eq. (18) is negative, its gradient direction is the arrow direction of the yellow dashed line 2. This direction is the iterative update direction of the automatic design framework, indicating that the automatic design framework needs to iteratively construct devices with smaller BV performance values. When BV is less than $\:{\text{B}\text{V}}^{\text{t}}$, i.e., Eq. (18) is positive, its gradient direction is the direction of the yellow dashed line 4. This direction is the iterative update direction of the automatic design framework, indicating that the automatic design framework needs to iteratively construct devices with larger BV performance values. The same applies to R_onsp. In summary, from the perspective of gradient direction, Eq. (17) will cause the automatic design framework to iteratively move towards the point (50, 25), and the best outcome it can iterate out can only meet the target performance values.

$$\:\begin{array}{c}r\left(x\right)=-\left\{\begin{array}{c}{\:\:\left(\frac{\left|{BV}^{t}-BV\left(x\right)\right|\times\:100}{{BV}^{t}}\right)}^{2}\:\\\:{+\left(\frac{\left|{R}_{onsp}^{t}-{R}_{onsp}\left(x\right)\right|\times\:100}{{R}_{onsp}^{t}}\right)}^{2}\end{array}\right\}\#\left(17\right)\end{array}$$

$$\:\begin{array}{c}\frac{\partial\:r\left(x\right)}{\partial\:BV\left(x\right)}=\frac{\left({BV}^{t}-BV\left(x\right)\right)\times\:\left(20000\right)}{{\left({BV}^{t}\right)}^{2}}\#\left(18\right)\end{array}$$

$$\:\begin{array}{c}\frac{\partial\:r\left(x\right)}{\partial\:{R}_{onsp}\left(x\right)}=\frac{\left({R}_{onsp}^{t}-{R}_{onsp}\left(x\right)\right)\times\:\left(20000\right)}{{\left({R}_{onsp}^{t}\right)}^{2}}\#\left(19\right)\end{array}$$

The gradient of the proposed optimal objective function, as shown in Eq. (20) and Fig. 10a), is always positive in the BV direction, corresponding to the yellow dashed line 1, and always negative in the R_onsp direction, corresponding to the yellow dashed line 2. As shown in Eq. (22), it is the sum of the gradient vectors of Eq. (20) and Eq. (21), which is also the same direction as the yellow dashed line 3. And it also represents the overall iterative optimization direction of the automatic design framework. Hence, the proposed objective function will drive the automatic design framework to iteratively optimize the device structure to achieve BV higher than the target value and R_onsp lower than the target value. When the performance of the constructed device reaches the target performance, the optimization does not stop. The optimal term OF(x) will drive the automatic design framework to continue iterating, optimizing the device structure towards the direction of obtaining larger FOM values.

$$\:\begin{array}{c}\frac{\partial\:O\left(x\right)}{\partial\:BV\left(x\right)}=\frac{2BV\left(x\right)}{{R}_{onsp}\left(x\right)}+1\#\left(20\right)\end{array}$$

$$\:\begin{array}{c}\frac{\partial\:O\left(x\right)}{\partial\:{R}_{onsp}\left(x\right)}=-\frac{{BV\left(x\right)}^{2}}{{{R}_{onsp}\left(x\right)}^{2}}-1\#\left(21\right)\end{array}$$

$$\:\begin{array}{c}g\left(x\right)=\sqrt{{\left(\frac{\partial\:O\left(x\right)}{\partial\:BV\left(x\right)}\right)}^{2}+{\left(\frac{\partial\:O\left(x\right)}{\partial\:{R}_{onsp}\left(x\right)}\right)}^{2}}\#\left(22\right)\end{array}$$

TCAD-based Verification of design results using the proposed framework

Firstly, the boundary of BV was specified to be greater than 50V and the boundary of R_onsp was specified to be less than 25 $\:m{\Omega\:}\bullet\:{mm}^{2}$. The framework output optimal FOM, BV and R_onsp listed in Table 8 with corresponding structure parameters listed in Table 7. And the correspond structure parameters are input back to TCAD simulation tool. Figure 12 and Fig. 13 is illustrated the STI LDMOS device simulation diagram in TCAD using the correspond structure parameters generated by automatic design framework. Table 8 also compare the results between automatic design framework and TCAD simulation tool. It is obvious that the results of the framework are extremely close to TCAD simulation tool, which are only 0.002% error of FOM, 1.98% error of BV and 3.68% error of R_onsp. Therefore, the device designed by proposed automatic design framework is extremely precise.

Table 7

The optimal device structure parameters.
Structure parameters
N_pbody.p(cm^− 3)	N_pbody.s(cm^− 3)	L_pog(um)	N_ndrift.p(cm^− 3)	N_ndrift.s(cm^− 3)	L_nes(um)	L_sti.w(um)	L_sti.d(um)	L_sog(um)
2.314e17	7.838e14	7.606e-1	7.412e16	2.459e16	3.886e-1	1.856	1.829e-1	9.962e-1

Table 8

The comparison of Automatic Design Framework and TCAD.
Method	Automatic Design Framework	TCAD	Error
FOM	145.8	146.12	0.002%
BV	59.88	61.09	1.98%
R_onsp	24.60	25.54	3.68%

In this article, an ultra-fast and precise automatic design framework of STI LDMOS device is proposed. It combines an optimal objective function, BO algorithm and DNN prediction model. Given the device structure parameters, the DNN prediction model can ultra-fast output the high accuracy performance including BV and R_onsp. The first experimental results show that the DNN model achieves average 98.68% performance prediction accuracy. Specified the target values of BV and R_onsp, the framework can fully automatically design the device structure that can satisfy the design constraints. The second experimental results demonstrate that the proposed framework is capable of optimizing the STI LDMOS device structure to obtain extremely precise designs. Moreover, the proposed framework is 4000 times more efficient than other frameworks. Thus, the proposed automatic design framework can significantly accelerate the development of STI LDMOS device compared to the traditional manual design flow.

Funding

This work was supported in part by the National Key R&D Program of China under Grant 2022YFF0605800, in part by the Zhejiang Provincial “Jianbing” “Lingyan” Research and Development Program of China under Grant 2024C01002 and 2022C01063, and in part by the National Natural Science Foundation of China under Grant 62204217. (Corresponding authors: Yitao Ma; Kai Xu)

Competing Interests

The authors have no relevant financial or non-financial interests to disclose.

Author Contributes

Chenggang Xu led the study and was responsible for the overall conceptualization and design of the research. Hongyu Tang, Yuxuan Zhu, Yue Cheng, Xuanzhi Jin, and Dawei Gao contributed to data collection, analysis, and interpretation of the results. Chenggang Xu, Yitao Ma and Kai Xu drafted the initial manuscript. All authors reviewed and approved the final manuscript. Yitao Ma and Kai Xu provided critical revisions and supervised the project.

Data Availability

Enquiries about data availability should be directed to the authors.

Dong, Z., Duan, B., Fu, C., Guo, H., Cao, Z., & Yang, Y. (2018). Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology. IEEE Electron Device Letters, 39(9), 1358–1361. https://doi.org/10.1109/LED.2018.2854417
Yao, J., Sun, M., Xu, T., Liu, X., Li, M., Chen, J., et al. (2023). SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions. IEEE Transactions on Electron Devices, 70(5), 2204–2209. https://doi.org/10.1109/TED.2023.3262224
Erlbacher, T. (2014). Lateral Power Transistors in Integrated Circuits. Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-00500-3
Qiao, M., Hu, X., Wen, H., Wang, M., Luo, B., Luo, X., et al. (2011). A novel substrate-assisted RESURF technology for small curvature radius junction. In 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs (pp. 16–19). Presented at the IC’s (ISPSD), San Diego, CA, USA: IEEE. https://doi.org/10.1109/ISPSD.2011.5890779
Tao Liang, Yitao He, Lu Lu, Ming Qiao, & Bo Zhang. (2016). 200-V high-side thick-layer-SOI field PLDMOS for HV switching IC. In 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia) (pp. 3116–3119). Presented at the 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC 2016 - ECCE Asia), Hefei, China: IEEE. https://doi.org/10.1109/IPEMC.2016.7512793
Su, R. Y., Yang, F. J., Tsay, J. L., Cheng, C. C., Liou, R. S., & Tuan, H. C. (2010). State-of-the-art device in high voltage power ICs with lowest on-state resistance. In 2010 International Electron Devices Meeting (p. 20.8.1-20.8.4). Presented at the 2010 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE. https://doi.org/10.1109/IEDM.2010.5703403
Yang, F.-J., Gong, J., Su, R.-Y., Huo, K.-H., Tsai, C.-L., Cheng, C.-C., et al. (2013). A 700-V Device in High-Voltage Power ICs With Low On-State Resistance and Enhanced SOA. IEEE Transactions on Electron Devices, 60(9), 2847–2853. https://doi.org/10.1109/TED.2013.2273573
Synopsys, Sentaurus Device User Guide:Version T-2022.03, March 2022.
Moens, P., Bauwens, F., Baele, J., Vershinin, K., De Backer, E., Sankara Narayanan, E. M., & Tack, M. (2006). XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit. In 2006 International Electron Devices Meeting (pp. 1–4). Presented at the 2006 International Electron Devices Meeting, San Francisco, CA: IEEE. https://doi.org/10.1109/IEDM.2006.346933
Xia, C., Cheng, X., Wang, Z., Xu, D., Cao, D., Zheng, L., et al. (2014). Improvement of SOI Trench LDMOS Performance With Double Vertical Metal Field Plate. IEEE TRANSACTIONS ON ELECTRON DEVICES, 61(10).
Wei, J., Luo, X., Zhang, Y., Li, P., Zhou, K., Zhang, B., & Li, Z. (2016). High-Voltage Thin-SOI LDMOS With Ultralow ON-Resistance and Even Temperature Characteristic. IEEE Transactions on Electron Devices, 63(4), 1637–1643. https://doi.org/10.1109/TED.2016.2533022
Guo, Y., Yang, K., Chen, J., Li, M., Jiang, Z., Yao, J., et al. (2023). Tradeoff Between the Breakdown Voltage and Specific On-Resistance of SOI RESURF LDMOS. In 2023 IEEE 15th International Conference on ASIC (ASICON) (pp. 1–4). Presented at the 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China: IEEE. https://doi.org/10.1109/ASICON58565.2023.10396435
Wei, J., Ma, Z., Luo, X., Li, C., Deng, G., Song, H., et al. (2021). Experimental Study of Ultralow On-resistance Power LDMOS with Convex-shape Field Plate Structure. In 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) (pp. 87–90). Presented at the 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan: IEEE. https://doi.org/10.23919/ISPSD 50666.2021.9452231
Carrillo-Nunez, H., Dimitrova, N., Asenov, A., & Georgiev, V. (2019). Machine Learning Approach for Predicting the Effect of Statistical Variability in Si Junctionless Nanowire Transistors. IEEE Electron Device Letters, 40(9), 1366–1369. https://doi.org/10.1109/LED.2019.2931839
Mehta, K., & Wong, H.-Y. (2021). Prediction of FinFET Current-Voltage and Capacitance-Voltage Curves Using Machine Learning With Autoencoder. IEEE Electron Device Lett., Article vol. 42, no. 2, pp. 136-139, Feb 2021, doi: 10.1109/led.2020.3045064.
Han, S.-C., Choi, J., & Hong, S.-M. (2021). Acceleration of Semiconductor Device Simulation With Approximate Solutions Predicted by Trained Neural Networks. IEEE Transactions on Electron Devices, 68(11), 5483–5489. https://doi.org/10.1109/TED.2021.3075192
Wang G., Wang S., Ma L., Wang G., Wu J., Duan X., Chen S., & Liu H. (2022) Optimization and Performance Prediction of Tunnel Field-Effect Transistors Based on Deep Learning. Adv. Mater. Technol. 2022, 7, 2100682. https://doi.org/10.1002/admt.202100682
Chen, J., Alawieh, M. B., Lin, Y., Zhang, M., Zhang, J., Guo, Y., & Pan, D. Z. (2020). Automatic Selection of Structure Parameters of Silicon on Insulator Lateral Power Device Using Bayesian Optimization. IEEE Electron Device Letters, 41(9), 1288–1291. https://doi.org/10.1109/LED.2020.3013571
Huang Yi, Sun Shiyu, Duan Xiusheng, & Chen Zhigang. (2016). A study on Deep Neural Networks framework. In 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC) (pp. 1519–1522). Presented at the 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), Xi’an, China: IEEE. https://doi.org/10.1109/IMCEC.2016.7867471
Shahriari, B., Swersky, K., Wang, Z., Adams, R. P., & De Freitas, N. (2016). Taking the Human Out of the Loop: A Review of Bayesian Optimization. Proceedings of the IEEE, 104(1), 148–175. https://doi.org/10.1109/JPROC.2015.2494218
Chen, J., Guo, X., Guo, Y., Zhang, J., Zhang, M., Yao, Q., & Yao, J. (2021). Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate. Japanese Journal of Applied Physics, 60(7), 077002. https://doi.org/10.35848/1347-4065/ac06da
Chuang, P.-J., Saadat, A., Van De Put, M. L., Edwards, H., & Vandenberghe, W. G. (2023). Algorithmic Optimization of Transistors Applied to Silicon LDMOS. IEEE Access, 11, 64160–64169. https://doi.org/10.1109/ACCESS.2023.3287204

No competing interests reported.

Download PDF

Editorial decision: Revision requested
30 Aug, 2024
Reviews received at journal
10 Aug, 2024
Reviewers agreed at journal
01 Aug, 2024
Reviewers agreed at journal
01 Aug, 2024
Reviewers invited by journal
27 Jul, 2024
Editor assigned by journal
07 Jul, 2024
Submission checks completed at journal
07 Jul, 2024
First submitted to journal
06 Jul, 2024

You are reading this latest preprint version

An Ultra-Fast and Precise Automatic Design Framework for Predicting and Constructing High-Performance Shallow-Trench-Isolation LDMOS Device

Status:

Version 1

Abstract

Figures

1 Introduction

2 Methods

2.1 A TCAD Simulation and Electrical Characteristics of Device

2.2 Automatic Design Framework

3 Experimental Results and Discussions

3.1 Performance analysis of proposed DNN Model

3.2 Performance analysis of proposed design framework

4 Conclusion

Declarations

References

Additional Declarations

Status:

Version 1