Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N + heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.


Introduction
The electronics industry has been greatly influenced since the remarkable technological invention of Integrated Circuits. In 1965, Moore predicted the pace of upcoming revolution in modern digital era, which became the golden rule for electronics industry. To keep up with the Moore's law, the electronics industry has been working to make faster, affordable and smaller transistors that would drive our modern digital gadgets. The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which was first invented in 1959 at Bell Labs, has been attempted to scale down for the past 50 years in order to attain high density, performance and cost-effectiveness [1,2]. However, Short channel effects (SCE) [3] are introduced due to scaling down of MOSFET [4] which adds to the already existing limitation of threshold voltage (V TH ), high Off-state Current (I OFF ) [5] and Sub-Threshold Swing (SS) (60 mV/ dec) [6]. MOSFET-based nano-devices are more susceptible to SCE and it is difficult to attain Saturation of drain current due to the ballistic effect of charge carriers [7]. TFETs [8,9] have shown potential to be considered as a capable alternative as they outperform MOSFET [10] in terms of SS, VTH and IOFF [11]. This is made possible due to the mechanism of TFET i.e., Band to Band Tunnelling, which increases the On to Off State Current ratio (ION/IOFF) as compared to Thermionic emission in MOSFET. This also breaks the limitation of MOSFET by achieving a SS lower than 60 mv/dec. However, TFETs offer low ON-state current due to the tunnelling inefficiency [12]. Abrupt junctions are effective in tunnelling but a high-temperature process is required to create these. [13]. To resolve these issues, Charge Plasma (CP) technique can be used.
The objective is to achieve high Ion, low V T , reduce cost and overcome the shortcomings of Conventional TFETs. Therefore, in this paper, a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor is being introduced which has a p-n-p-n configuration. Doping-less structure are more economical and defect-free [9]. There are two ways to induce doping in the intrinsic substrate which are Electrostatic and Charge Plasma (CP)Technique. The proposed device is based on CP technique as it also resolves the problem of the Abrupt Doping Profile. CP technique utilizes Electrodes having suitable work-function to induce p-doped Source and n-doped Drain regions [14]. Vertical Nanowire [15] eases the device fabrication process compared to axial nanowires [10]. The cylindrical-shaped GAA structure offers stronger electrostatic control of the charge carriers due to greater surface inversion which in turn increases the drain current. The p-n-p-n configured structure is similar to the p-i-n TFETS with a variation by introducing a n-pocket from the CP technique [16,17].

Device Architecture and Simulation Parameters
The 2D structures of the two devices, DL-V-NW-TFET with p-i-n and p-n-p-n configuration, are presented in Fig. 1(a) and (b) respectively. Similarly, the 3D structures for the same is represented in Fig. 1(c) and (d) respectively. Drain (D), Source (S), Gate(G), Channel, electrodes and oxide regions are indicated in the diagrams.
The proposed nanowire device is grown vertically on the SOI (Silicon on Insulator) wafer [12]. In this device, intrinsic Si with 7nm thickness, is used for Drain (D), Source (S), Channel regions. This is a Doping-less device, thus for fabricating the source and drain regions, Charge Plasma (CP) technique is adopted [15]. In this technique, metals with relevant work function are used as the drain/source electrode, as a result of which, generation of e − and h + is facilitated [18]. Table 1 illustrates the designing parameters used in the process. To create the Source (p + ) region, Platinum (work-function = 5.93 eV) is used as a source-metal. Similarly, Aluminium (work-function = 4.2 eV) is used as drain-metal to form drain (n + ) region. The aim of choosing Platinum and Aluminium for source and drain electrodes, respectively, is that for p-type doping in the source region, work-function electrode used for Source metal must be higher than that of intrinsic Si substrate. Similarly, in drain region, electrode work function of the drainmetal must be less than that of intrinsic Silicon, for n-doping [17]. Figure 1 clearly shows the placement of the aforementioned metal electrodes. Tungsten (work function = 4.5 eV) is used for the Gate metal electrode. The gate oxide thickness for both structures is 2 nm. SiO 2 makes up the oxide region surrounding the intrinsic silicon body in both devices. This use of SiO 2 facilitates the effortless process of deposition and feasibility of ultra-thin consistency settled above the surface of intrinsic silicon [12]. Channel length (L G ), Source length (L DS ) and Drain Length (L SD ) for the structure is 20 nm each. The doping concentration is 3 × 10 19 cm − 3 for the source (p) region, 2 × 10 19 cm − 3 for the drain (n) region and 10 19 cm − 3 for the channel region, for both the device configurations. Radius (R) of the nanowire is 7.5 nm. The p-n-p-n configuration of the device structure is similar to a TFET of pin structure. The only difference is that an N + pocket is induced between the Source (S) and channel region in the p-n-p-n configured device. For actualizing this, we use CP technique in which an electrode of suitable work-function is used to introduce n + doping near the interface of the source (S)-channel. By doing so, the tunnelling field is increased, which therefore increases I ON , and thus the device performance is improved when weighed up against p-i-n TFET [19]. The proposed device predominates the formation of the abrupt-junction [12]. For efficient tunnelling in the TFETs, an abrupt junction is required. However, this process is difficult and requires a high-temperature process which often diffuses dopant atoms into the channel from S/D regions. For this reason, we use CP technique in our work.
Models mentioned below are used to define the characteristics of the device and are used in the simulation. For the tunnelling of charge carriers through the device, BTBT model is used. SRH and AUGER models used help in calculating the generation and recombination rate of charge carriers. Various models like FLDMOB, CONMOB and CVT are used to calculate mobility dependence on electric field and charge concentration. Models like FERMI & NI.FERMI adhere to Fermi Dirac Statistics as charge carrier concentration may exceed the available density of states due to CP technique. BGN model is effective in taking into account the variation in energy bandgap that can occur due to heavy induced doping of S/D region. QUANTUM correction models help in analysing the feasible quantum effects in the device [12].

Results and Discussion
In our work, we have analysed the performance of our proposed device, p-n-p-n DLVNWTFET with the p-i-n structure and compared them for the two operating states, i.e., ON and OFF. Figure 2a and b respectively compare the simulated Energy Band diagrams of DLVNWTFET of p-i-n and p-n-p-n configuration. This comparison is made for both the OFF-state where (V GS = 0 V, V DS = 1.0 V) and ON-state where (V GS = 1.5 V, V DS = 1.0 V). In the OFF-state, the p-n-p-n configuration DLVNWTFET shows a reduced bandgap in the source region. When the device is working in on-state, the reduced bandgap at Source (S) side reduces the tunnelling width as seen in Fig. 2b. Introducing a pocket(N+) near the Source(S)-Channel interface helps in reducing the tunnelling width. The band is bent further at source junction because of pocketing in p-n-p-n configuration DLVNWTFET resulting in lowering of tunnel width, resulting in an increase in tunnelling probability at the interface of Source(S) and Channel, hence improving the device performance [20].  The Electric field plot of the DLVNWTFET of p-i-n and pn-p-n configuration along x-coordinate in I OFF and I ON are studied in Fig. 3a and b correspondingly. Electric field intensity can be seen to rise at the interface of Source & Channel and decrease towards the Drain-Channel interface. In p-n-p-n configuration, e − field intensity rises near the sourcechannel interface in contrast to that of p-i-n configuration, this happens because of the N-pocket induced by using CP technique. Since there is more bending of the band at source-channel interface (shown in Fig. 2a), this leads to a high electric field and probability of tunnelling at the source-channel interface hence the p-n-p-n is configured DLVNWTFET offers improved performance.
The electron concentration profiles of DLVNWTFET of pi-n and p-n-p-n configuration along x-coordinates in I OFF and I ON are represented in Fig. 4a and b, respectively. Required electron concentration is achieved with the use of suitable S/D metal work function by using the charge plasma technique. In p-n-p-n configuration, e − concentration is higher at the interface of source and channel as compared to that of p-i-n configuration, this indicates the introduction of N pocket by the usage of CP technique. Figure 5 shows the I D -V GS characteristics of the DLVNWTFET of p-i-n and p-n-p-n configuration. From the graph, we can conclude that p-n-p-n configuration DLVNWTFET offers a higher I D and has a lower threshold voltage and steeper curve in contrast to p-i-n configured DLVNWTFET. It is observed that the I ON is improved, keeping the I OFF unaffected in the p-n-p-n configured TFET. The rise in I D is observed because of the use of CP technique near the source-channel region, which introduces a N-type pocket that improves the electron concentration, bends the bandgap more near the Source-channel junction lowering the tunnelling width and increasing the tunnelling probability which therefore increases drain current for lower gate voltages and enhances the I ON of the device, as represented in Fig. 5. With this, we conclude that p-n-p-n structure offers a higher I ON (i.e., I ON = 8.86653 × 10 − 6 A/µm) and is switched on at a lower gate voltage (i.e., Vt = 0.372621 V).
Transconductance (G m ) showcases the ability to amplify and hence is a crucial factor in the designing of analog circuits (like amplifiers). It is illustrated as the slope of I D -V GS curve and is calculated by the formula given below: The comparison of Transconductance for the DLVNWTFET of p-n-p-n configuration and p-i-n configuration is shown in Fig. 6. These results conclude that the proposed p-n-p-n TFET is desirable as it shows a steeper Gm slope in relation to p-i-n configured DLVNWTFET. Higher Gm corresponds to higher drain current at lower V GS making the device energy efficient at a lower value of V G , which is a crucial factor in analog applications using low power.
Total Gate capacitance (C GG ) is the addition of gate-tosource capacitance (C GS ) and its gate-to-drain capacitance (C GD ). The charges which are present in the channel region of the device, responsible for generating these capacitances. This is useful in predicting the switching speed and determines the power depletion of the TFET. C GS depends on the concentration of the electrons present in the source region, while C GD depends on the concentration of the electrons present in the drain region. Figure 7 shows the comparison of C GG for both p-n-p-n and p-i-n TFETs. Lower C GG corresponds to higher cutoff frequency (fT) as they are inversely proportional to each other (shown in Eq. 2). Therefore p-n-p-n configured TFET having lower C GG showcases improvised performance in contrast with p-i-n TFET.  The highest frequency which can be achieved by a device is referred to as Cut-off frequency(f T ). It can be calculated using the formula given below: Higher fT is used in RF applications. Figure 8 shows that f T is higher for the p-n-p-n configured TFET as compared with the p-i-n configuration, due to the higher transconductance (f T is directly proportional to Gm) as shown in Fig. 6.
In p-n-p-n DLVNWTFET in Figs. 6 and 7, there is a surge in Gm while a contraction in C GG , and this is significantly due to the inducing of N pocket, by CP technique in contrast to p-i-n DLVNWTFET. Because of this, there is an increase in the cutoff frequency p-n-p-n TFETs which can be observed from Fig. 8. Figure 9(a) depicts the output characteristics I D -V DS of both DLVNWTFETs at V GS =1.0 V. These results clearly help in understanding that p-n-p-n configured TFET saturates at a higher drain current at (~9 × 10 − 6 A/ µm) whereas drain current is about (~3 × 10 − 6 A/µm) for p-i-n).
Representation of Output conductance (G d ) is done in Fig. 9(b). Gd is extracted from I D −V DS curve ( Fig. 9(a)). Gd is dependent on the operating state of the device. In the linear region, its value is high but as the V DS increases, Gd starts decreasing. In the saturation region, Gd lowers down to the lowest value. The p-i-n DLVNWTFET exhibits low G d in comparison to the proposed device.
G d is an essential factor because the intrinsic gain of a device is dependent on it. Lower G d and higher G m are needed for high intrinsic gain Fig. 10.

Intrinsic gain ¼
Gm Gd at the same voltages ð Þ ð 3Þ From the above results, we can infer that p-n-p-n DLVNWTFET is better for analog applications, as it gives high value of gain in contrast to the p-i-n DLVNWTFET.

Conclusion
In this paper, p-n-p-n Doping-less Vertical Nano-wire Tunnel Field Effect Transistor has been proposed and compared with the p-i-n configuration of the same device. Charge Plasma technique has been used throughout in the formation of this device. In the p-n-p-n configuration, the N pocket has been induced without the need of separate implantation through CP technique. Upon the completion of device performance analysis, we can conclude that the proposed DLVNWTFET in pn-p-n configuration offers the highest ON-State current, I ON -I OFF ratio, G m , cut-off frequency and intrinsic gain amongst all the TFETS considered in Table 2, given above. The p-n-p-n configured DLVNTFET device has reduced Vth and SS avg which is the least value in comparison to all the devices considered in table. In the analog performance analysis, we have seen the p-n-p-n shows better performance in contrast to the pi-n structure DLVNWTFET like steeper I D -V GS curve and higher I ON due to better electron concentration, increased intensity of electric field and reduced bandgap near the Source-Channel interface. So, on the basis of the performance analysis of this device proposed in this work, we can conclude that the performance of DLVNWTFET is better than other devices we have referred.