Numerical simulations of carrier-selective contact silicon solar cells: Role of carrier-selective layers electronic properties

Ag/ITO/MoOx/n-Si/LiFx/Al carrier-selective contact (CSC) solar cell structures are modelled and numerically simulated based on the experimental data using an industrial quality base silicon wafer by the Sentaurus TCAD software. The role of (1) electron-selective lithium fluoride (LiFx) layer and its thickness, (2) hole-selective molybdenum oxide (MoOx) work function variation, and (3) front contact (MoOx/n-Si) surface passivation interlayer are explored on the device performance. The electron-selective LiFx layer at the rear side is led to the substantial enhancement in device photocurrent by providing the electrical barrier to the minority carriers (holes) and a slight improvement in open-circuit voltage, but the thickness of the layer is sensitive to efficient extraction of the majority carriers (electrons). The hole-selective MoOx layer work function needs to be engineered for inducing the strong inversion layer with better built-in potential at the MoOx/n-Si junction to achieve high open-circuit voltage from a cell. A thin SiOx interlayer at the MoOx/n-Si junction has significantly enhanced the device’s open-circuit voltage by minimizing the minority carrier recombination at the interface.


Introduction
Carrier-selective contact (CSC) silicon solar cells are presently getting attention as an alternative to conventional silicon heterojunction (SHJ) cells due to simple fabrication, low parasitic absorption from carrier-selective layers, and high-efficiency potential [1][2][3][4]. CSC solar cells rely on widebandgap transition metal oxides (TMOs) for charge carrier extraction, where high work function (WF) materials such as molybdenum oxide (MoO x ), vanadium oxide (V 2 O x ) and tungsten oxide (WO x ) are employed as hole-selective layers [3,5,6], and low WF materials such as lithium fluoride (LiF x ), magnesium fluoride (MgF x ), and titanium oxide (TiO x ) are used as electrons-selective layers [7][8][9][10]. The carrier selectivity in CSC cells happens through asymmetric energy band alignment of different TMOs with the c-Si; the difference in WF between TMOs and c-Si produces both extraction of charge carriers and field-effect surface passivation [11,12].
Apart from experimental effort, the modelling and simulation studies have been carried out on CSC solar cells to visualize the role of the interface and bulk defect states on carrier recombination and transport mechanisms (band-toband or trap-assisted tunnelling) [11,13,14]. A few research reports on the role of back (electron-selective) contact of CSC cells are available such as Vijayan et al. [12] showed the improvement in surface passivation and electron selectivity from TiO x layer along with LiF x /Al stack by using Sentaurus device simulator. LiF x alone has also been used as an electron-selective layer due to its simple fabrication process to produce a low resistive path to electrons collection at the rear side of the CSC cell as LiF x /Al stack [8]. Usually, a thin intrinsic amorphous silicon (i-a-Si:H) layer is used as an interface passivation layer on both conventional and CSC-based SHJ cells. However, a thin SiO x interlayer can also be used as an alternative passivation layer [15,16].
In this work, we have investigated the CSC cells' performance with the device structure Ag/ITO/MoO x /n-Si/LiF x / Al using the Sentaurus TCAD simulation. This work highlights the role of LiF x layer with its thickness in the electronselective back contact (n-Si/LiF x /Al). The study emphasizes the importance of MoO x work function in the hole-selective contact (MoO x /n-Si) and the SiO x layer on chemical passivation at the front contact. The simulated energy band diagrams at both the contacts are considered for explaining the carrier transport barrier at the interfaces and the light J-V graphs in device performance. Based on our earlier reported experimental observations [17], the numerical simulation parameters are considered to validate the simulated energy band diagrams and light J-V graphs.

Simulation details
The numerical solutions of Poisson, drift-diffusion and carrier continuity equations are solved in a self-consistent approach. Various physical models have been invoked to analyze CSC solar cell's terminal characteristics accurately using Sentaurus TCAD software [18]. The thermionic emission model is employed at heterojunction interfaces, which defines the thermionic current and thermionic energy flux better at these abrupt junctions. The recombination of carriers is modelled by Shockley-Read-Hall (SRH) model that includes recombination through defects levels within the bandgap. The surface recombination velocity model is used at the c-Si surface to explore the effect of chemical passivation in the solar cell. The constant mobility model is used in c-Si as the concentration of carriers is low. In addition to these models, the tunnelling (intraband and band-to-band) models have also been used to define the carrier transport at heterointerface and a thin insulator (such as SiO x and LiF x ). Here, the robust non-local tunnelling model based on the Wentzel-Kramers-Brillouin (WKB) tunnelling probability is used.
The optical generation model based on the complex refractive index of materials is taken to compute the generation from the input spectrum of wavelength. Here, we have employed the standard AM1.5 global as the input spectrum to calculate the J-V curve under the illumination. The transfer matrix method (TMM) has been used as an optical solver to calculate plain waves' propagation through layer media (materials). The complex refractive indices (n and k) of materials have been obtained from the Sentaurus database and PV Lighthouse [19]. The schematic and energy band diagram of simulated CSC solar cell is shown in Fig. 1a and b, respectively. The material parameters used for the device simulation are tabulated in Table 1.

Results and discussion
3.1 Role of electron-selective contact on cell performance Figure 2a and b show the light J-V graphs and energy band diagrams of CSC cells with and without LiF x interlayer at the electron-selective back contact. The cell with LiF x structure shows an increase in efficiency by ~ 2% due to an improvement in V oc and J sc by ~ 20 mV and ~ 3 mA/cm 2 , respectively. The characteristics of both the J-V graphs are the same (Fig. 2a); however, the cell with LiF x (Fig. 2b) shows a downward bending in conduction and valance bands along with the better quasi fermi-level splitting. Due to the low WF, the LiFx layer facilitates the downward band bending at CSC cell's rear contact between the c-Si and Al. The band bending at the n-Si surface leads to the generation of an electric field, which provides an energy barrier for the holes (minority) at the interface and reduces the carrier recombination with the electrons (majority carriers). Also, the band bending produces field-effect passivation by creating an imbalance in charge carrier (electron/ hole) concentration due to the repulsion of holes at LiF x / Al interface by enhancing the minority carrier diffusion length within the bulk n-Si, which also led to an increase in J sc of ~ 3 mA/cm 2 from the cell [17]. An increment in V oc (~ 20 mV) is observed due to the significant minority carrier density with the better quasi fermi-level splitting. However, in our experimental results, an improvement of ~ 25 mV in V oc is observed [17]; the deviation from the experimental value can be because of other layers, which are not well calibrated. Also, a minor shunting effect due to the cell area is noted in the experimental J-V graphs, which is not considered in the numerical simulation. It is worth mentioning here that the effect of traps is not considered in this simulation study. However, the field-effect passivation can be expected due to downward band bending at the Si/ LiF x interface [6,20]. The LiF x interface also reduces the fermi-level pinning at the c-Si surface, which is the case with the direct contact of Al with the n-Si wafer [21]. The thin LiF x interlayer capped with Al contact can also reduce the contact resistivity to some extent [6].
The collection of electrons happens from the rear side through carrier tunnelling, which is very sensitive to layer thickness [8]. Figure 3a and b show the J-V curves of cell and band diagrams of c-Si/LiF x /Al structure for different LiF x layers'' thicknesses. The width of the tunnel barrier for charge carriers is very sensitive to LiF x thickness, increasing LiF x thickness (from 1 to 2.5 nm) and can be seen from Fig. 3b. For LiF x thickness < 2.5 nm, the J-V curve does not show any change in its characteristics. However, a distortion in the shape of J-V characteristic is observed for LiF x thickness ≥ 2.5 nm due to increased resistance to electrons from the cell's backside. The J-V curve deviates from its original shape, indicating an increase in series resistance, which lowers the cell's FF by 8% and efficiency by ~ 2%. The n-Si conduction band bending also reduces with an increase in LiF x thickness due to an accumulation of electrons at the rear interface. An upward band bending results at the MoO x /c-Si interface due to carrier inversion at the c-Si surface because of the significant difference in WF between MoO x and c-Si, further enhanced with the SiO x interlayer. The upward bending enhances the holes collection and simultaneously provides an electron blocking field (due to carrier inversion) at the front contact. The enhanced field with the SiO x interlayer lowers the flow of electrons to the front contact and therefore reduces the charge carrier recombination with the better chemical passivation on the front c-Si surface. The recombination of carriers is proportional to the accessibility of both the charge carriers (electrons and holes) [22]. Thus, the SiO x interlayer accompanied by the MoO x hole-selective layer shows better performance due to the combined chemical and field-effect passivation. This effect has led to enhancing the V oc from 575 to 632 mV in the cell. Due to the insulating nature of SiO x , a spike in the band diagram is noted at the MoO x /c-Si interface (Fig. 4b), which will allow the hole and can hinder the electron transport [23]. Also, the band offset significantly reduces the interface recombination and improves the shows the cells' photovoltaic parameters, EF n and EF p represent the electron and hole quasi fermi-levels in the c-Si energy bandgap under illumination condition device performance [24]. The thickness of SiO x should not be greater than the tunnel barrier limit (~ 2 nm) so that the carriers can tunnel (band-to-band or hopping through traps) the interfacial barrier [25]. Also, the SiO x interlayer's uniformity is essential for achieving the uniform chemical passivation of the c-Si surface by suppressing most of the silicon dangling bonds.

Effect of MoO x work function on front contact of cell performance
To investigate the MoOx layer's WF role, the device is simulated for a range of varying WF (from 4.80 to 6.70 eV). The simulated J-V graphs of cells and energy band diagrams of the MoO x /n-Si junction with different MoO x WF are shown in Fig. 5a and b, respectively. The corresponding photovoltaic parameters are presented in Table 2. The MoO x /c-Si junction is taken as the Schottky contact due to a significant WF difference between the MoO x and n-Si, which gives rise to upward band bending in the energy bandgap on the front c-Si surface [3].
With decreasing of the MoO x layer's WF, the reduction in band bending is observed (Fig. 5b). The low band bending cannot produce a significant field to block the electrons and thus promotes the carrier recombination at the MoO x /c-Si interface with the photogenerated minority carrier (holes) [11]. Also, the low band bending hinders hole transport and increases the device resistance. However, in the case of higher MoO x WF (> 6 eV), the carrier transport at the MoO x /c-Si interface happens through band-to-band tunnelling [12,13]. Also, a large hole concentration is induced at the interface, which inverts the charges' polarity at the c-Si surface. As a result, the hole conductivity increases, provides better selectivity, and leads to high V oc . The decrease in MoO x layer's WF can be expected due to increase in the oxygen vacancies and also annealing temperature [26,27].   For the mid-range of MoO x WF (5.0 eV < WF < 6.0 eV), the carrier transport happens through trap states that exist in the MoO x bandgap [14], which also can provide the low resistive path to electronic transportation. However, with the low value of the MoO x layer's WF < 5.0 eV, a hole transport barrier is observed, hindering the hole selectivity by MoOx layer and producing an S-shape in J-V curves degrades the performance of the CSC solar cells [28]. Further improvement in the device efficiency can be visualised by employing a high-quality c-Si wafer. Figure 6 shows the simulated J-V curves under illumination with different c-Si bulk lifetimes, an enhancement in V oc is apparent with an improvement in the bulk lifetime of the n-Si wafer from 300 to 1500 µs. As a result, the device power conversion efficiency reaches ~ 20% with V oc of > 700 mV. So, the overall performance of the CSC solar cells can be fine-tuned by good bulk lifetime values as well as with a better c-Si surface passivation quality.

Conclusions
For Ag/ITO/MoO x /n-Si/LiF x /Al solar cell, the LiF x interlayer is verified as an efficient electron-selective layer compared to direct Al contact on the c-Si back contact. LiF x /Al back contact's field effect is observed with downward band bending in simulated band diagram, which is reflected in the better performance of CSC cells. The carrier tunnelling length is limited by ~ 2 nm LiF x layer, further increase in thickness is reduced field-effect passivation with the minimal conduction band bending. The improvement in CSC cells' performance has also been observed with a thin SiO x interlayer due to a significant reduction of surface recombination. The role of hole-selective front contact in carrier recombination and transport mechanisms is analysed by varying MoO x 's work function in three different ranges (high, medium, and low). The hole collection barrier is observed with the low work function of MoO x layer (< 5.0 eV). These numerical simulations can provide some information on the electronic properties of carrier-selective layers apart from the critical role of the base silicon wafer's surface passivation and bulk lifetime.